Large-scale multi-channel extensible parallel high-speed control system

Abstract

A large-scale multi-channel extensible parallel high-speed control system comprises an upper computer module, a master-slave control module and an analog switch matrix module. The upper computer module operates control software, generates a control instruction, configures parameters and a scheduling strategy, and issues the instruction to the main control module through a high-speed communication interface; meanwhile, the state information and the collected data uploaded by the main control module are received, and are used for real-time monitoring and operation interface display; the master-slave control module is a core scheduling and execution layer of the system, is provided with the upper computer module on the upper part and is connected with the analog switch matrix module on the lower part; the analog switch matrix module is a final physical execution layer and directly acts on the novel large-scale antenna system; according to the invention, the scale of the control ports can be greatly improved through cascade regulation and control of the large-scale parallel output ports of the FPGA and the analog switches. The analog switch outputs control signals in a high-speed switching mode, and meanwhile the higher load characteristic of the analog switch further improves the output driving capacity of the control system.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of new large-scale antenna systems, and particularly relates to a large-scale multi-channel scalable parallel high-speed control system. BACKGROUND

[0002] New large-scale antenna systems (such as reconfigurable reflective arrays, reconfigurable transmissive arrays, intelligent reconfigurable super surfaces, etc.) are usually composed of periodically arranged adjustable array units. By adjusting the electromagnetic response state of the array units, the spatial electromagnetic channel can be flexibly reconfigured. However, the current new large-scale antenna systems require independent and high-speed adjustment of each array unit, and the existing control system architecture cannot achieve large-scale and fast control, and the scale of the control channel cannot be further expanded.

[0003] New large-scale antenna systems realize multi-beam dynamic shaping and high-speed spatial multiplexing communication functions, and have significant application value in emerging scenarios such as 6G near-field communication, intelligent Internet of Things, and low-orbit satellite networking. Among them, the control system as the core sub-module of the new large-scale antenna system determines the electromagnetic adjustment response rate, the adjustment unit scale and the overall power consumption performance of the system. At present, the mainstream control system is mostly based on a centralized serial control architecture, which uses MCU + SPI control bus combined with timing driving method to adjust each point of the phased unit. However, this architecture has problems such as limited bus bandwidth, high response delay, and difficulty in synchronous control in high channel density applications, which cannot meet the needs of ultra-large-scale arrays in microsecond-level response speed and thousand-level unit synchronous adjustment.

[0004] In the existing new large-scale antenna system, the control system usually adopts a design method based on a centralized serial control architecture, mainly by an MCU or a special control chip sending control signals to each antenna adjustment unit through a SPI / I 2 C and other serial buses. However, as the antenna scale expands from dozens of units to hundreds or even thousands of units, this architecture exposes obvious technical defects in the following aspects:

[0005] (1) Due to the limited bus bandwidth, control information needs to be transmitted one by one, and as the number of control units increases, data congestion is significant, which leads to prolonged system control response time and increased system delay.

[0006] (2) In the case of serial control, the timing is complex and the synchronization is poor. The control logic needs to rely on timing to cascade step by step, so there will be differences in response time between different units, making it difficult to achieve large-scale synchronous control.

[0007] (3) The current control system is subject to poor expandability of circuit structure and low utilization rate of hardware resources, making it difficult to flexibly adapt to different antenna topologies. SUMMARY

[0008] In order to overcome the deficiencies of the prior art, the purpose of the present application is to provide a large-scale multi-channel scalable parallel high-speed control system, which can greatly improve the scale of the control port through the large-scale parallel output port of the FPGA and the cascade regulation and control of the analog switch.

[0009] In order to achieve the above purpose, the technical solution adopted by the present application is:

[0010] A large-scale multi-channel scalable parallel high-speed control system, comprising a host computer module, a master-slave control module and an analog switch matrix module.

[0011] The host computer module is the instruction source and management center of the entire system, runs control software, generates control instructions, configuration parameters and scheduling strategies, and the PC end or other devices transmit the instructions to the master control module through a high-speed communication interface; at the same time, it receives the state information and collected data uploaded by the master control module, and realizes real-time monitoring and operation interface display.

[0012] The master-slave control module is the core scheduling and execution layer of the system, which is connected to the host computer module above and the analog switch matrix module below; the master-slave control module comprises a master control module and a plurality of slave control modules; the master control module receives the host computer module instructions through the internal FPGA module, performs task analysis, timing scheduling, and transmits the allocated control data to each slave control module; the slave control module performs specific channel control operations according to the instructions issued by the master control module, and feeds back the execution results or state to the master control module; a plurality of slave control modules are extended in a daisy chain mode to realize parallel expansion of a large number of channels.

[0013] The analog switch matrix module is the final physical execution layer, which directly acts on the new large-scale antenna system; the analog switch matrix module is directly connected to the slave control module, which is used to realize high-speed switching and signal routing in the actual physical channel, receives the driving signal from the slave control module, realizes independent or synchronous switching of hundreds to thousands of channels to realize the operation of turning on and off the switch matrix, supports flexible connection between multiple signal sources and loads, and meets the operation requirements of the new large-scale antenna system.

[0014] The host computer module is located at the top layer of the entire system, and communicates with the master control module through USB3.0 or serial port; the user transmits system configuration instructions to the master-slave control module, completes the control of the analog switch on and off logic state, the setting of the register timing channel of the internal logic of the FPGA module, and enables the channel switch.

[0015] The host computer module comprises a control interface GUI, a communication driver layer, a data analysis module, a database and a device management module; the control interface GUI is made of visual buttons, input boxes and icons by Python or Matlab, and is used as an operation interface for human-computer interaction to input required instructions;

[0016] The communication driver layer relies on UART serial ports, USB communication and IP communication to realize transmission of communication data, the UART serial port communication transmits data bit by bit through a single data line; the USB communication is a high-speed serial bus standard, supports communication between a host and multiple devices, and adopts a layered protocol stack; the IP communication is network communication based on an IP protocol stack, and supports global interconnection;

[0017] The data analysis module decodes, formats and extracts original data uploaded by the master-slave control module, converts low-layer original data into structured information (such as channel state, switching result, timing delay, etc.), and provides the structured information for real-time display by the control interface GUI, while supporting abnormality detection and preliminary analysis of the data to assist users in judging system operation status; the database is used to store historical instructions, state data, measurement results and user configurations during system operation, supports data query, retrieval and comparison, and is convenient for long-term trend analysis and repetitive experiments, and is linked with the control interface GUI to realize historical data playback and statistical chart display;

[0018] The device management module is used to uniformly manage the accessed master-slave control modules, including device registration, identification, state monitoring and resource allocation, supports online or offline detection and automatic reconnection of the devices, ensures reliability and scalability of the system, provides a device mapping table, and enables users to directly operate corresponding physical devices and channels through a logical channel number on the control interface GUI.

[0019] The master-slave control module comprises an FPGA module, a memory unit, a power module, a daisy chain, a UART module, a USB module and a clock synchronization module;

[0020] The memory unit and the FPGA module interact with each other in data and instructions, the power module supplies power for the FPGA module, the USB module and the UART respectively provide interfaces for the FPGA module and interact with the host computer module, the clock synchronization module provides a global clock for the FPGA module to ensure that the timing of the instructions issued by the FPGA module is aligned, and the daisy chain enables the FPGA module to realize interaction and expansion of multiple boards.

[0021] The FPGA module is a core control unit of the system, connects the host computer, the memory unit and the daisy chain, and is a central controller for completing command analysis, protocol communication, state synchronization and data scheduling in the system;

[0022] The FPGA module includes logic cells, IO pins, embedded BRAM, clock resources, DSP modules, hard core interfaces, and a JTAG debugging interface; the logic cells are basic programmable logic blocks used to implement various logic combinations and sequential logic; the IO pins are responsible for communication with peripherals; the embedded BRAM is used as a built-in storage module for image caching and storing data in processing; the clock resources are used to generate and synchronize clocks, to realize synchronous mobilization between modules; the DSP module is a dedicated multiplier and adder, to accelerate digital signal processing; the hard core interface is an integrated high-speed peripheral controller, which is a bridge for high-speed communication with the host computer, and is commonly a PCIe controller and a USB peripheral; the JTAG debugging interface is used for online code burning and internal signal capture, to complete online debugging and verification.

[0023] The clock resources generate clocks to drive global work; the logic cells, as the core, cooperate with the embedded BRAM and the DSP module to complete complex operations or data access; the logic cells are connected with the IO pins and the hard core interface to drive external signal input and output; the JTAG debugging interface directly communicates with the internal logic cells of the FPGA to provide debugging and configuration support.

[0024] The memory unit is used to realize data caching, configuration saving, and state register, and includes Flash, EEPROM, and SRAM;

[0025] The Flash is a non-volatile memory, and data is not lost after power failure, and is used for configuration data and program firmware storage; the EEPROM is commonly used for saving small amount of configuration parameters; the SRAM is a high-speed volatile memory, and data is lost after power failure, and is used for temporary data caching;

[0026] When the system is powered on, the solidified program and large-scale configuration data in the Flash are loaded to the SRAM, for initializing logic and fast running; during system running, the FPGA module can read and write the EEPROM at any time, for saving and restoring key configuration parameters; the SRAM exchanges data with the main logic of the FPGA module in real time, to undertake the functions of caching and register during running;

[0027] The control command issued by the upper computer module is first stored in the memory unit, and then read and executed by the FPGA module in sequence; the FPGA module also stores data and logs in the memory unit, for facilitating debugging and maintenance.

[0028] The power module provides stable power supply of different voltage levels; the power module converts the input voltage of 12V of the entire circuit system into 5V through AC / DC; the DCDC voltage reduction plate block in the power module converts the 5V voltage into 3.3V to supply power for the EEPROM and the analog switch; the voltage required by the low-power IO level is 1.8V, and the power module also converts 3.3V into 1.8V.

[0029] The daisy chain is a module series connection mode, one of the control modules is selected as the master module, and the other control modules are slave modules, the clock signal (SCK) and the chip selection signal (NSS) of all sub-boards are directly connected with the master module, when the master module sends data, the data synchronization clock signal is sent to all slave modules, when the chip selection signal of the slave module is low, the data is sent to the slave module through the master send slave receive (MOSI), the selected slave module will respond to the result through the corresponding master receive slave send (MISO) to the next slave module, when the chip selection signal is pulled high, the slave module stops working and waits for the next chip selection. This ensures that multiple modules can execute control logic at the same time, in addition, it breaks the defect that the hardware of the circuit itself cannot be expanded, and a number of slave modules can be added, greatly improving the expandability of the system.

[0030] The UART module realizes the interaction between the host computer module and the FPGA module, the UART module is a serial asynchronous communication protocol, which completes communication through TX (transmit data) and RX (receive data) two lines, each communication is carried out in the form of a frame, each frame contains: start bit, data bit, check bit and stop bit;

[0031] The start bit is low, the data is 8 bits, the check bit is selected to have or not to have, and the stop bit is high.

[0032] The USB module includes a USB controller, an interface circuit and a driving logic; the USB controller is a hardware implementation unit of the USB protocol, which is divided into a host controller and a device controller, respectively located on the host computer unit (computer) and the peripheral (FPGA module), the interface circuit is a USB physical layer interface, commonly known as a type C interface, etc., and the driving logic is an internal logic interaction with the FPGA module; the USB is a hardware interface standard, which defines the data transmission mode between the computer and the external device, including the physical interface (plug / jack), the electrical characteristics and the USB communication protocol; the USB communication protocol is a rule set for the interaction between the USB device and the host, which includes enumeration, data transmission mode and transaction definition; the enumeration is to identify the device type and capability of the host computer, the data transmission mode is divided into control output, batch output, interrupt output and isochronous output, which is the mode of different data transmission of USB, and the transaction definition is that the host initiates a request and the device responds; the USB is a large framework, the USB communication protocol is the rule of communication, the USB controller is the hardware for executing the USB communication protocol, and the USB module is a functional unit containing the USB controller and the interface, which is used to complete the specific communication.

[0033] The USB module is an important communication unit possessed by the master module and the slave module, and the core role is to realize data communication and management interaction with the host computer module or other modules; the USB communication protocol initiates all communications for the host computer, the device responds to the host request, after power-on, the device is connected to the host computer through the USB, the host computer identifies the device type through the USB enumeration, the USB controller in the device responds, completes the configuration, and the two parties interact data through the USB communication protocol.

[0034] The clock synchronization module realizes the timing alignment of command execution, data acquisition and synchronous triggering among multiple modules, ensures that the internal FPGA module works under the same reference clock, avoids data offset and logic inconsistency; when sharing the reference clock line, the master module sends the unified frequency clock to multiple slave modules through clock output, and the slave module receives the clock signal, synchronizes the internal logic operation and execution action, and ensures that all switches execute the command at the same time.

[0035] The analog switch matrix module completes the flexible switching, connection and isolation operation of the signal path; the essence of the analog switch matrix module is a semiconductor device, which determines the on-off state of the switch through the control end level, allows the signal to pass when the switch is on, and blocks the signal flow when the switch is off;

[0036] When the FPGA module sends a control signal to decide which switches are closed and which are open in real time, the analog switch matrix module responds to the control logic to complete the switching of the corresponding signal channel, achieving rapid switching of the order of microseconds, which is suitable for new large-scale antenna control systems.

[0037] The beneficial effects of the present application are:

[0038] The existing new large-scale antenna system usually adopts the method that the MCU or special control chip sends control signals to each antenna control unit through SPI / I 2 C and other serial buses, the present application uses FPGA parallel port output to replace the serial bus, so that each control unit can receive control instructions at the same time, eliminate the delay of serial transmission, and the control response time remains almost constant with the increase of the scale, the adaptability is also greatly improved, and the advantages of multi-channel high-speed control can be well achieved. Because of the reason of circuit architecture, the topology cannot be flexibly matched, and it is difficult to expand, the modularization of the control system structure can make each control board support the layout of different forms of antenna arrays, meet the demand of large-scale reconfigurable array in the future.

[0039] FPGA parallel control signal is directly driven by FPGAI / O to control unit, each control unit has independent data line, and all control units receive signals at the same clock edge, realizing full array synchronous signal update. Compared with serial bus, parallel port can ensure that control unit receives configuration command at the same time in a clock cycle, response time is almost independent of channel number, and internal clock of FPGA module can easily reach hundreds of MHz, so that multi-channel configuration can be completed in sub-second level, realizing real-time adaptive demand of new large-scale antenna array.

[0040] Large-scale array is not always in one form, some need uniform linear array or uniform surface array, and some need sparse array, users can issue instructions to slave module according to their own needs through master module, control different slave modules to complete different switch matrix state switching, so that part of switch matrix needed can be opened, and another part can be closed, so as to control antenna array to realize switching of different forms. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 Workflow diagram of large-scale multi-channel scalable parallel high-speed control system.

[0042] Figure 2 Workflow diagram of power module.

[0043] Figure 3 Daisy chain working principle diagram.

[0044] Figure 4 UART module principle diagram. DETAILED DESCRIPTION

[0045] The application will be further described in detail below with reference to the drawings.

[0046] As shown in Figure 1 The application discloses a large-scale multi-channel scalable parallel high-speed control system, host computer module, master-slave control module and analog switch matrix module.

[0047] The host computer module is located at the top of the entire system, and communicates with the master module through USB or serial port. Users can complete the control of the logic state of the analog switch, the setting of the register timing channel of the FPGA internal logic, the enablement of the channel switch, and the like by issuing system configuration instructions. The host computer module specifically includes a control interface GUI, a communication driver layer, a data analysis module, a database, and a device management module. The control interface GUI is a visual button, input box, and icon made by Python or Matlab and the like, and is used as an operation interface for human-computer interaction to input the required instructions. The communication driver layer mainly relies on UART serial port, USB, and IP protocol support to realize the transmission of communication data. The UART serial port communication transmits data bit by bit through a single data line; the USB communication is a high-speed serial bus standard, supports the communication between the host and multiple devices, and adopts a layered protocol stack; and the IP communication is network communication based on the IP protocol stack and supports global interconnection.

[0048] The master-slave control module is composed of an FPGA, a memory unit, a power module, a daisy chain, a UART, a USB module, and a clock synchronization. The FPGA is the core control unit of the system, connects the host computer, the storage, the daisy chain, and the like, and is the central controller for completing command analysis, protocol communication, state synchronization, and data scheduling in the system. A complete FPGA module generally includes the following main units: a logic unit, an IO pin, an embedded BRAM, a clock resource, a DSP module, a hard core interface, and a JTAG debugging interface. The logic unit is a basic programmable logic block that can be used to implement various logic combinations and timing logic; the IO pin is responsible for communication with external devices; the embedded BRAM can be used as an internal storage module for image caching and storing data in processing; the clock resource is used to generate and synchronize the clock to realize the synchronous movement between modules; the DSP module is a dedicated multiplier and adder that can accelerate digital signal processing; the hard core interface is a high-speed peripheral controller that is a bridge for high-speed communication with the host, and is commonly a PCIe controller and a USB peripheral; and the JTAG debugging interface is used for online code burning and internal signal capture to complete online debugging and verification.

[0049] The memory unit is used to realize data caching, configuration saving, and state register functions, and generally includes Flash, EEPROM, and SRAM. The Flash is a non-volatile memory that does not lose data when power is off, and is used for configuration data and program firmware storage; the EEPROM is commonly used for saving small amount of configuration parameters; and the SRAM is a high-speed volatile memory that loses data when power is off, and is mainly used for temporary data caching. The control command issued by the host computer is first stored in the memory, and then read and executed by the FPGA in sequence. The FPGA also stores data and logs in the memory for debugging and maintenance.

[0050] The power module is the basic core part, which can provide stable power supply of different voltage levels. The power module is responsible for converting the input voltage of 12V of the entire circuit system to 5V through AC / DC. The DCDC step-down board in the power module converts 5V voltage to 3.3V to supply power to EEPROM and analog switch. The voltage required by low-power IO level is 1.8V, and the power module also converts 3.3V to 1.8V. Figure 2 As shown in

[0051] The daisy chain is a module connection mode in series, in which one control module acts as the master module and the other control modules act as slave modules. The clock signal (SCK) and chip select signal (NSS) of all sub-boards are directly connected with the master module. When the host sends data, the data synchronization clock signal is sent to all slave modules. When the chip select signal of the slave module is low, the data is sent to the slave module through the master send slave receive (MOSI). The selected slave module will respond to the result through the corresponding master receive slave send (MISO) to the next slave module. When the chip select signal is pulled high, the slave module stops working and waits for the next chip selection. This ensures that multiple modules can execute control logic at the same time. In addition, it breaks the defect that the hardware of the circuit itself cannot be expanded. Several slave modules can be added to greatly improve the expandability of the system. Figure 3 As shown.

[0052] The UART module realizes the interaction between the host computer and the FPGA. UART is a serial asynchronous communication protocol. Communication only needs TX (send data) and RX (receive data) two lines to complete. Each communication is in the form of a frame, which contains start bit, data bit, check bit and stop bit. The start bit is low, the data is 8 bits, the check bit can be selected to have or not to have, and the stop bit is high. Figure 4 As shown.

[0053] The USB module is an important communication unit in the master module and the slave module. Its core function is to realize data communication and management interaction with the host computer or other modules. The USB communication protocol is initiated by the host computer. The device responds to the host request. After power on, the device is connected to the host computer through USB. The host computer identifies the device type through USB enumeration. The USB controller in the device responds to complete the configuration. Both parties interact with data through USB protocol.

[0054] The clock synchronization module realizes the timing alignment of command execution, data collection and synchronous triggering among multiple modules, ensures that the internal FPGA works under the same reference clock, and avoids data offset and logic inconsistency. When sharing the reference clock line, the master module sends the unified frequency clock to multiple slave modules through clock output, and the slave modules receive the clock signal to synchronize the internal logic operation and execution action, so that all switches execute the command at the same time.

[0055] The analog switch matrix module mainly completes flexible switching, connection and isolation of signal paths. The essence of the analog switch is a semiconductor device, and the on-off state of the switch is determined by the control terminal level. When the switch is on, the signal is allowed to pass through, and when the switch is off, the signal flow is blocked. When the FPGA sends a control signal to determine which switches are closed and which are open in real time, the analog switch module responds to the control logic to complete the switching of the corresponding signal channel, which can achieve rapid switching in the order of microseconds and is suitable for new large-scale antenna control systems.

[0056] The working principle of the application is as follows:

[0057] According to the user's demand for large-scale antenna array control, the user writes a target instruction in Verilog or VHDL computer language through the host computer module to realize the corresponding function. The signal reaches the FPGA module of the master control module through the serial port, and the master control module FPGA module is used as the core to send instructions to different slave control modules. Relying on the powerful parallel port output of the FPGA, all slave control modules can respond to the instructions sent by the master control module FPGA module under the same clock, and complete the conduction and cutoff of the corresponding analog switch matrix to realize the regulation and control of the large-scale antenna array. The application mainly consists of three modules: host computer module (top control), master-slave control module (core control unit) and analog switch matrix module (signal path control). The three modules work cooperatively through UART serial port, USB or network (IP) communication to complete high-concurrency, high-speed data collection and signal switching to control the large-scale antenna array to perform the operation of human imagination.

[0058] The host computer module is located at the top layer of the system and is responsible for human-computer interaction and command issuing. The user inputs the control instruction through the buttons, input boxes or icons of the GUI interface. UART, USB and IP protocol are responsible for data transmission for subsequent master control module application. The data analysis module analyzes the user instruction and temporarily stores it in the memory to provide data for subsequent FPGA module execution.

[0059] The master-slave control module is relied on the master control module FPGA module to execute the host computer instruction, analyze the protocol, synchronize the state and dispatch the data. The host computer instruction exists in the memory unit, and the master control module FPGA reads and executes in order again, and the execution result can be written back to the memory module for debugging. The master control module is connected in series with a plurality of slave control modules through a daisy chain, and unified clock signal (SCK) and chip selection signal (NSS) are used to ensure that the timeline of each slave control module is consistent with that of the master control module. When the master control module sends data, the data is transmitted to the specified slave control module through the MOSI channel, and the slave control module transmits the processed data to the next slave control module through the MISO channel. When the data is transmitted to the last slave control module, the data is transmitted back to the master control module to complete a round of instruction issuance and completion.

[0060] When each slave control module receives the instruction, the control analog switch matrix module controls the semiconductor switch in the analog switch matrix module to open and close the switch by controlling the level of the signal to complete the opening and closing of the switch, so as to control the switch corresponding to the large-scale antenna array response respectively, and complete the user's needs.

[0061] Application example:

[0062] The antenna array often contains hundreds or even thousands of radiation units, and needs to accurately control the amplitude, phase and polarization. The system relies on the high-speed parallel logic of the FPGA module and the daisy chain expansion structure, and can control multiple channels simultaneously within microseconds.

[0063] The new large-scale antenna array usually needs to support multiple frequency bands. The low frequency band is used for wide coverage, and the high frequency band is used for large bandwidth and high rate. The analog switch matrix is the core control node of the radio frequency path. Different frequency band radio frequency links (power amplifier, filter, antenna unit) are connected through the switch matrix, and the FPGA module issues control signals to realize millisecond or microsecond fast switching of different working frequency bands.

[0064] The new large-scale antenna array may need different polarization modes in different applications. Linear polarization, circular polarization and dual polarization have their own application scenarios, and the analog switch matrix can control the on-off of different feed ports to switch to linear polarization, dual polarization or circular polarization configuration in real time.

[0065] Each channel of the new large-scale antenna array has differences in amplitude, phase and time delay, and needs to be calibrated to ensure the beam synthesis accuracy and test the stability and performance of the channel. The analog switch matrix can quickly switch some channels in the antenna array to a test link or a calibration link. The calibration link can access a reference signal source, a power meter and a phase measurement module to complete the test and calibration of the antenna array.

Claims

1. A large-scale, multi-channel, scalable, parallel, high-speed control system, characterized in that, It includes a host computer module, a master-slave control module, and an analog switch matrix module; The host computer module is the instruction source and management center of the entire system. It runs the control software, generates control instructions, configuration parameters and scheduling strategies. The host computer module sends instructions to the main control module through a high-speed communication interface. Simultaneously, it receives status information and collected data uploaded by the main control module to achieve real-time monitoring and operation interface display; The master-slave control module is the core scheduling and execution layer of the system, connecting the host computer module above and the analog switch matrix module below. The master-slave control module includes a master control module and multiple slave control modules; The main control module receives instructions from the host computer module through its internal FPGA module, performs task parsing and timing scheduling, and sends the allocated control data to each slave control module. The slave control module performs specific channel control operations according to the instructions issued by the master control module and feeds back the execution results or status to the master control module; multiple slave control modules can be extended in a daisy chain manner to achieve parallel expansion of the number of channels on a large scale. The analog switch matrix module is the final physical execution layer, directly acting on the new large-scale antenna system. The analog switch matrix module is directly connected to the slave control module and is used to realize high-speed switching and signal routing in the actual physical channels. It receives drive signals from the slave control module and realizes independent or synchronous switching of hundreds to thousands of channels to achieve the operation of turning the switch matrix on and off. It supports flexible connection between various signal sources and loads to meet the operational requirements of the new large-scale antenna system.

2. The large-scale multi-channel scalable parallel high-speed control system according to claim 1, characterized in that, The host computer module communicates with the main control module via USB 3.0 or serial port. The user can send system configuration commands to the master and slave control modules to complete the control of the analog switch on and off logic states, the setting of the register timing channels of the FPGA module internal logic, and the enabling channel switch. The host computer module includes a control interface (GUI), a communication driver layer, a data parsing module, a database, and a device management module. The control interface (GUI) uses Python or Matlab to create visual buttons, input boxes, and icons, which serve as the human-computer interaction interface for inputting the required commands. The communication driver layer relies on UART serial port, USB communication, and IP communication to realize the transmission of communication data. UART serial port communication transmits data bit by bit through a single data line; USB communication is a high-speed serial bus standard that supports communication between the host and multiple devices and adopts a layered protocol stack; IP communication is a network communication based on the IP protocol stack and supports global interconnection. The data parsing module decodes, formats, and extracts features from the raw data uploaded by the master and slave control modules, converting the low-level raw data into structured information and providing it to the control interface GUI for real-time display. It also supports anomaly detection and preliminary analysis of the data to help users judge the system's operating status. The database is used to store historical instructions, status data, measurement results, and user configurations during system operation. It supports data querying, retrieval, and comparison, facilitating long-term trend analysis and repeatable experiments. It is linked with the control interface GUI to realize historical data playback and statistical chart display. The device management module is used to uniformly manage the connected master and slave control modules, including device registration, identification, status monitoring and resource allocation. It supports online or offline device detection and automatic reconnection, ensuring the reliability and scalability of the system. It provides a device mapping table, enabling users to directly operate the corresponding physical devices and channels through logical channel numbers on the control interface GUI.

3. The large-scale multi-channel scalable parallel high-speed control system according to claim 1, characterized in that, The master-slave control module includes an FPGA module, a memory unit, a power module, a daisy chain, a UART module, a USB module, and a clock synchronization module. The memory unit interacts with the FPGA module for data and instructions. The power supply module provides power to the FPGA module. The USB module and UART provide interfaces for the FPGA module to interact with the host computer module. The clock synchronization module provides a global clock for the FPGA module to ensure the timing alignment of the instructions issued by the FPGA module. The daisy chain enables the FPGA module to achieve multi-board interaction and expansion.

4. The large-scale multi-channel scalable parallel high-speed control system according to claim 3, characterized in that, The FPGA module includes logic units, I / O pins, embedded BRAM, clock resources, DSP modules, hard core interfaces, and JTAG debugging interfaces. Clock resources generate clock signals to drive global operation. Logic units, as the core, work with embedded BRAM and DSP modules to perform complex calculations or data access. Logic units are connected to I / O pins and hard core interfaces to drive external signal input and output. The JTAG debugging interface is directly connected to the internal logic units of the FPGA, providing debugging and configuration support. A logic unit is a basic programmable logic block used to implement various logic combinations and sequential logic. IO pins are responsible for communicating with peripherals; Embedded BRAM serves as a built-in storage module for image caching and storing data during processing; Clock resources are used to generate and synchronize clocks, enabling synchronous operation between modules; The DSP module is a dedicated multiplier and adder that accelerates digital signal processing; the hard core interface is an integrated high-speed peripheral controller that serves as a bridge for high-speed communication with the host computer. The JTAG debugging interface is used by users to burn code online and capture internal signals to complete online debugging and verification.

5. A large-scale multi-channel scalable parallel high-speed control system according to claim 3, characterized in that, The memory unit is used to implement data caching, configuration storage, and status registers, and includes Flash, EEPROM, and SRAM. Flash memory is a non-volatile memory that retains data even when power is off. It is used to store configuration data and program firmware. EEPROM is used to store a small number of configuration parameters; SRAM is a high-speed volatile memory; data is lost when power is off, and it is used for temporary data caching. When the system is powered on, the firmware and large-scale configuration data in Flash are loaded into SRAM for initialization logic and fast operation. During system operation, the FPGA module can read and write EEPROM at any time to save and restore key configuration parameters. SRAM exchanges data with the main logic of the FPGA module in real time, and undertakes the functions of cache and register during operation. The control commands issued by the host computer module are first stored in the memory unit, and then the FPGA module reads and executes them sequentially. The FPGA module also stores the data and logs in the memory unit for easy debugging and maintenance.

6. A large-scale multi-channel scalable parallel high-speed control system according to claim 3, characterized in that, The power module provides stable power at different voltage levels. The power module converts the input voltage of the entire 12V circuit system to 5V via AC / DC. The DC-DC step-down module in the power module converts the 5V voltage to 3.3V to power the EEPROM and analog switches. The voltage required for low-power I / O level is 1.8V, and the power module will also convert 3.3V to 1.8V.

7. A large-scale multi-channel scalable parallel high-speed control system according to claim 3, characterized in that, The daisy chain is a module serial connection method, in which one control module is selected as the master control module and the other control modules are as slave control modules. The clock signals and chip select signals of all daughter boards are directly connected to the master control module. When the master control module sends data, the data synchronization clock signal will be sent to all slave control modules. When the chip select signal of a slave control module is low, the data will be sent to that slave control module through master transmit and slave receive. The selected slave control module will transmit the response result to the next slave control module through the corresponding master receive and slave transmit. When the chip select signal is high, the slave control module will stop working and wait for the next chip select.

8. A large-scale multi-channel scalable parallel high-speed control system according to claim 3, characterized in that, The UART module enables interaction between the host computer module and the FPGA module. The UART module uses a serial asynchronous communication protocol and communicates through two lines, TX and RX. Each communication is performed in the form of frames, and each frame contains: start bit, data bits, parity bit and stop bit. The start bit is low, the data is 8 bits, the parity bit is optional, and the stop bit is high.

9. A large-scale multi-channel scalable parallel high-speed control system according to claim 3, characterized in that, The USB module includes a USB controller, interface circuitry, and driver logic. The USB controller is the hardware implementation unit of the USB protocol, divided into a host controller and a device controller, located on the host computer unit and the peripheral FPGA module, respectively. The interface circuitry is the USB physical layer interface, and the driver logic interacts internally with the FPGA module. USB includes a physical interface, electrical characteristics, and a USB communication protocol. The USB communication protocol is a set of rules for interaction between the USB device and the host, including enumeration, data transmission modes, and transaction definitions. Enumeration is used by the host computer to identify device types and capabilities. Data transmission modes include control output, batch output, interrupt output, and isochronous output, which are different data transmission modes for USB. Transaction definitions are used when the host initiates a request and the device responds. USB is the main framework, the USB communication protocol is the communication rules, the USB controller is the hardware that executes the USB communication protocol, and the USB module is a functional unit in the system that includes a USB controller and an interface to complete specific communication. The USB module enables data communication and management interaction with the host computer module or other modules. The USB communication protocol is that the host computer initiates all communication, and the device responds to the host request. After power-on, the device connects to the host computer via USB. The host computer identifies the device type through USB enumeration, and the USB controller in the device responds to complete the configuration. The two parties exchange data through the USB communication protocol. The clock synchronization module realizes the timing alignment of command execution, data acquisition and synchronous triggering among multiple modules, ensuring that the internal FPGA modules work under the same reference clock and avoiding data offset and logic inconsistency; When a common reference clock line is used, the master control module sends a unified frequency clock to multiple slave control modules through clock output. The slave control modules receive the clock signal, synchronize their internal logic operation and execution actions, and ensure that all switches execute commands at the same time.

10. A large-scale multi-channel scalable parallel high-speed control system according to claim 1, characterized in that, The analog switch matrix module completes the flexible switching, connection and isolation of signal paths; the analog switch matrix module is essentially a semiconductor device, and the on and off state of the switch is determined by the level of the control terminal. When it is on, the signal is allowed to pass through, and when it is off, the signal flow is blocked. When the FPGA module sends a control signal to determine in real time which switches are closed and which are open, the analog switch matrix module responds to the control logic and completes the corresponding signal channel switching, achieving a fast switching speed on the order of microseconds, which is suitable for new large-scale antenna control systems.

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