Memory data management method and device, electronic equipment and readable storage medium

Abstract

The present disclosure relates to the technical field of memory, and provides a memory data management method and device, an electronic device and a readable storage medium. The method comprises: dividing storage data of a target memory into a plurality of target data blocks, and storing a target check code in each target data block; periodically checking the target data blocks according to the target check code to determine whether a data change behavior occurs in the target data blocks; obtaining a target data frame and interacting with the target data blocks according to indication information of the target data frame; and counting a data change frequency of the target data blocks and adjusting a check period and a block division scheme of the target data blocks according to the data change frequency. The technical scheme provided by one or more embodiments of the present disclosure can improve the data management efficiency of the memory and prolong the service life of the memory.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and specifically to a memory data management method, apparatus, electronic device, and readable storage medium. Background Technology

[0002] In modern electronic systems, Flash memory, as a non-volatile storage medium, has been widely used in various fields, such as embedded systems, mobile devices, and industrial control, due to its advantages such as non-volatility when power is off, large capacity, low power consumption, and strong shock resistance.

[0003] However, traditional Flash data management methods typically employ complete erase and write operations when storing and updating data. Even minor data changes require rewriting the entire Flash memory, resulting in relatively low data update efficiency. Furthermore, frequent erase and write operations accelerate Flash memory wear and tear, easily shortening its lifespan. Summary of the Invention

[0004] In view of this, one or more embodiments of the present disclosure provide a memory data management method, apparatus, electronic device and readable storage medium, which can improve the data management efficiency of the memory and extend the service life of the memory.

[0005] This disclosure provides a memory data management method, the method comprising: dividing the stored data of a target memory into multiple target data blocks, and storing a target check code in each target data block; periodically checking the target data blocks according to the target check code to determine whether the target data blocks have undergone data modification; acquiring target data frames and interacting with the target data blocks according to the indication information of the target data frames; calculating the data modification frequency of the target data blocks, and adjusting the check cycle and block partitioning scheme of the target data blocks according to the data modification frequency.

[0006] This disclosure also provides a memory data management device, comprising a security protection module, a transceiver control module, and a dynamic adjustment module. The security protection module is configured to divide the stored data of a target memory into multiple target data blocks, and store a target checksum in each target data block. The security protection module is further configured to periodically check the target data blocks according to the target checksum to determine whether data changes have occurred in the target data blocks. The transceiver control module is configured to acquire target data frames and interact with the target data blocks according to the indication information of the target data frames. The dynamic adjustment module is configured to statistically analyze the data change frequency of the target data blocks and adjust the checksum period and block partitioning scheme of the target data blocks according to the data change frequency.

[0007] This disclosure also provides an electronic device, which includes a memory and a processor. The memory is used to store a computer program, and when the computer program is executed by the processor, it implements the memory data management method described above.

[0008] This disclosure also provides a computer-readable storage medium for storing a computer program that, when executed by a processor, implements the memory data management method described above.

[0009] This disclosure provides a technical solution through one or more embodiments that can divide and manage stored data in a target memory into blocks, and store a corresponding target checksum for each target data block. Periodic verification of the target data blocks ensures their integrity and accuracy, enhancing data security. Based on the target data frame, data interaction can be refined to individual target data blocks, rather than interacting with the target memory as a whole, thereby increasing data update efficiency.

[0010] The technical solutions provided by one or more embodiments of this disclosure allow for flexible adjustment of the verification cycle and block partitioning scheme of the target data block based on statistical information about the data change frequency, further optimizing the data management strategy of the target memory. This dynamic adjustment mechanism can effectively improve the data management efficiency of the target memory and extend its service life. Attached Figure Description

[0011] The features and advantages of the embodiments of this disclosure will be more clearly understood by referring to the accompanying drawings, which are illustrative and should not be construed as limiting the present disclosure in any way. In the drawings:

[0012] Figure 1 A schematic diagram illustrating the steps of a memory data management method according to one embodiment of this disclosure is shown;

[0013] Figure 2 A schematic diagram of a data interaction process is shown in one embodiment of this disclosure;

[0014] Figure 3 A schematic diagram of the module division of a controller according to one embodiment of the present disclosure is shown;

[0015] Figure 4 A schematic diagram illustrating the workflow of a security protection module in one embodiment of this disclosure is shown.

[0016] Figure 5 A schematic diagram illustrating the workflow of a prediction model in one embodiment of this disclosure is shown.

[0017] Figure 6 A schematic diagram of the functional modules of a memory data management device in one embodiment of the present disclosure is shown;

[0018] Figure 7 A schematic diagram of the structure of an electronic device according to one embodiment of the present disclosure is shown. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0020] In related technologies, data stored in Flash memory is susceptible to accidental modification and theft if effective security protection measures are lacking. Furthermore, in scenarios with concurrent multi-task access, access to the same Flash memory by different host devices may interfere with each other.

[0021] In view of this, the memory data management method provided in one embodiment of this disclosure, on the one hand, directly interacts with each target data block, improving data update efficiency, reducing unnecessary erase and write operations, and extending the lifespan of the Flash memory; on the other hand, it performs periodic verification on each target data block, enhancing data security and reducing the risk of data being accidentally modified or stolen. Furthermore, during concurrent access by multiple tasks, each target data block can respond to the target data frame independently, effectively avoiding data inconsistency and system performance degradation, and improving the overall system performance and stability of the memory.

[0022] This disclosure provides a memory data management method according to one embodiment, which can be applied to a control chip or control device and run therein as firmware or software components. The control chip can be an electronic chip with data processing capabilities. For example, the control chip can be an integrated circuit with data processing capabilities such as an MCU (Microcontroller Unit), an MPU (Microprocessor Unit), an FPGA (Field-Programmable Gate Array), or a SoC (System on Chip). The control device can be an electronic device with data processing capabilities. For example, the control and testing device can be a personal computer, workstation, laptop computer, industrial control computer, etc.

[0023] Please see Figure 1 The memory data management method provided in one embodiment of this disclosure may include the following steps.

[0024] S1: Divide the stored data in the target memory into multiple target data blocks, and store a target check code in each target data block.

[0025] In this embodiment, the target memory primarily refers to Flash memory. Depending on the specific application scenario, the target memory can also be expanded to other memories that support data block partitioning. Dividing the stored data in the target memory into blocks allows each target data block to be managed and updated independently. When the target host (also known as the source device) needs to update or read data from the target memory, it can stop writing or reading the entire stored data from the target memory and instead perform local interactions with each target data block.

[0026] In this embodiment, for each divided target data block, a preset verification algorithm can be used to calculate the data content of the target data block, generate a target verification code, and store the target verification code in the target data block. The target verification code can be used to verify whether the target data block has been damaged or tampered with.

[0027] In a practical application example, using the same preset verification algorithm, the data content in the target data block, excluding the target CAPTCHA, can be recalculated. Comparing the recalculated result with the target CAPTCHA already recorded in the target data block can determine whether the target data block has been corrupted or tampered with. Preset verification algorithms include, but are not limited to, one-way hash algorithms (such as SHA-256, BLAKE2), keyed message authentication codes (such as HMAC-SHA256), and digital signature algorithms (such as ECDSA-P256, Ed25519).

[0028] In this embodiment, each of the divided target data blocks can be marked with a block number for easy identification and management. Using the block number, the corresponding data block can be quickly indexed in the target memory.

[0029] S2: Perform periodic verification on the target data block according to the target verification code to determine whether the target data block has undergone data modification.

[0030] In this embodiment, the target data block is periodically verified to ensure its integrity and accuracy, thereby enhancing the data security of the target storage. If the verification fails, it indicates that the data block may be corrupted or tampered with. In this case, a request can be proactively sent to the target host to update the data content of the target data block, thus ensuring its integrity and accuracy.

[0031] In a practical application example, during each verification cycle, a preset verification algorithm can be used to calculate the current data content of the target data block and generate the current checksum. After comparing the current checksum with the target checksum, if a discrepancy is found, a data update request for the target data block can be sent to the target host.

[0032] S3: Acquire the target data frame and interact with the target data block according to the indication information of the target data frame.

[0033] In this embodiment, when external data at the target host needs to be updated into the target memory, the target host can store the data to be updated in a special type of target data frame. Subsequently, the target host can transmit the target data frame containing the data to be updated to the execution entity of this method via the network topology. Alternatively, the target host can have the driver directly send the target data frame containing the data to be updated to the execution entity of this method. After obtaining the target data frame, the execution entity of this method can parse the target data frame and, based on the instruction information contained in the target data frame, perform data interaction with the target memory (e.g., erasing, writing, reading, etc.).

[0034] In some implementations, the step of interacting with the target data block according to the indication information of the target data frame includes: determining the frame type of the target data frame; if the target data frame is a data type frame, then updating the target data block according to the data to be updated contained in the data type frame; if the target data frame is a notification type frame, then reading the target data block according to the notification information contained in the notification type frame.

[0035] Specifically, the target host can instruct the method execution entity to update a portion of target data blocks in the target memory by sending a data type frame. The data type frame can contain the data to be updated and the block number of the target data block to be updated. When the target host has a large cache, all stored data in the target memory can be read into the target host's cache and compared with the data to be updated to determine the target data block to be updated and its block number. When the target host does not have a large cache, all target checksums in the target memory can be read into the target host's cache and compared with the update checksum calculated based on the data to be updated. Based on the checksum comparison result, the target data block to be updated and its block number can be determined.

[0036] The target host can also notify the method execution entity to read specific data content of a portion of the target data block from the target memory by sending a notification type frame. The method execution entity can then place the read data content into a dedicated data frame and send it back to the target host.

[0037] To enhance data security, data encryption algorithms can be introduced into the data interaction process between the method execution subject and the target host, as well as the data interaction process between the method execution subject and the target storage, to prevent data from being illegally intercepted.

[0038] In a practical application example, please refer to Figure 2 When the received data frame is a data type frame, the content of the data block can be updated directly based on the block number. When the received data frame is a notification type frame, the comparison result of the checksum can first be used to determine which data blocks' content is inconsistent with the data to be updated on the target host. Then, based on the notification information in the notification type frame, it can be determined whether to read the specific block content of these data blocks. If it is necessary to read the specific block content, the read specific block content can be placed in a new data type frame and sent back to the target host. If it is not necessary to read the specific block content, the checksum comparison result can be placed in a new notification type frame to inform the target host.

[0039] S4: Calculate the data change frequency of the target data block, and adjust the verification cycle and block partitioning scheme of the target data block according to the data change frequency.

[0040] In this embodiment, for storage areas in the target memory where data is frequently modified, the data block verification cycle in that area can be reduced to make verification more frequent, thereby timely detection of possible abnormal behavior and increasing data security; for storage areas in the target memory where data has not been modified for a long time, the data block verification cycle in that area can be increased to reduce system load.

[0041] In this embodiment, for storage areas in the target memory where data is frequently modified, the number of data blocks in that area can be increased to allow for more granular management of each data block; for storage areas in the target memory where data has not been modified for a long time, the number of data blocks in that area can be reduced to decrease the system load.

[0042] In a practical application example, suppose a storage area initially contains 5 data blocks. Once this storage area is designated as a high-frequency modification area, these 5 data blocks can be further divided into 10 data blocks. This way, when an anomaly occurs in one of the 10 data blocks, updating the data takes less time.

[0043] In some implementations, adjusting the verification period and block partitioning scheme of the target data block according to the data change frequency includes: if the data change frequency of the first data block in the target data block is greater than a first preset value, then reducing the verification period of the first data block; if the data change frequency of the second data block in the target data block is less than a second preset value, then reducing the verification period of the second data block; wherein the first preset value is greater than the second preset value.

[0044] In some implementations, adjusting the verification period and block partitioning scheme of the target data block according to the data change frequency includes: splitting the third data block if the data change frequency of the third data block in the target data block is greater than a third preset value; merging multiple fourth data blocks if the data change frequency of the fourth data block in the target data block is less than a fourth preset value; wherein the third preset value is greater than the fourth preset value.

[0045] Setting the first, second, third, and fourth preset values ​​allows for a clearer determination of whether data updates are frequent within a specific storage area. The specific values ​​of these preset values ​​can be adjusted based on the actual application scenario.

[0046] In some embodiments, the memory data management method further includes: acquiring reference relationship data between the operating performance of the target memory and the working environment conditions; determining a control mode for the target data block based on the reference relationship data and the current environmental conditions; wherein the control mode includes at least one of read / write priority setting, block partitioning density setting, and verification cycle setting.

[0047] Specifically, by conducting performance tests on the target memory under different operating environmental conditions (such as temperature and voltage), reference data on the relationship between the target memory's operating performance (e.g., read / write speed, bit error rate) and the environmental conditions (e.g., temperature, humidity, voltage) can be obtained. Based on the known reference data and the current environmental conditions, the control mode for the target memory and target data blocks can be dynamically adjusted. For example, under different environmental conditions, the magnitude of the reduction in the verification cycle and the amount of data block splitting can vary for storage areas that frequently change data.

[0048] In some embodiments, obtaining reference relationship data between the working performance of the target memory and the workpiece environmental conditions includes: performing read and write tests on the free area of ​​the target memory for various workpiece environmental conditions to obtain target performance parameters; and determining the reference relationship data based on the statistical analysis results of the workpiece environmental conditions and the target performance parameters.

[0049] Specifically, the environmental conditions of the workpiece may include the target controller's chip temperature, chip voltage, chip current, read / write workload per unit time, electromagnetic interference, humidity, etc. The target performance parameters may include read / write speed, bit error rate, etc.

[0050] By reading and writing to the free areas of the target memory under different environmental conditions, effective reference relationship data can be obtained. Using this reference relationship data and the current environmental conditions, the control mode applicable to the target memory and the target data block can be accurately predicted. For example, when multiple tasks concurrently access the same data block, if a high bit error rate occurs during write operations, the priority of read operations can be adjusted to the highest, write transactions can be suspended, and writing can resume only after the bit error rate disappears.

[0051] Please see Figure 3 The present disclosure provides a memory data management method according to one embodiment, which can be used by... Figure 3 The controller shown can execute, and can... Figure 3 The Flash memory shown is used for data management. This controller contains four core functional modules: a security protection module, a data transmission and reception control module, a training model, and a prediction model.

[0052] The security protection module can execute the method steps S1 and S2 described above. Specifically, the security protection module can divide the stored data in the Flash memory into blocks and store a checksum in each data block.

[0053] In a practical application example, please refer to Figure 4The security protection module can periodically verify the content of each data block. The verification process involves using a verification algorithm to calculate the current checksum of the data block and comparing it with the checksum pre-stored in that data block. If the verification fails, it indicates that the data block may be corrupted or tampered with. The security protection module can proactively send a request to the host to update the content of the data block to ensure data integrity and accuracy. The security protection module can send each verification result to the prediction model, allowing the model to refer to these results and determine whether to adjust the verification cycle and block partitioning scheme for some data storage areas.

[0054] The data transceiver control module can execute the steps described in step S3 above. Specifically, the data transceiver control module completes data interaction and parsing with external devices (mainly the target host). When an external device needs to update data into the Flash memory, it can place the content to be updated in a special type of data frame and send it to the controller's data transceiver control module. The data transceiver control module is responsible for judging, parsing, erasing, and writing data. When the external device's bandwidth allows, it can also send a special type of notification frame to notify the data transceiver control module to read the specific contents of the Flash memory. To improve system security, in addition to defining special types of data frames and notification frames, data encryption algorithms can be introduced during the interaction between the data transceiver control module and external devices to prevent the interaction content from being illegally intercepted.

[0055] The training model primarily performs functional self-training, providing the training results as parameters to the prediction model. This allows the prediction model to more appropriately adjust the verification cycle and block partitioning scheme of the target data blocks. When the transceiver control module does not receive read / write traffic from the target host, the training model will read and write the free storage area of ​​the Flash memory to understand the target memory's performance under different workpiece environmental conditions. Taking the temperature conditions collected by the controller (which could be the temperature of the chip where the controller is located or the collected Flash memory temperature) as an example, the temperature conditions will constantly change due to environmental influences. By reading and writing the free storage area of ​​the Flash memory under different temperature conditions, the training model can obtain the relationship between the temperature conditions and the speed of reading and writing different lengths of data in the Flash memory, the Flash memory read / write bit error rate, and other performance parameters. The reference relationship data obtained by the training model is provided to the prediction model for its use. Here, temperature conditions are only used as an example of workpiece environmental conditions. In practical applications, conditions such as chip voltage, chip current, read / write workload per unit time, electromagnetic interference, and humidity can also be used as workpiece environmental conditions.

[0056] The prediction model can be executed according to the method steps in step S4 above. Please refer to [link / reference]. Figure 5 The predictive model primarily relies on existing input parameters to predict future Flash memory demands and dynamically adjusts the control mode for target data blocks to optimize Flash memory performance. The predictive model can adjust the number of data blocks used in each storage area of ​​the Flash memory and the data block verification cycle based on the data change frequency of the data blocks. The predictive model can also predict which control adjustments the controller should make based on the input content of the training model, selecting the optimal operation when multiple tasks are concurrent (i.e., multiple devices need to interact with the Flash memory). For example, under certain conditions, if write operations experience a high bit error rate while read operations are unaffected, the predictive model will prioritize read transactions and suspend write transactions until the bit error rate disappears, then resume write operations.

[0057] This collaborative mechanism between the training and prediction models can dynamically optimize the data storage and management strategies of the memory based on actual conditions, thereby improving the performance and stability of the memory system.

[0058] This disclosure provides a technical solution through one or more embodiments that can divide and manage stored data in a target memory into blocks, and store a corresponding target checksum for each target data block. Periodic verification of the target data blocks ensures their integrity and accuracy, enhancing data security. Based on the target data frame, data interaction can be refined to individual target data blocks, rather than interacting with the target memory as a whole, thereby increasing data update efficiency.

[0059] The technical solutions provided by one or more embodiments of this disclosure allow for flexible adjustment of the verification cycle and block partitioning scheme of the target data block based on statistical information about the data change frequency, further optimizing the data management strategy of the target memory. This dynamic adjustment mechanism can effectively improve the data management efficiency of the target memory and extend its service life.

[0060] Please see Figure 6 This disclosure also provides a memory data management device, a security protection module 100, a transceiver control module 200, and a dynamic adjustment module 300;

[0061] The security protection module 100 is used to divide the stored data of the target memory into multiple target data blocks, and store a target verification code in each target data block.

[0062] The security protection module 100 is also used to periodically verify the target data block according to the target verification code to determine whether the target data block has undergone data modification.

[0063] The transceiver control module 200 is used to acquire the target data frame and interact with the target data block according to the indication information of the target data frame.

[0064] The dynamic adjustment module 300 is used to count the data change frequency of the target data block and adjust the verification cycle and block partitioning scheme of the target data block according to the data change frequency.

[0065] In one embodiment, the security protection module 100 is specifically configured to, in each verification cycle, use a preset verification algorithm to calculate the current data content of the target data block and generate a current verification code; compare the current verification code with the target verification code; if the current verification code and the target verification code are inconsistent, send a data update request for the target data block to the target host.

[0066] In one embodiment, the transceiver control module 200 is specifically used to determine the frame type of the target data frame; if the target data frame is a data type frame, then update the target data block according to the data to be updated contained in the data type frame; if the target data frame is a notification type frame, then read the target data block according to the notification information contained in the notification type frame.

[0067] In one embodiment, the dynamic adjustment module 300 is specifically used to: if the data change frequency in the first storage area of ​​the target memory is greater than a first preset value, then reduce the verification cycle of the target data block located in the first storage area; if the data change frequency in the second storage area of ​​the target memory is less than a second preset value, then increase the verification cycle of the target data block located in the second storage area; wherein the first preset value is greater than the second preset value.

[0068] In one embodiment, the dynamic adjustment module 300 is specifically used to: if the data change frequency in the third storage area of ​​the target memory is greater than a third preset value, then perform a secondary division on the target data block located in the third storage area; if the data change frequency in the fourth storage area of ​​the target memory is less than a fourth preset value, then merge the target data block located in the fourth storage area; wherein the third preset value is greater than the fourth preset value.

[0069] In one embodiment, the dynamic adjustment module 300 is further configured to acquire reference relationship data between the working performance of the target memory and the workpiece environmental conditions; and determine the control mode of the target data block based on the reference relationship data and the current environmental conditions; wherein the control mode includes at least one of read / write priority setting, block partitioning density setting, and verification cycle setting.

[0070] In one embodiment, the memory data management device further includes a training module. The training module is used to perform read / write tests on the free storage area of ​​the target memory under various workpiece environmental conditions to determine target performance parameters; and to determine the reference relationship data based on the statistical analysis results of the workpiece environmental conditions and the target performance parameters.

[0071] The modules described in the above embodiments can be implemented by computer chips or by products with certain functions. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0072] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each module can be implemented in one or more software and / or hardware.

[0073] Please see Figure 7 This disclosure also provides an electronic device, which includes a memory and a processor. The memory is used to store a computer program, and when the computer program is executed by the processor, it implements the memory data management method described above.

[0074] This disclosure also provides a computer-readable storage medium for storing a computer program, which, when executed by a processor, implements the memory data management method described above.

[0075] The processor can be a central processing unit (CPU). It can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations thereof.

[0076] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor executes various functional applications and data processing by running the non-transitory software programs, instructions, and modules stored in the memory, thereby implementing the methods in the above-described embodiments.

[0077] The memory may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created by the processor, etc. Furthermore, the memory may include high-speed random access memory and non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory may optionally include memory remotely located relative to the processor, which can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0078] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc.; the storage medium can also include combinations of the above types of memory.

[0079] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, embodiments of apparatus, devices, and storage media are basically similar to method embodiments, so the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0080] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

[0081] Although embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A memory data management method, characterized in that, The method includes: The data stored in the target memory is divided into multiple target data blocks, and a target check code is stored in each target data block. Based on the target check code, the target data block is periodically checked to determine whether the target data block has undergone data modification. Acquire the target data frame and interact with the target data block according to the indication information of the target data frame; The data change frequency of the target data block is statistically analyzed, and the verification cycle and block partitioning scheme of the target data block are adjusted according to the data change frequency. The step of adjusting the verification cycle and block partitioning scheme of the target data block according to the data change frequency includes: If the data change frequency in the first storage area of ​​the target memory is greater than a first preset value, then the verification cycle of the target data block located in the first storage area is reduced. If the data change frequency in the second storage area of ​​the target memory is less than a second preset value, then the verification cycle of the target data block located in the second storage area is increased; wherein, the first preset value is greater than the second preset value; If the data change frequency in the third storage area of ​​the target memory is greater than a third preset value, then the target data block located in the third storage area is divided a second time. If the data change frequency in the fourth storage area of ​​the target memory is less than a fourth preset value, then the target data block located in the fourth storage area is merged; wherein the third preset value is greater than the fourth preset value.

2. The method according to claim 1, characterized in that, The step of periodically verifying the target data block based on the target checksum includes: In each verification cycle, a preset verification algorithm is used to calculate the current data content of the target data block and generate the current verification code. Compare the current checksum with the target checksum; If the current checksum does not match the target checksum, a data update request for the target data block is sent to the target host.

3. The method according to claim 1 or 2, characterized in that, The step of interacting with the target data block according to the indication information of the target data frame includes: Determine the frame type of the target data frame; If the target data frame is a data type frame, then the target data block is updated according to the data to be updated contained in the data type frame; If the target data frame is a notification type frame, then the target data block is read according to the notification information contained in the notification type frame.

4. The method according to claim 1, characterized in that, The method further includes: Obtain reference relationship data between the working performance of the target memory and the workpiece environmental conditions; Based on the reference relationship data and the current environmental conditions, determine the control mode of the target data block; The control mode includes at least one of read / write priority setting, block partition density setting, and verification cycle setting.

5. The method according to claim 4, characterized in that, The step of acquiring reference relationship data between the working performance of the target memory and the workpiece environmental conditions includes: For various workpiece environmental conditions, read and write tests are performed on the free storage area of ​​the target memory to determine the target performance parameters; The reference relationship data is determined based on the statistical analysis results of the workpiece environmental conditions and the target performance parameters.

6. A memory data management device, characterized in that, The device includes a safety protection module, a transceiver control module, and a dynamic adjustment module; The security protection module is used to divide the stored data of the target memory into multiple target data blocks, and store a target verification code in each target data block. The security protection module is also used to periodically verify the target data block according to the target verification code to determine whether the target data block has undergone data modification. The transceiver control module is used to acquire the target data frame and interact with the target data block according to the indication information of the target data frame. The dynamic adjustment module is used to count the data change frequency of the target data block and adjust the verification cycle and block partitioning scheme of the target data block according to the data change frequency. The step of adjusting the verification cycle and block partitioning scheme of the target data block according to the data change frequency includes: If the data change frequency in the first storage area of ​​the target memory is greater than a first preset value, then the verification cycle of the target data block located in the first storage area is reduced. If the data change frequency in the second storage area of ​​the target memory is less than a second preset value, then the verification cycle of the target data block located in the second storage area is increased; wherein, the first preset value is greater than the second preset value; If the data change frequency in the third storage area of ​​the target memory is greater than a third preset value, then the target data block located in the third storage area is divided a second time. If the data change frequency in the fourth storage area of ​​the target memory is less than a fourth preset value, then the target data block located in the fourth storage area is merged; wherein the third preset value is greater than the fourth preset value.

7. An electronic device, characterized in that, The electronic device includes a memory and a processor, the memory being used to store a computer program that, when executed by the processor, implements the method as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store a computer program that, when executed by a processor, implements the method as described in any one of claims 1 to 5.

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