A solid state disk adaptive reference clock compensation method and platform

Abstract

The present application relates to the technical field of solid state disk testing, in particular to a solid state disk adaptive reference clock compensation method and platform. It comprises the following steps: S1, running the solid state disk self-contained application software calling script, performing PCIe configuration space detection in the initialization stage; S2, enabling L1.2 function; S3, constructing platform library and obtaining host end parameters; S4, performing platform feature register detection; S5, application software calling script, responding to the SSD device entering L1.2 state; S6, after obtaining the host end parameters, starting the dynamic compensation process; S7, verifying the compensation effectiveness through LTSSM state machine low power switching. Compared with the prior art, aiming at the systematic failure caused by the system clock recovery difference of different CPUs when the SSD is in L1.2 low power state switching, the SSD self-contained application software is used to realize effective improvement of cross-platform timing compatibility through adaptive dynamic compensation.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solid state disk testing, in particular to a compensation method and platform for adaptive reference clock of a solid state disk. BACKGROUND

[0002] In a low-power state, turning off most modules in the link can make the PCIe terminal device, such as a solid state disk, consume almost no energy, which can greatly improve the endurance of mobile devices such as laptops.

[0003] With the continuous application of PCIe low-power technology, the differences in clock recovery mechanisms of different CPU manufacturers have led to increasingly significant system compatibility problems. There are significant differences in the clock recovery time of Intel, AMD, and domestic CPUs when exiting the L1.2 state. For example, the clock recovery time of a certain AMD processor is measured to be 14μs, which is much lower than the PCIe specification value of 150μs. This time difference causes the SSD device to receive the link training signal before completing the T_power_on initialization, thereby causing a series of system failures. These failures include:

[0004] 1. The SSD PHY layer receives the link training signal before completing the voltage stabilization detection.

[0005] 2. The system misjudges the device trigger blue screen, such as clock watchdog timeout error.

[0006] 3. Data verification failure: due to timing problems, the data verification code is incorrect during data transmission.

[0007] It is found through measurement that there are significant differences in clock recovery among mainstream CPU platforms: for example, AMD platform: Ryzen 5500U measured recovery time 14μs, which is 90.7% shorter than the specified value of 150μs. For example, Intel platform: Xeon 8480+ measured recovery time 32μs±5μs. For example, domestic platform: Feiteng S5000 series recovery time 80-120μs.

[0008] These differences make the existing firmware of SSD manufacturers unable to adapt to the timing characteristics of multiple platforms, highlighting some technical deficiencies. For example, firmware design defects: the existing SSD firmware only designs the delay according to the PCIe specification value, without fully considering the actual performance differences of different CPU manufacturers. For example, lack of state awareness: the SSD device cannot real-time sense the progress of CPU clock recovery, resulting in ineffective timing adjustment. SUMMARY

[0009] The application provides a solid state disk adaptive reference clock compensation method and platform to overcome the deficiencies of the prior art, based on the clock synchronization problem of a solid state disk device (SSD) in an L1.2 low-power state and different CPU platforms under a PCIe link, a dynamic sensing and compensation scheme is proposed.

[0010] To achieve the above-mentioned purpose, a solid state disk adaptive reference clock compensation method is designed, including the following steps:

[0011] S1, running a solid state disk self-contained application software calling script, performing PCIe configuration space detection in an initialization stage;

[0012] S2, enabling L1.2 function;

[0013] S3, constructing a platform library and obtaining host parameters;

[0014] S4, performing platform feature register detection;

[0015] S5, application software calling script, responding to the SSD device entering an L1.2 state;

[0016] S6, after obtaining the host parameters, starting a dynamic compensation process;

[0017] S7, verifying compensation effectiveness through an LTSSM state machine low-power switching.

[0018] The specific method of the step S1 is as follows:

[0019] S11, positioning a Capability chain table pointer: the script reads a device PCIe Capability pointer and is positioned to a Power Management Capability structure;

[0020] S12, basic PM Capability detection: reading a PM Capability structure and confirming that a PMCSR register supports an L1.2 substate;

[0021] S13, positioning an extended PM Capability and obtaining SSD parameters: positioning an extended power management capability structure of Cap ID=0x1E through a PCIe configuration space, analyzing T_POWERON_SCALE / VALUE fields and obtaining a theoretical recovery time T_power_on of the SSD device, the T_power_on being a theoretical time required for the SSD itself to recover from an L1.2 state to a normal state.

[0022] The specific method of the step S2 is as follows:

[0023] S21, ASPM low-power strategy configuration: set the ASPM field of the link control register to L0s+L1 enabled, and verify that L1.2 is a sub-state support bit; set PCI-PM L1.2 Enable=1 in the PCI-PM control register, and confirm that both devices support the L1.2 sub-state;

[0024] S22, LTR threshold setting: configure the delay tolerance report register according to the theoretical recovery time T_power_on of the SSD, and set the maximum acceptable exit delay to match the T_power_on value.

[0025] The specific method of step S3 is as follows:

[0026] S31, extract platform feature parameters by CPUID and PCH register:

[0027] S32, use the extracted data to generate a database stored in the application software provided with the solid state disk, and build a low-power strategy library of the platform.

[0028] In step S31, the parameters include processor manufacturer code obtained by CPUID instruction, CPU microarchitecture version obtained by SMBIOS Type4 record, and L1.2 reference timing extracted from PCH register by configuration space access script.

[0029] In step S4, the platform feature register of the Intel platform is detected: the script reads the PM_CFG4 register of the PCH to obtain the theoretical recovery time T_power_on value of the host end.

[0030] In step S4, the platform feature register of the AMD platform is detected: the script reads the PM_CTRL register of the FCH to obtain the theoretical recovery time T_power_on value of the host end.

[0031] The specific method of step S6 is as follows:

[0032] S61, when the theoretical recovery time T_power_on or T_SSD_min of the host end changes, recalculate T_hold and update the register, and trigger the script to start the dynamic compensation process;

[0033] S62, real-time parameter acquisition:

[0034] S621, read the PCIe device PMCSR register to obtain the current power state; S622, obtain T_SSD_min through the PHY register; S623, extract the actual timing from the CPU feature register;

[0035] S63: dynamic compensation calculation:

[0036] S631, ensure that T hold covers the worst case host power recovery time T power on and SSD response delay T SSD min; S632, select the vendor's preset fault tolerance parameter beta coefficient; S633, calculate the compensation value: T hold =max( T SSD min, T power on x beta+2us);

[0037] S64, register writing, write the compensation value calculated in step S63 to the host PCIe controller and PHY register: S641, modify the PCIe controller register; S642: synchronize the PHY timing update;

[0038] Wherein T hold represents the hold time, covering the worst case timing; T SSD min represents the shortest time that the CLKREQ# signal must maintain stable when the SSD switches from low power state.

[0039] In step S7, it is confirmed whether the actual recovery time of the host reference clock is less than T hold. If the actual recovery time is less than T hold, the link is normal and L1.2 exits the trigger; if the actual recovery time is greater than T hold, secondary compensation is triggered and the beta coefficient is updated, and L1.2 exit verification is performed again until the actual recovery time is less than T hold, the link is normal, and the test is exited.

[0040] To achieve the above purpose, a platform for a solid state disk adaptive reference clock compensation method is designed, comprising:

[0041] PC platform, for providing a multi-platform adaptive solid state disk reference clock compensation method verification environment;

[0042] PC host platform processor, for executing computer programs;

[0043] PC platform Linux operating system, manages and schedules computer software and hardware and data resources;

[0044] Application software, for storing feature library data, providing customers with solid state disks, and serving as an entry script;

[0045] Test script, for PCIe configuration space query; L1.2 function enablement; platform feature library establishment; platform feature judgment; control register sends pull high / pull low CLKREQ# signal; real-time parameter acquisition, dynamic compensation parameter writing; test result report;

[0046] PC platform memory, providing an environment for the operation of the PC platform operating system and the test script;

[0047] The solid-state drive under test.

[0048] Compared with existing technologies, this invention addresses the systemic failures caused by differences in system clock recovery due to different CPUs when SSDs switch to L1.2 low-power states. By utilizing the SSD's built-in application software, it achieves effective improvement in cross-platform timing compatibility through adaptive dynamic compensation. Attached Figure Description

[0049] Figure 1 This is a schematic diagram of the process of the present invention. Detailed Implementation

[0050] The present invention will now be further described with reference to the accompanying drawings.

[0051] like Figure 1 As shown, the compensation method for the adaptive reference clock of the solid-state drive in this embodiment includes the following steps:

[0052] S1 runs the application software that comes with the solid-state drive and calls the script to perform PCIe configuration space detection during the initialization phase;

[0053] S2 enables L1.2 functionality;

[0054] S3: Build the platform library and obtain host parameters;

[0055] S4, perform platform feature register detection;

[0056] S5, the application software calls the script to respond to the SSD device entering the L1.2 state;

[0057] S6, after obtaining the host parameters, start the dynamic compensation process;

[0058] S7 verifies the effectiveness of compensation through low-power switching of the LTSSM state machine.

[0059] The specific method for step S1 is as follows:

[0060] S11, Locate the Capability linked list pointer: The script reads the device PCIe Capability pointer and locates the Power Management Capability structure through the pointer offset of 0x34;

[0061] S12, Basic PM Capability Detection: Read the PM Capability structure, Cap ID=0x01, and confirm that the PMCSR register supports L1.2 sub-state;

[0062] S13, locate the extended PM Capability, Cap ID=0x1E, get the SSD side parameters: locate the extended power management capability structure of Cap ID=0x1E through the PCIe configuration space, analyze the T_POWERON_SCALE / VALUE field, and get the theoretical recovery time T_power_on of the SSD device. T_power_on is the theoretical time required for the SSD itself to recover to a normal state from L1.2.

[0063] In step S12, Bit[5]=1 is set.

[0064] The specific method of step S2 is as follows:

[0065] S21, ASPM low-power strategy configuration: set the ASPM field of the link control register to L0s+L1 enabled, and verify that L1.2 is a sub-state support bit; set PCI-PM L1.2 Enable=1 in the PCI-PM control register, and confirm that both devices support the L1.2 sub-state;

[0066] S22, LTR threshold setting: configure the delay tolerance reporting register according to the theoretical recovery time T_power_on of the SSD, and set the maximum acceptable exit delay to match the T_power_on value.

[0067] The specific method of step S3 is as follows:

[0068] S31, extract platform feature parameters by CPUID and PCH register:

[0069] S32, use the extracted data to generate a database and store it in the application software provided with the solid state disk, and build a low-power strategy library for the platform.

[0070] In step S31, the parameters include the processor manufacturer code obtained by the application software calling script through the CPUID instruction, the CPU microarchitecture version obtained by the script reading the SMBIOS Type4 record, and the L1.2 reference timing extracted by the script accessing the PCH register from the configuration space.

[0071] In specific use, the application can be applied in different types of CPU platforms. When applied in an Intel platform, in step S4, platform feature register detection is performed on the Intel platform: the script reads the PM_CFG4 register of the PCH to obtain the theoretical recovery time T_power_on value of the host end. In this embodiment, the bit field corresponding to the PM_CFG4 register is Bus 0, Device 0x1F, Offset 0xE4. When applied in an AMD platform, in step S4, platform feature register detection is performed on the AMD platform: the script reads the PM_CTRL register of the FCH to obtain the theoretical recovery time T_power_on value of the host end.

[0072] In step S5, the Intel platform is taken as an example in this embodiment, and the CLKREQ# of the PCH is forcibly pulled high through the PM_CFG register of the PCH, so that the SSD device enters the L1.2 state.

[0073] The specific method of step S6 is as follows:

[0074] S61, when the theoretical recovery time T_power_on or T_SSD_min of the host end changes, recalculate T_hold and update the register, and trigger the script to start the dynamic compensation process;

[0075] S62, real-time parameter acquisition:

[0076] S621, read the PCIe device PMCSR register to obtain the current power state; S622, obtain T_SSD_min through the PHY register; S623, extract the actual timing from the CPU feature register;

[0077] S63: dynamic compensation calculation:

[0078] S631, ensure that T_hold covers the host end power recovery time T_power_on and the SSD response delay T_SSD_min in the worst case; S632, according to the vendor, select the vendor's preset fault tolerance parameter β coefficient; S633, calculate the compensation value: T_hold =max( T_SSD_min, T_power_on× β+2μs);

[0079] The fault tolerance parameter β of the Intel platform is 1.2, the fault tolerance parameter β of the AMD platform is 1.8, and the fault tolerance parameter β of the domestic platform is 1.0.

[0080] S64, register writing, write the compensation value calculated in step S63 to the host PCIe controller and PHY register: S641, modify the PCIe controller register; S642: synchronously update the PHY timing.

[0081] Wherein T hold represents the hold time, covering the worst-case timing; T SSD_min represents the shortest time that the CLKREQ# signal must maintain stable when the SSD switches in the low-power state, ensuring that the internal circuit of the SSD completes the state switching, avoiding data loss or link errors due to insufficient timing.

[0082] In step S7, it is confirmed whether the actual recovery time of the host reference clock is less than T hold. If the actual recovery time is less than T hold, the link is normal, and L1.2 exits the trigger; if the actual recovery time is greater than T hold, secondary compensation is triggered and the beta coefficient is updated, and L1.2 exit verification is performed again until the actual recovery time is less than T hold, the link is normal, and the test is exited.

[0083] In step S7, it is confirmed whether the actual recovery time of the host reference clock is less than T hold. If the actual recovery time is less than T hold, the link is normal, and L1.2 exits the trigger; if the actual recovery time is greater than T hold, secondary compensation is triggered and the beta coefficient is updated, and L1.2 exit verification is performed again until the actual recovery time is less than T hold, the link is normal, and the test is exited.

[0084] The platform of the above-mentioned solid state disk adaptive reference clock compensation method comprises:

[0085] The PC platform is used to provide a verification environment for a multi-platform adaptive solid state disk reference clock compensation method;

[0086] The PC host platform processor is used to execute a computer program;

[0087] The PC platform Linux operating system manages and schedules computer hardware and data resources;

[0088] The application software is used to store feature library data, which is provided to customers with the solid state disk and serves as an entry for calling scripts;

[0089] The test script is used for PCIe configuration space query; L1.2 function enablement; platform feature library establishment; platform feature judgment; control register sending pull-up / pull-down CLKREQ# signal; real-time parameter acquisition, dynamic compensation parameter writing; test result report;

[0090] The PC platform memory provides an environment for the operation of the PC platform operating system and the test script;

[0091] The solid state disk to be tested.

[0092] The application provides a self-adaptive dynamic compensation mechanism through application software of a solid state disk, and significantly improves cross-platform compatibility of PCIe low-power state switching. A feature recognition unit detects platform types through a CPUID instruction in real time, belongs to which of Intel, AMD and domestic products, automatically matches an optimal compensation parameter beta coefficient, and solves the adaptation problem of a traditional fixed threshold scheme under different platforms.

Claims

1. A compensation method for an adaptive reference clock in a solid-state drive, characterized in that: Includes the following steps: S1 runs the application software that comes with the solid-state drive and calls the script to perform PCIe configuration space detection during the initialization phase; S2 enables L1.2 functionality; S3: Build the platform library and obtain host parameters; S4, perform platform feature register detection; S5, the application software calls the script to respond to the SSD device entering the L1.2 state; S6, after obtaining the host parameters, start the dynamic compensation process; S7 verifies the effectiveness of compensation through low-power switching of the LTSSM state machine; The specific method for step S6 is as follows: S61, when the theoretical recovery time T_power_on or T_SSD_min on the host changes, recalculate T_hold and update the register, triggering the script to start the dynamic compensation process; S62, Real-time Parameter Acquisition: S621, Read the PCIe device PMCSR register to obtain the current power status; S622, Obtain T_SSD_min through the PHY register; S623, Extract the actual timing from the CPU feature register; S63: Dynamic Compensation Calculation S631, ensure that T_hold covers the worst-case host power recovery time T_power_on and SSD response latency T_SSD_min; S632, select the manufacturer's preset fault tolerance parameter β coefficient according to the manufacturer; S633, calculate the compensation value: T_hold = max( T_SSD_min, T_power_on × β + 2μs); S64, Register write: Write the compensation value calculated in step S63 to the host PCIe controller and PHY register; S641, Modify PCIe controller register; S642: Synchronously update PHY timing; Where T_hold represents the hold time, covering the worst-case timing; T_SSD_min represents the shortest time that the CLKREQ# signal must remain stable when the SSD switches to a low-power state.

2. The compensation method for an adaptive reference clock in a solid-state drive according to claim 1, characterized in that: The specific method of step S1 is as follows: S11, Locate the Capability linked list pointer: The script reads the device PCIe Capability pointer and locates the PowerManagement Capability structure; S12, Basic PM Capability Detection: Read the PM Capability structure and confirm that the PMCSR register supports the L1.2 sub-state; S13, Locate the extended PM Capability and obtain SSD-side parameters: Locate the extended power management capability structure of Cap ID=0x1E through the PCIe configuration space, parse the T_POWERON_SCALE / VALUE field, and obtain the theoretical recovery time T_power_on of the SSD device. T_power_on is the theoretical time required for the SSD itself to recover from L1.2 to the normal state.

3. The compensation method for an adaptive reference clock in a solid-state drive according to claim 1, characterized in that: The specific method for step S2 is as follows: S21, ASPM low-power policy configuration: Set the ASPM field of the link control register to L0s+L1 enable, and verify that L1.2 is a sub-state support bit; set PCI-PM L1.2 Enable=1 in the PCI-PM control register to confirm that both devices support L1.2 sub-state; S22, LTR Threshold Setting: Configure the latency tolerance report register based on the SSD's theoretical recovery time T_power_on, and set the maximum acceptable exit latency to match the T_power_on value.

4. The compensation method for an adaptive reference clock in a solid-state drive according to claim 1, characterized in that: The specific method for step S3 is as follows: S31, platform feature parameter extraction is obtained through CPUID and PCH registers: S32 uses extracted data to generate a database stored in the application software that comes with the solid-state drive, and builds the platform's low-power strategy library.

5. The compensation method for an adaptive reference clock in a solid-state drive according to claim 4, characterized in that: In step S31, the parameters include the application software calling the script to obtain the processor manufacturer code through the CPUID instruction, the script reading the SMBIOS Type4 record to obtain the CPU microarchitecture version, and the script accessing the PCH register from the configuration space to extract the L1.2 reference timing.

6. The compensation method for an adaptive reference clock in a solid-state drive according to claim 1, characterized in that: In step S4, platform characteristic register detection is performed on the Intel platform: the script reads the PM_CFG4 register of the PCH to obtain the theoretical recovery time T_power_on value of the host.

7. The compensation method for an adaptive reference clock in a solid-state drive according to claim 1, characterized in that: In step S4, platform characteristic register detection is performed on the AMD platform: the script reads the PM_CTRL register of FCH to obtain the theoretical recovery time T_power_on value of the host side.

8. The compensation method for an adaptive reference clock in a solid-state drive according to claim 1, characterized in that: In step S7, it is confirmed whether the actual recovery time of the host reference clock is less than T_hold. If the actual recovery time is less than T_hold, the link is normal and L1.2 exits the trigger. If the actual recovery time is greater than T_hold, a secondary compensation is triggered and the β coefficient is updated. The L1.2 exit verification is performed again until the actual recovery time is less than T_hold, the link is normal, and the test is exited.

9. A platform for a compensation method of an adaptive reference clock for a solid-state drive according to any one of claims 1 to 8, characterized in that: include: A PC platform is provided as a verification environment for a multi-platform adaptive solid-state drive reference clock compensation method. PC host platform processor, used to execute computer programs; The PC platform uses the Linux operating system to manage and schedule computer hardware, software, and data resources. Application software, used to store feature library data, is provided to customers along with the solid-state drive and serves as the entry point for calling scripts; Test scripts are used for PCIe configuration space query; L1.2 function enabling; platform feature library establishment; platform feature judgment; The control register sends a high / low CLKREQ# signal; real-time parameter acquisition and dynamic compensation parameter writing; test result reporting; PC platform memory provides an environment for the PC platform operating system and the test script to run; The solid-state drive under test.

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