Test case dynamic priority scheduling method for automobile electronic chip

Abstract

The invention relates to the field of task queue scheduling of automobile chips, in particular to a test case dynamic priority scheduling method for automobile electronic chips. Comprising the following steps: analyzing standard test data of the automobile electronic chip, and organizing a structured data set associated with the physical layout of the chip; identifying failure clusters and noise points on the structured data set by using a data clustering algorithm; extracting geometric and position features of the failure cluster, classifying the failure cluster into a known failure mode by using a classifier, performing correlation analysis on the failure mode, an upstream key process step and an equipment log, and establishing a causal relationship; calculating a function security risk score for each chip; and when the function security risk score is higher than a preset risk threshold value, generating and executing a dynamic task rearrangement instruction, and dynamically improving the execution priority of the test case. According to the method, the priority is dynamically selected according to the function security risk score through the dynamic task rearrangement instruction, so that the test time is saved, and the coverage depth and quality of the test are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip test scheduling management, and particularly to a test case dynamic priority scheduling method for automotive electronic chips. BACKGROUND

[0002] In the production test of modern automotive electronic chips, in order to ensure that the product meets the stringent quality and functional safety standards, a large test set containing tens of thousands of test cases must be executed. However, there is a contradiction between ensuring test coverage and maximizing production throughput, and the cost of completely executing all test cases is too high. To solve this problem, the industry generally uses test case priority sorting (TCP) technology, the core idea of which is to optimize the execution order of test cases to discover critical defects as soon as possible within a limited time, thereby maximizing fault detection rate.

[0003] Although test case priority sorting (TCP) aims to improve test efficiency, the current commonly used technical methods have several inherent and universal defects, especially when dealing with large-scale and highly dynamic production environments, many existing TCP technologies are inefficient. When the test suite is large and contains a large number of test cases with the same initial priority, these technologies are difficult to effectively sort, often leading to improper scheduling and cost overruns. Moreover, the sorting algorithm is often rigid and may ignore actual weight factors or use inefficient weight algorithms. This "one-size-fits-all" model cannot adapt to dynamic changes in the production process, and its sorting basis is usually historical data or preset assumptions, which may no longer be applicable to the specific wafer batch currently being processed. Or generating a fixed execution sequence at one time before test execution may not be able to respond to sudden trends that occur in the production process.

[0004] In summary, there is a need for a method that can receive and analyze inputs from a manufacturing data system and map these inputs as dynamic adjustment factors for test case priority, thereby generating an adaptive and optimized test execution sequence for each batch of chips to be tested.

[0005] To this end, a test case dynamic priority scheduling method for automotive electronic chips is proposed. SUMMARY

[0006] The present application aims to provide a test case dynamic priority scheduling method for automotive electronic chips to solve the problems raised in the background art.

[0007] To achieve the above-mentioned purpose, the present application provides the following technical solution: a test case dynamic priority scheduling method for automotive electronic chips, comprising: Collect and analyze standard test data of automotive electronic chips; extract structured data sets including wafer ID, physical coordinates of each chip and software bin number; apply data clustering algorithm to identify aggregated failure clusters; Extract geometric and positional features from the failure clusters, and use a classifier to classify them into known failure modes; query the manufacturing execution system and equipment automation system through the wafer ID to associate the failure modes with process steps and equipment logs, and match them with the failure root cause knowledge base to establish causal relationships; analyze historical test results, calculate the frequency of failure modes, and perform statistical significance test with the failure rate of the production line baseline to obtain a diagnostic confidence score, and store the diagnostic confidence score and causal relationships in the failure root cause knowledge base; For each chip, calculate the Euclidean distance between the physical coordinates and the centroid of all failure clusters; combine the severity weight of the failure mode associated with the failure cluster and the spatial influence factor obtained by principal component analysis of the physical coordinates of the chips in the failure cluster to quantify the risk coverage range of the failure cluster; and combine the weighted sum function with Gaussian attenuation to obtain the functional safety risk score. Compare the functional safety risk score with the preset risk threshold value, when the functional safety risk score is higher than the risk threshold value, analyze the composition of the functional safety risk score, identify the most dangerous failure cluster that contributes most to the risk, generate and execute dynamic task rearrangement instructions, dynamically improve the execution priority of the most sensitive test cases of the associated failure mode, and perform testing; when unqualified is detected, terminate all subsequent testing of the chip and classify it into a high-risk isolated batch.

[0008] Preferably, the specific generation process of the structured data set comprises: Collect and analyze standard test data of automotive electronic chips, extract wafer ID, physical coordinates of chips on the wafer and software bin number, and form key data tuples; according to the preset mapping rule, perform data conversion on the software bin number, map the test results to binary data labels; create a two-dimensional matrix according to the physical size of the wafer; traverse all chip data of the wafer, fill the binary data label of each chip into the position corresponding to the physical coordinates in the matrix, and form a structured data set.

[0009] Preferably, the specific process of identifying the aggregated failure clusters and isolated noise points on the structured data set comprises: The density-based unsupervised clustering algorithm is selected, the neighborhood radius and the minimum number of points are set according to the physical size of the chip and the process experience, and the physical coordinates of all the failed chips in the structured data set are taken as the input point set; each failed chip is traversed, and according to the density of the failed chips within the neighborhood radius, it is divided into three categories: core point: the number of failed chips contained is not less than the preset minimum number of points; boundary point: the number of failed chips contained is less than the minimum number of points, but within the neighborhood radius of the core point; noise point: the failed chip that is neither a core point nor a boundary point; starting from the core point that has not been accessed, a new failed cluster is created, and all the connectable core points and their associated boundary points are assigned to the same failed cluster through recursion.

[0010] Preferably, the specific process of classifying into known failure modes using the classifier includes: A set of geometric and positional features is calculated and extracted from the failed cluster; the geometric and positional features are taken as the input of the pre-trained classifier, and the classifier outputs a failure mode label from a predefined library of automotive chip labels; the geometric and positional features include cluster size, cluster density, centroid coordinates, relative position, and elongation obtained by principal component analysis.

[0011] Preferably, the specific generation process of establishing causal relationships includes: When the failed cluster is assigned a failure mode label, a concurrent query is initiated to the manufacturing execution system and the equipment automation system by triggering the wafer ID; the full life cycle manufacturing data associated with the wafer ID is retrieved from the manufacturing execution system database; the process parameter log within the time window of processing the wafer is retrieved from the equipment automation system database according to the full life cycle manufacturing data; the process parameter log is compared with the preset control limit to detect the existence of out-of-specification conditions, and when a process parameter anomaly is detected, it is matched with the pre-set failure root cause knowledge base; the causal relationship established with the process step and the equipment log is stored in the database, and the failure root cause knowledge base is dynamically updated by the judgment of process experts.

[0012] Preferably, the specific generation process of the functional safety risk score includes: The centroid coordinates of all failed clusters are obtained by traversing each chip on the wafer, and for any chip, the Euclidean distance between the physical coordinates and the centroid coordinates of each failed cluster is calculated; according to the failure mode associated with each failed cluster, a quantitative severity weight based on the causal relationship is assigned, and principal component analysis is performed on the physical coordinates of all chips in the failed cluster to determine a spatial influence factor; the Euclidean distance, the severity weight and the spatial influence factor are input into a weighted summation function combined with Gaussian attenuation to calculate the functional safety risk score; the functional safety risk score is associated with the chip identifier combined with the wafer ID and the physical coordinates, and stored in the database.

[0013] Preferably, the specific process of dynamically promoting the execution priority of the test case most sensitive to the associated failure mode comprises: Taking the chip identifier as the database query key, querying the functional safety risk score from the database, and comparing it with the preset risk threshold, if the functional safety risk score is higher than the risk threshold, it is determined that the chip is high-risk, and a dynamic task rearrangement instruction is generated and executed to dynamically promote the execution priority of the test case most sensitive to the associated failure mode; the data structure of the original task queue is reordered to generate a new task queue, and the test case with high priority is placed at the front end of the task queue; when unqualified is detected, all subsequent tests on the chip are immediately terminated and are classified into a high-risk isolated batch.

[0014] Preferably, the specific process of generating and executing the dynamic task rearrangement instruction comprises: When it is determined that the chip is high-risk, the composition of the functional safety risk score is analyzed, the most dangerous failure cluster that contributes most to the risk is identified, and the failure mode label associated with the dangerous failure cluster is retrieved; through the preset database of storing the mapping relationship between the test case and the failure mode, the test case with high detection sensitivity to the failure mode label is screened out, and the execution priority of the test case is dynamically promoted to the highest.

[0015] Compared with the prior art, the beneficial effects of the present application are: 1. The density-based unsupervised clustering algorithm is applied to identify the failure cluster on the structured data set, and further, through the wafer ID, the manufacturing execution system and the equipment automation system are queried to analyze the association between the failure mode and the upstream key process step and the equipment log, thereby providing accurate clues for process engineers to quickly locate the problem equipment or process step, shortening the time from problem discovery to problem solving, effectively curbing the spread of systematic defects, and improving the overall production line yield from the source. When more data confirms or refutes the causal relationship, the confidence score will be dynamically updated. This confidence score provides engineers with an intuitive judgment of diagnostic reliability, making the entire risk assessment system more data-driven and intelligent.

[0016] 2. The mechanism of calculating the Euclidean distance between each chip in the wafer and the centroid of all failed clusters, combining the root cause severity, and determining a spatial impact factor by performing principal component analysis on the physical coordinates of all chips within a failed cluster, and then combining a weighted sum function with Gaussian decay to obtain the functional safety risk score, can identify chips that have passed the CP test by chance but are highly likely to carry potential defects due to their presence in high-risk physical proximity areas, helping to prevent flawed chips from entering the final product, thereby greatly improving product safety and reliability. Integrating risk assessment with analysis of failure root cause severity can identify chips that have passed preliminary testing but are highly likely to carry potential defects due to their presence in high-risk manufacturing environments, playing a crucial role in meeting zero-defect requirements in the automotive electronics and other fields.

[0017] 3. When a chip with a functional safety risk score higher than the risk threshold enters the FT test station, trace the failure cluster and its associated failure mode that is the main source of risk, and query the preconfigured failure mode and test case mapping database to dynamically improve the execution priority of the most sensitive test cases associated with the failure mode. This means that the testing process is transformed from a fixed test sequence to a queue with dynamically adjustable priorities. This testing strategy improves the probability of detecting critical defects early in the testing process, and once a failure is detected, the test can be terminated immediately, saving a lot of testing time for high-risk chips, and ensuring that the most effective stress testing for potential defects is performed first, thereby improving the depth and quality of testing, effectively preventing chips carrying potential defects from entering the market, and ensuring the reliability of the final product. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 A flowchart of a test case dynamic priority scheduling method for automotive electronic chips according to an embodiment of the present application; Figure 2 A schematic diagram of a structured data set according to an embodiment of the present application; Figure 3 A functional safety risk score distribution thermodynamic diagram according to an embodiment of the present application; Figure 4 A flowchart of an optimized test task queue according to an embodiment of the present application. DETAILED DESCRIPTION

[0019] Clearly and completely, the technical solutions in the embodiments of the present application will be described in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0020] Referring to Figures 1-4 The present application provides a test case dynamic priority scheduling method for automotive electronic chips, and the specific steps are as follows: Collect and analyze the standard test data of the automotive electronic chip; extract the structured data set including wafer ID, physical coordinates of each chip and software bin number; apply data clustering algorithm to identify the aggregated failure cluster; Extract the geometric and positional features of the failure cluster, and use the classifier to classify into known failure modes; query the manufacturing execution system and the device automation system through the wafer ID, associate and analyze the failure mode with the process step and the device log, and match with the failure root cause knowledge base to establish the causal relationship; analyze the historical test results, calculate the frequency of the failure mode, and perform statistical significance test with the failure rate of the production line baseline to obtain the diagnostic confidence score, and store the diagnostic confidence score and the causal relationship in the failure root cause knowledge base; For each chip, calculate the Euclidean distance between the physical coordinates and the centroid of all failure clusters; and combine the severity weight of the failure mode associated with the failure cluster and the spatial influence factor for quantifying the risk coverage range of the failure cluster obtained by principal component analysis on the physical coordinates of the chips of the failure cluster, to obtain the functional safety risk score through the weighted summation function combined with Gaussian attenuation; Compare the functional safety risk score with the preset risk threshold value, when the functional safety risk score is higher than the risk threshold value, analyze the composition of the functional safety risk score, identify the most dangerous failure cluster with the greatest risk contribution, generate and execute the dynamic task rearrangement instruction, dynamically improve the execution priority of the test case of the most sensitive failure mode associated with the failure mode, and perform the test; when the unqualified is detected, terminate all subsequent tests on the chip immediately, and enter the high-risk isolated batch.

[0021] The technical solutions of the present application will be further described in combination with specific embodiments.

[0022] Embodiment one The embodiments of the present application disclose a test case dynamic priority scheduling method for automotive electronic chips, referring to Figure 1The specific steps include: S1, collecting and analyzing standard test data of the automobile electronic chip; extracting a structured data set including wafer ID, physical coordinates of each chip, and software bin number; S2, applying a data clustering algorithm to identify aggregated failure clusters; S3, extracting geometric and positional features of the failure clusters, and using a classifier to classify them into known failure modes; querying the manufacturing execution system and the device automation system through the wafer ID, correlating the failure modes with process steps and device logs, and matching them with the failure root cause knowledge base to establish causal relationships; analyzing historical test results, calculating the frequency of failure modes, and performing statistical significance test with the failure rate of the production line baseline to obtain a diagnostic confidence score, and storing the diagnostic confidence score and the causal relationship in the failure root cause knowledge base; S4, for each chip, calculating the Euclidean distance between the physical coordinates and the centroid of all failure clusters; and combining the severity weight of the failure mode associated with the failure cluster and the spatial influence factor for quantifying the risk coverage range of the failure cluster obtained by principal component analysis on the physical coordinates of the chips in the failure cluster, to obtain a functional safety risk score through the weighted sum function of Gaussian attenuation; S5, comparing the functional safety risk score with the preset risk threshold, when the functional safety risk score is higher than the risk threshold, analyzing the composition of the functional safety risk score, identifying the most dangerous failure cluster with the largest risk contribution, generating and executing dynamic task rearrangement instructions, dynamically improving the execution priority of the most sensitive test case of the associated failure mode, and testing; when the unqualified is detected, all subsequent tests on the chip are terminated immediately, and the chip is classified into a high-risk isolated batch.

[0023] Further, the standard test data of the automobile electronic chip is collected and analyzed; a structured data set including wafer ID, physical coordinates of each chip, and software bin number is extracted; corresponding to the above S1 step; refer to Figure 2 ; the specific implementation process includes: When an automatic test equipment (ATE) completes the wafer probe (CP) test of a wafer, a standard binary test data file, i.e., standard test data, will be generated. The generation of the file will serve as a trigger signal to automatically start the analysis program to read the standard test data: WIR (Wafer Information Record): extract wafer ID (WAFER ID); PRR (Part Results Record): this record is for each independent chip (Die), from which the physical coordinates (X_COORD, Y_COORD) of the chip on the wafer and its final software bin number (SOFT_BIN) are extracted.

[0024] The key data tuples (WAFER ID, X_COORD, Y_COORD, SOFT BIN) are sent to the database of the data analysis center (DAC) after preliminary cleaning and integration, forming a standardized wafer test result dataset.

[0025] For a specific wafer ID, retrieve the physical coordinates and software bin numbers of all chips on the wafer from the database of the data analysis center. Then, according to the pre-set mapping rules, make logical judgments on the software bin number results of each chip. Usually, SOFT BIN is 1, representing a test pass, and all other non-1 values represent different types of failures. According to the above definition, map the test results of each chip to binary data labels: 0 represents normal, and 1 represents failure. Finally, create a two-dimensional matrix according to the physical size of the wafer, and fill the binary data label (0 or 1) of each chip into the position corresponding to its physical coordinates in the matrix. This completely filled two-dimensional matrix constitutes the digital structured dataset of the wafer.

[0026] By analyzing the standard test data generated by the automatic test equipment after CP testing, which contains the wafer ID, and extracting the physical coordinates and software bin results of each chip, the integrity and traceability of the data are ensured. By mapping these data into a two-dimensional matrix, a structured dataset is generated, which realizes the key step of spatializing discrete test results and accurately reproduces the physical distribution of all failed chips on the wafer, laying a solid data foundation for stable, reliable, and automated failure mode analysis.

[0027] Further, a data clustering algorithm is applied to identify clustered failure clusters; corresponding to the above S2 step; the specific process includes: This embodiment selects a density-based unsupervised clustering algorithm, such as DBSCAN (Density-Based Spatial Clustering of Applications with Noise), which does not need to specify the number of clusters in advance and can effectively identify clusters of arbitrary shape, which is very suitable for discovering various systematic defect patterns in semiconductor manufacturing. In the data analysis center, according to the physical size of the chip and process experience, two key parameters are set: neighborhood radius: defines a physical distance to determine the "neighborhood" range around a failed chip.

[0028] minimum number of points: defines the minimum number of failed chips required to form a dense area (i.e. the core of the cluster) within the neighborhood radius of a failed chip.

[0029] DBSCAN takes the physical coordinates of all failed chips in a structured dataset as input point set. Then each failed chip point is traversed and automatically classified into three categories according to the density of failed points in its neighborhood: Core point: A chip contains more failed points than the minimum point number in its neighborhood radius. Core points are considered as internal points of systematic failure clusters.

[0030] Boundary point: A chip contains less failed points than the minimum point number in its neighborhood radius, but the point itself falls in the neighborhood of a core point. Boundary points are considered as the edge of failure clusters.

[0031] Noise point: A failed chip that is neither a core point nor a boundary point. These points usually correspond to random defects (Type-A defects) in semiconductor manufacturing and will be identified as isolated noise points.

[0032] DBSCAN starts from an arbitrary unvisited core point and creates a new cluster. By recursion or iteration, all core points and associated boundary points that can be connected by a sequence of core point neighborhoods from this core point are assigned to the same cluster. When a cluster can no longer be expanded, the next unvisited core point is selected and the process is repeated until all core points are assigned to a cluster.

[0033] After the first-stage clustering algorithm is completed, the physical coordinates of all failed chips marked as noise points are collected to form a residual dataset; a density-sensitive clustering algorithm is applied to the residual dataset to identify weak signal clusters that are ignored due to low density and uneven distribution. Features are extracted for them and attempts are made to classify and analyze the root cause. This two-stage analysis process retains the ability to identify high-density "strong signal" failure clusters while increasing the ability to detect low-density "weak signal" clusters, thus building a more comprehensive and forward-looking failure mode monitoring system.

[0034] Through the above steps, the failed points on the structured dataset are divided into one or more failure clusters with physical aggregation (composed of core points and boundary points), and at the same time, those random failed points that do not meet the characteristics of systematic aggregation are effectively distinguished.

[0035] By applying a density-based unsupervised clustering algorithm, statistically significant aggregated failure clusters can be automatically identified from structured datasets. This allows subsequent analysis resources to focus on tracing and solving the root causes of systematic problems that truly affect line stability and overall yield, improving the efficiency and accuracy of fault diagnosis and avoiding the waste of valuable engineering resources on random failures.

[0036] Further, geometric and location features are extracted from the failure cluster, and a classifier is used to categorize the failure mode; through wafer ID query of manufacturing execution system and equipment automation system, the failure mode is associated with process steps and equipment logs, and matched with the failure root cause knowledge base to establish causal relationship; historical test results are analyzed, the frequency of the failure mode is calculated, and statistical significance test is performed with the failure rate of the production line baseline to obtain a diagnostic confidence score, and the diagnostic confidence score and the causal relationship are stored in the failure root cause knowledge base; the above S3 step is corresponded to; the specific implementation process includes: For each independent failure cluster, a set of feature vectors quantifying its physical morphology and distribution characteristics is calculated and extracted. The process includes: Cluster size: the total number of failed chips constituting the cluster is calculated.

[0037] Cluster density: the ratio of the size of the cluster to the area of its minimum bounding box is calculated to quantify its compactness.

[0038] Centroid coordinates: the arithmetic mean of the physical coordinates of all failed chips in the cluster is calculated to determine its geometric center.

[0039] Relative position: according to the distance between the centroid coordinates and the center of the wafer, the position of the cluster is categorized into predefined areas such as "center", "edge" or "corner".

[0040] Elongation: the physical coordinates of all failed chips in the cluster are regarded as a two-dimensional point set, and principal component analysis is applied to obtain the ratio of the eigenvalues corresponding to the first principal component (representing the longest axis direction of the cluster) and the second principal component (representing the shortest axis direction).

[0041] After obtaining the feature vector, a pre-trained classifier (e.g., support vector machine SVM) is input to process the input feature vector. The support vector machine is trained based on a large amount of historical wafer map data labeled by process experts in the data analysis center, and can identify the mapping relationship between the feature vector and the known failure mode, automatically and accurately classify the input feature vector into a known failure mode, and assign the most matching failure mode label. Specifically, the training data set of the pre-trained support vector machine (SVM) classifier can be selected from at least 10,000 wafer maps accurately labeled by failure analysis engineers as training data set. To ensure the generalization ability of the model, the data set needs to cover at least 15 typical systematic failure modes in semiconductor manufacturing, including but not limited to center aggregation, edge ring, local area, scratch, and repeated occurrence, etc., and over-sampling or under-sampling technology is used to ensure that the number of samples of each failure mode in the data set is not less than 200. A support vector machine model with strong generality and stable effect is selected, and a grid search combined with five-fold cross-validation method is used to automatically determine the hyperparameters of the model. Among them, the search range of the penalty coefficient C is set to [0.1, 100], and the search range of the gamma value is set to [0.001, 10]. Finally, a label library is defined and applied. The pre-defined label library relied on by the classifier contains a standardized failure mode ID and description mapping list, which serves as the output standard of the classifier. For example: {1: center aggregation, 2: edge ring, 3: scratch,..., 15: specific device cavity contamination type}. When a new failure cluster feature vector is input, the trained SVM model will output the most matching failure mode label.

[0042] At the same time when the classifier outputs the failure mode label, the confidence score is obtained. The absolute value of the confidence score is compared with the preset confidence threshold. When the confidence score is lower than the confidence threshold, the failure mode label will be automatically marked as "low confidence", and a human-machine loop process is triggered; all failure mode labels marked as low confidence are pushed to a dedicated review queue, and process experts reconfirm the failure mode label according to their professional knowledge; if the failure mode is a new type, the process expert creates a new failure mode category; the failure mode label confirmed by the expert is automatically added back to the training data set of the classifier for accumulation until the incremental retraining of the SVM classifier is triggered. Through this closed-loop feedback mechanism, new or difficult-to-identify failure mode cases can be actively identified and learned, continuously improving the recognition ability of new failure modes and the discrimination accuracy of ambiguous modes.

[0043] When a failed cluster is assigned a failure mode label (e.g. "edge ring"), a query request is automatically initiated to the upstream manufacturing execution system and equipment automation system, with the wafer ID (WAFER ID) and test completion timestamp as the key index. From the manufacturing execution system database, the full life cycle manufacturing data associated with the wafer ID is retrieved, including but not limited to: the wafer lot number it belongs to, the mask layer number used, the equipment number of the etching machine, thin film deposition equipment, and the process recipe followed in each critical step.

[0044] From the equipment automation system database, the process parameter logs collected and recorded in real time by the above-mentioned key equipment during the processing of the wafer lot in which the wafer is located are retrieved. For example, these parameters specifically include: the radio frequency power and gas flow of the plasma etching machine, the temperature and pressure during thin film deposition, the polishing pressure of chemical mechanical polishing, etc.

[0045] The retrieved process parameter logs are compared with the control limits preset by the process recipe to detect abnormal fluctuations. And the detected process anomalies are matched with a pre-set failure root cause knowledge base. The construction and updating process of the knowledge base includes: a) import the initial FMEA (Failure Mode and Effects Analysis) data jointly formulated by design, process, equipment and other multi-disciplinary experts; b) automatically mine historical production data, verify and correct existing causal relationships, and discover new associations; c) establish an automated entry interface for new root cause analysis (RCA) reports to ensure continuous learning and iteration. For example, when a wafer is found to present a "edge ring" failure mode, and at the same time an abnormal radio frequency power is found in the EAP log of its etching step, a high-confidence causal relationship is established: "the 'edge ring' failure of the current wafer is most likely caused by power fluctuations of the etching machine".

[0046] The causal relationship established with the process step and equipment log is taken as a hypothesis to be verified, and the historical production database is automatically queried to retrieve all wafer lots that have been processed by the equipment and have changed parameters, and the wafer test results of the wafer lots are analyzed to calculate the frequency of failure mode occurrence. Through statistical significance test with the failure rate of the production line baseline, based on the results of the statistical significance test, the frequency of failure mode occurrence, and the initial weight preset by the process expert for the causal relationship, a comprehensive diagnostic confidence score is calculated, and the diagnostic confidence score and the causal relationship are stored in the failure root cause knowledge base. When more data confirms or refutes the causal relationship subsequently, its confidence score will be dynamically updated. This confidence score provides engineers with an intuitive judgment of diagnostic reliability, making the entire risk assessment system more data-driven and intelligent.

[0047] By extracting geometric and location features from the failure clusters, a set of points with no specific meaning is quantified into a set of feature vectors that can be analyzed. By using a classifier to categorize into known failure patterns, the failure clusters are given a standardized, engineer-understandable label. This allows subsequent root cause tracing to be no longer a purposeless data mining, but a more targeted correlation analysis based on the classified patterns, significantly improving the efficiency and accuracy of diagnosis. By querying the manufacturing execution system and equipment automation system through wafer ID, the barrier between test data and upstream manufacturing data is broken down, and the integration of full-process data is achieved. On this basis, the failure patterns are correlated with upstream key process steps and equipment logs to establish causal relationships, providing a high-confidence diagnostic report for process engineers. This shortens the cycle from discovering yield problems to locating problem sources, enabling fast and accurate feedback on the production process, so that corrective measures can be taken in time to effectively curb the generation of defects and improve product yield from the source.

[0048] Further, for each chip, the Euclidean distance between the physical coordinates and the centroid of all failure clusters is calculated; and the severity weight of the failure mode associated with the failure cluster is combined with the spatial influence factor obtained by principal component analysis of the physical coordinates of the chips of the failure cluster to quantify the risk coverage range of the failure cluster, and the functional safety risk score is obtained by combining the weighted sum function of Gaussian attenuation; corresponding to the above S4 step; refer to Figure 3 ; the specific implementation process includes: Iterate through each chip to obtain the physical coordinates, while calling the centroid coordinates of all identified failure clusters. For any chip, calculate the Euclidean distance between its physical coordinates and the centroid coordinates of each identified failure cluster.

[0049] For each failure mode associated with a failure cluster, a quantitative severity weight is assigned. This weight is dynamically set based on the severity of the root cause analysis. According to the wafer ID, a secondary query is initiated to the database to retrieve the process capability index values of the key process parameters associated with the specific process step within the time window in which the wafer was processed; a pre-set nonlinear mapping function is used to achieve an inverse exponential decay function containing configurable constants, ensuring that as the process capability index value increases, the severity weight will decrease rapidly.

[0050] A spatial impact factor is determined for each failed cluster to control the speed of risk decay with distance. Principal component analysis is performed on all the physical coordinates of the chips within the failed cluster to calculate two orthogonal principal component directions (eigenvectors) and the data variance along these two directions. The standard deviations σ_pc1 and σ_pc2 along the first principal component (PC1) and the second principal component (PC2) directions are calculated, which are equal to the square roots of the corresponding eigenvalues, respectively. The spatial impact factor σ is the root mean square of the two standard deviations. Thus, a failed cluster with a larger size or a more elongated shape will naturally obtain a larger spatial impact factor σ, making its risk assessment coverage wider.

[0051] The Euclidean distance, the severity weight of the associated failure mode, and the spatial impact factor extracted from the failed cluster are input into a weighted summation function combined with a Gaussian decay function to sum up the risk contributions of all the identified failed clusters to the chip. The risk contribution of each failed cluster is determined by the severity weight of the cluster multiplied by a factor that decays exponentially with distance. The decay rate of the decay factor is controlled by the spatial impact factor of the cluster and is inversely proportional to the square of the Euclidean distance from the chip to the cluster centroid. The functional safety risk score is obtained, associated with its unique chip identifier (combined with wafer ID and physical coordinates), and stored in the database of the data analysis center.

[0052] By calculating the Euclidean distance from each chip on the wafer to all the failed cluster centroids and utilizing the severity weight of the associated failure mode and the spatial impact factor, the risk assessment incorporates the analysis of the severity of the failure root cause, enabling accurate identification of chips that have passed the preliminary tests but are highly likely to carry potential defects due to being in a high-risk manufacturing environment, playing a crucial role in meeting the zero-defect requirements in the automotive electronics field.

[0053] Further, the functional safety risk score is compared with a preset risk threshold. When the functional safety risk score is higher than the risk threshold, the composition of the functional safety risk score is analyzed, the most dangerous failed cluster that contributes most to the risk is identified, dynamic task rearrangement instructions are generated and executed to dynamically improve the execution priority of the most sensitive test case of the associated failure mode, and testing is performed. If unqualified is detected, all subsequent testing of the chip is immediately terminated and placed in a high-risk isolated batch. Corresponding to the S5 step; see Figure 4 ; the specific implementation process includes: When a chip enters a final test (FT) station, the functional safety risk score of the chip is queried from the database of the data analysis center through the unique identification of the chip. The queried risk score is compared with a preset risk threshold value which can be configured by an engineer. If the score is higher than the threshold value, the chip is determined as a high-risk chip, and a dynamic task rearrangement logic is triggered to generate a dynamic task rearrangement instruction; if the score is lower than or equal to the threshold value, the chip is determined as a low-risk chip, and a default test sequence is executed.

[0054] The risk threshold value is set by first selecting a plurality of wafer batches with stable yield and high product reliability in history as a reference data set; the functional safety risk scores of all chips in the reference data set are calculated by the method of the application; statistical analysis is performed on the risk scores, for example, the value of the 95th percentile of the risk score distribution plus three times the standard deviation is set as the initial risk threshold value. The threshold value can be dynamically adjusted according to the actual defect detection rate and test cost of the production line.

[0055] For high-risk chips, further analysis of the composition of the risk score is performed to identify one or more failure clusters that contribute most to the risk, and the failure mode labels associated with these failure clusters (such as "edge ring", "scratch type", etc.) are retrieved. A pre-established test failure mode knowledge base is accessed, which is defined by test and process experts in the form of a mapping table, which clearly defines the physical failure mechanisms or their corresponding failure modes that can be effectively detected by each independent test case in the test program library. The mapping table at least includes the following fields: failure mode label (such as edge ring), possible physical root cause (such as timing performance degradation), high sensitivity test case ID list (such as TC_AC_001, TC_AC_005), and optional sensitivity score. The establishment process of the table includes: combining failure mode and impact analysis in the design stage and process failure mode and impact analysis, preliminarily associating failure mode and test item; by analyzing the test data of a specific failure mode batch in history, the test cases with the highest detection rate for the mode are counted and filled into the table, thereby continuously enriching and optimizing the knowledge base.

[0056] The failure mode label is matched with the test failure mode knowledge base to screen all test cases with high detection sensitivity for the specific failure mode. For example, if the traced failure mode is "edge ring", and the mode is associated with the physical root cause of "timing performance decline" caused by photolithography layer misalignment or uneven etching, all test cases related to timing performance, such as "maximum operating frequency test", "setup / hold time test", and other communication parameter tests, are screened in the knowledge base. The execution priority of one or more test cases most sensitive to the associated failure mode screened in the previous step is dynamically promoted to the highest. A new test execution sequence is generated, and the high-priority test cases are placed at the front end of the test queue, and the remaining standard test cases are arranged in the default order.

[0057] The reconstructed dynamic test sequence is sent to the controller of the automatic test equipment, and the automatic test equipment tests the high-risk chip according to the new optimized sequence. In this way, the test most likely to find potential defects is executed first, and when a functional failure is detected during the execution of any test case, all subsequent tests on the chip are immediately terminated, and the chip is classified into a high-risk isolated batch.

[0058] By dynamically promoting the execution priority of the test case most sensitive to the associated failure mode, the test most likely to find potential defects is executed first, the early fault detection rate is improved, and the test is terminated as soon as a failure is found, thereby saving a large amount of test time for the high-risk chip. Secondly, by performing more targeted stress testing on the high-risk area, the coverage depth and quality of the test are improved, and the chip carrying potential defects is effectively prevented from flowing into the market.

[0059] The application can capture the systemic yield loss pattern caused by specific process or equipment problems in real time and accurately by collecting and analyzing the standard test data of the automotive electronic chip and applying the density-based unsupervised clustering algorithm to identify the failure cluster aggregated on the structured data set. More importantly, the application correlates and analyzes the failure mode with the upstream key process steps and equipment logs by querying the manufacturing execution system and equipment automation system through wafer ID, establishes a causal relationship, deeply integrates test data and manufacturing data, realizes the leap from phenomenon correlation to root cause diagnosis, and provides precise clues for process engineers to quickly locate and solve the root problem. On this basis, a quantitative functional safety risk score is calculated for each chip, which not only considers the physical proximity, but also integrates the severity weight determined by the manufacturing root cause, realizing individualized risk assessment. Finally, for the chips with a functional safety risk score higher than the preset risk threshold, the execution priority of the test case most sensitive to the associated failure mode can be dynamically improved for accurate testing. In summary, the application improves the early defect detection rate, shortens the test time and reduces the test cost; through root cause analysis feedback, the overall line yield is improved; and a screening mechanism is provided for automotive electronics to eliminate potential failure risk chips, thereby improving the quality and functional safety level of the product.

[0060] Embodiment Two This embodiment two shows the specific test process of the application method applied in the automotive electronic chip factory, referring to Figure 2 and Figure 3 ; the specific implementation is as follows: For a wafer that has completed CP (Chip Probing) test, the unique identifier (WAFER_ID) is "HNA2025-L0T34A-W21", and a series of chip test result records are extracted from its standard test data. Each record contains the physical coordinates and software bin number of the chip. For example, the following two records are extracted: Chip One: physical coordinates (10, 25), software bin number 1.

[0061] Chip Two: physical coordinates (32, 58), software bin number 101.

[0062] The extracted data tuples are loaded and integrated into a structured database. According to the mapping rules, logical judgment and mapping are performed on the extracted software bin numbers. Software bin number 1 is defined as pass and mapped to binary state 0. Software bin number 101 (for example, representing high leakage current failure) and all other software bin numbers that are not "1" are defined as failure and mapped to binary state 1. A two-dimensional matrix is created according to the physical size of the wafer. Then, all chip data of the wafer are traversed, and the binary state of each chip is filled into the position corresponding to its physical coordinates in the matrix. The value 0 is filled in the (10, 25) position of the matrix, and the value 1 is filled in the (32, 58) position of the matrix.

[0063] This process is repeated for all chips on the wafer "HNA2025-L0T34A-W21", and a complete, digitized structured data set is finally generated.

[0064] The DBSCAN algorithm is selected, and according to the physical size of the tested chip and process experience, the neighborhood radius is set to 2 to 4 times the diagonal length of the chip, and in this embodiment, it is 2.5 times. The minimum number of points is set to an integer range of 3 to 10, and in this embodiment, it is 5. The algorithm traverses each failure chip point in the structured data set, such as point P (32, 58), and according to the density of failure points in its neighborhood, it is automatically divided into three categories: core point, boundary point and noise point.

[0065] Then the algorithm starts with an arbitrarily selected core point that has not been visited from the structured data set, creates a new cluster (for example, Cluster 1), and recursively or iteratively assigns all core points and associated boundary points connected by a series of core point neighborhoods to the same cluster. When a cluster cannot be expanded any further, the algorithm selects the next unvisited core point and repeats the above process until all core points are assigned to a cluster.

[0066] After the algorithm is executed, a labeled data set is output. The data set adds a classification label, i.e. a unique cluster ID or a noise label, to each failure chip point based on the original structured data set. For example: (WAFER ID: HNA2025-L0T34A-W21, X: 32, Y: 58, Fail: 1, Cluster ID: 1) (WAFER ID: HNA2025-L0T34A-W21, X: 32, Y: 59, Fail: 1, Cluster ID: 1) (WAFER ID: HNA2025-L0T34A-W21, X: 15, Y: 40, Fail: 1, Cluster ID: -1).

[0067] For each failed cluster, a set of feature vectors quantifying its physical morphology and distribution characteristics are automatically calculated and extracted. For example, for Cluster ID: 1: Size: the total number of failed dies is calculated to be 157. Centroid: the geometric center is calculated to be (32.8, 85.1). Relative Position: according to the distance between the centroid and the wafer center, the position is classified as "Center". Shape Feature: applying Principal Component Analysis (PCA) to the 157 coordinate points within the cluster, the elongation is calculated to be 1.1, indicating that the cluster shape is close to a circle.

[0068] The generated feature vectors for each failed cluster (e.g., [157, Center, 1.1,...]) are input into a pre-trained Support Vector Machine in the data analysis center, and a standardized failure mode label is output. For example: Cluster ID: 1 is classified as "Center Cluster". Cluster ID: 2 is classified as "Edge Ring". With the wafer's unique identifier "HNA2025-L0T34A-W21" and the test completion timestamp as the key index, a query request is initiated to the upstream manufacturing execution system and equipment automation system to retrieve the complete manufacturing history of the wafer, obtaining a large amount of process and equipment data related to the wafer. For example, it is found that the wafer was processed by the plasma etching machine with equipment number "ETCH_Tool_08" at "14:32:05", using the process recipe "Recipe_Poly_Etch_v2.3". Using the above equipment number and timestamp, the high-frequency process parameter log containing thousands of data points collected by "ETCH_Tool_08" during processing of the wafer is retrieved from the equipment automation system database, and the retrieved EAP parameter data is compared with the control limit preset in the process recipe "Recipe_Poly_Etch_v2.3", detecting that the radio frequency power (RF_Power) has an abnormal decrease of 4%. Then, the failure root cause knowledge base is queried, and a rule is matched: "Edge Ring" failure mode is highly correlated with "plasma etching uniformity problem", and the typical cause is "RF power fluctuation", and a causal relationship is established accordingly.

[0069] The attribute data of all failed clusters generated for the wafer is retrieved. For example, there are two failed clusters on the wafer: Failed Cluster 1: Cluster ID: 1, Failure Mode: "Center Cluster", Centroid: (32.8, 85.1), Severity Weight (SW): 0.8, Spatial Impact Factor (SIF): 0.5. Failed Cluster 2: Cluster ID: 2, Failure Mode: "Edge Ring", Centroid: (15, 40), Severity Weight (SW): 0.2, Spatial Impact Factor (SIF): 0.8. ): 15.0.

[0070] Failure Cluster 2: Cluster_ID: 2, Failure Pattern: "Edge-Ring", Centroid Coordinate: (85.0, 15.2), Severity Weight ( ): 0.5, Spatial Impact Factor ( ): 25.0.

[0071] Traverse all failure clusters, calculate the Euclidean distance between the target chip (45, 62) and the centroid of each failure cluster. The distance to failure cluster 1 is , and the distance to failure cluster 2 is .

[0072] For each failure cluster, calculate its risk contribution to the target chip according to its severity weight, spatial impact factor, and distance to the target chip. The calculation process is as follows: multiply the severity weight by a factor that decays exponentially as the distance increases, and the decay rate of this decay factor is controlled by the spatial impact factor, and is inversely proportional to the square of the Euclidean distance from the chip to the centroid of the cluster.

[0073] The risk contribution of failure cluster 1 = 0.8 × exp[- (26.12 2 / (2 × 15 2 ))]= 0.8 × exp(-1.516) = 0.176, The risk contribution of failure cluster 2 = 0.5 × exp(-3.032) = 0.024, Sum up the risk contributions of all failure clusters to the target chip to get the final functional safety risk score of the chip = 0.176 + 0.024 = 0.200 After the calculation is completed, a record containing the unique identifier of the chip and its corresponding risk score is output. For example: {Chip_UID: HNA2025-L0T34A-W21_45_62, Risk_Score: 0.200}, this record is stored in the database of the data analysis center and is associated with other information of the chip.

[0074] When the chip enters the final test (FT) station, the test system controller queries the functional safety risk score from the database of the data analysis center. Get {Chip_UID: HNA2025-L0T34A-W21_45_62, Risk_Score: 0.200}. Compare the queried risk score 0.200 with a preset, engineer-configurable risk threshold (for example, 0.150). Since 0.200 > 0.150, the chip is determined to be a high-risk chip, and the dynamic task rearrangement logic is triggered to generate dynamic task rearrangement instructions.

[0075] Further analysis of the risk score composition of this chip identifies the failure cluster that contributes most to its risk as failure cluster 2, and retrieves from the database the associated, classified failure mode label for this cluster: "Edge Ring". The database is accessed. The associated physical root cause "timing performance degradation" is obtained, matched against the database, and all test cases with high detection sensitivity for this specific failure mode are filtered out. For example, from a test program containing thousands of test cases, the following high sensitivity test cases are filtered out: TC_AC_001 : Fmax_Test @ VDD_nom, Temp_hot TC_AC_005 : Setup_Time_Test_Core_A @ VDD_min, Temp_cold TC_AC_006 : Hold_Time_Test_Core_A @ VDD_max, Temp_hot TC_AC_012 : Fmax_Test_DDR_Interface @ VDD_nom, Temp_hot The execution priority of the filtered, most targeted test cases (TC_AC_001, TC_AC_005, TC_AC_006, TC_AC_012) is dynamically boosted to the highest. A new test execution sequence is generated, placing these high priority test cases at the very front of the test queue, while the rest of the standard test cases are arranged in their default order at the back. The reconfigured dynamic test sequence is issued to the controller of the automated test equipment, which then proceeds to test the high risk chip according to this new, optimized order. The chip fails while executing TC_AC_005, and the remaining thousands of test cases are not executed. The final results of the test, including pass / fail status, specific failed test item (e.g. TC_AC_005), and detailed parameter measurements, are recorded. These data are fed back to the data analysis center through the real-time monitoring system, for subsequent yield analysis and continuous optimization of the scheduling method model.

[0076] While embodiments of the present application have been shown and described, it is to be understood that various modifications, substitutions, combinations, and variations can be made by those skilled in the art without departing from the spirit and scope of the present application, which is defined by the appended claims and their equivalents.

Claims

1. A method for dynamic priority scheduling of test cases for automotive electronic chip, characterized in that, The application comprises: Collecting and analyzing standard test data of automotive electronic chips; extracting a structured data set including wafer ID, physical coordinates of each chip, and software bin number; Applying data clustering algorithm to identify aggregated failure clusters; Extracting geometric and positional features of the failure clusters, and using a classifier to classify them into known failure modes; Through wafer ID query of manufacturing execution system and equipment automation system, correlating and analyzing the failure modes with process steps and equipment logs, and matching them with failure root cause knowledge base to establish causal relationship; Analyzing historical test results, calculating the frequency of failure modes, and performing statistical significance test with failure rate of production line baseline to obtain diagnostic confidence score, and storing the diagnostic confidence score and causal relationship in the failure root cause knowledge base; For each chip, calculating the Euclidean distance between the physical coordinates and the centroid of all failure clusters; Combining the severity weight of the failure mode associated with the failure cluster and the spatial influence factor obtained by principal component analysis of the physical coordinates of the chips in the failure cluster to quantify the risk coverage range of the failure cluster, and obtaining the functional safety risk score through the weighted summation function of Gaussian decay; Comparing the functional safety risk score with the preset risk threshold, when the functional safety risk score is higher than the risk threshold, analyzing the composition of the functional safety risk score, identifying the most dangerous failure cluster with the largest risk contribution, generating and executing dynamic task rearrangement instructions, dynamically improving the execution priority of the most sensitive test cases of the associated failure mode, and testing; detecting unqualified, immediately terminate all subsequent tests on the chip, and enter the high-risk isolation batch.

2. The test case dynamic priority scheduling method for automotive electronic chip according to claim 1, wherein, The specific generation process of the structured data set comprises: collecting and analyzing standard test data of automotive electronic chips, extracting wafer ID, physical coordinates of chips on the wafer, and software bin number, and forming key data tuples; according to the preset mapping rule, data conversion is performed on the software bin number, and the test result is mapped to binary data label; a two-dimensional matrix is created according to the physical size of the wafer; all chip data of the wafer are traversed, and the binary data label of each chip is filled into the position corresponding to the physical coordinates in the matrix to form a structured data set.

3. The method of claim 1, wherein, The specific process of identifying the aggregated failure clusters comprises: selecting a density-based unsupervised clustering algorithm, setting the neighborhood radius and minimum point number according to the physical size of the chip and process experience, and taking the physical coordinates of all failed chips in the structured data set as input point set; traversing each failed chip, according to the density of failed chips within the neighborhood radius, dividing into three categories: core point: the number of contained failed chips is not less than the preset minimum point number; boundary point: the number of contained failed chips is less than the minimum point number, but within the neighborhood radius of the core point; noise point: neither core point nor boundary point; starting from the core point that has not been visited, creating a new failure cluster, and through recursion, all connectable core points and their associated boundary points are assigned to the same failure cluster.

4. The method of claim 1, wherein, The specific process of using the classifier to classify into a known failure mode includes: calculating and extracting a set of geometric and positional features from the failure cluster; inputting the geometric and positional features into a pre-trained classifier, and outputting a failure mode label from a predefined library of automotive chip labels; the geometric and positional features include cluster size, cluster density, centroid coordinates, relative position, and elongation obtained by principal component analysis.

5. The method of claim 1, wherein, The specific generation process of establishing a causal relationship includes: when a failure cluster is assigned a failure mode label, triggering a concurrent query to a manufacturing execution system and a device automation system through a wafer ID; retrieving full-life-cycle manufacturing data associated with the wafer ID from the manufacturing execution system database; retrieving process parameter logs within a time window of processing the wafer from the device automation system database according to the full-life-cycle manufacturing data; comparing the process parameter logs with preset control limits to detect out-of-specification conditions, and matching with a preset failure root cause knowledge base when a process parameter anomaly is detected; establishing a causal relationship with process steps and device logs.

6. The method of claim 1, wherein, The specific generation process of the functional safety risk score includes: traversing each chip on the wafer to obtain the centroid coordinates of all failure clusters; for any chip, calculating the Euclidean distance between the physical coordinates and the centroid coordinates of each failure cluster; according to the failure mode associated with each failure cluster, assigning a quantified severity weight; performing principal component analysis on the physical coordinates of all chips in the failure cluster to determine a spatial influence factor; inputting the Euclidean distance, severity weight, and spatial influence factor into a weighted summation function combined with Gaussian decay to calculate the functional safety risk score; associating the functional safety risk score with the chip identifier combined with the wafer ID and physical coordinates, and storing it in the database.

7. The method of claim 1, wherein the method further comprises: The specific process of dynamically promoting the execution priority of the test case most sensitive to the associated failure mode includes: using the chip identifier as a database query key to query the functional safety risk score from the database and compare it with a preset risk threshold; if the functional safety risk score is higher than the risk threshold, the chip is determined to be high-risk, and a dynamic task rearrangement instruction is generated and executed to dynamically promote the execution priority of the test case most sensitive to the associated failure mode; reordering the data structure of the original task queue to generate a new task queue, and placing the test case with high priority at the front of the task queue; when a defect is detected, all subsequent tests on the chip are immediately terminated and are classified into a high-risk isolation batch.

8. The method of claim 7, wherein, The specific process of generating and executing a dynamic task rearrangement instruction includes: when the chip is determined to be high-risk, analyzing the composition of the functional safety risk score, identifying the dangerous failure cluster that contributes most to the risk, and retrieving the failure mode label associated with the dangerous failure cluster; filtering out the test case with high detection sensitivity to the failure mode label through a pre-set database storing the mapping relationship between test cases and failure modes, and dynamically promoting the execution priority of the test case to the highest.

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