Write-in method of flash memory and flash memory device

Abstract

The invention provides a writing method of a flash memory and a flash memory device. The writing method of the flash memory comprises the following steps: dividing a plurality of blocks of the flash memory into a plurality of block groups according to the deletion times of the blocks; then, a data address range of a host is divided into a plurality of address sections, and the address sections respectively correspond to one of the block groups; after a write-in data is received from the host, a target address segment corresponding to a logical address of the write-in data is determined from the address segments. Then, a target block group corresponding to the target address segment is determined from the block groups, and a target block is selected from the blocks contained in the target block group. And finally, writing the write-in data into the target block, and when the blocks of the flash memory are subjected to wear averaging, only the blocks contained in the block groups are subjected to wear averaging respectively.

Description

TECHNICAL FIELD

[0001] The present invention relates to a memory device, and more particularly, to a flash memory device. BACKGROUND

[0002] A flash memory includes a plurality of blocks for storing data. Each block has a different number of uses. The number of times a block is written and erased is referred to as the program / erase count, and a controller of the flash memory has a table of erase counts to record the erase counts of the blocks of the flash memory. The number of times a block is read is referred to as the read count. Each block has a different program / erase count and read count. The program / erase count and the read count reflect the usage of each block of the flash memory. The more frequently a block is used, the higher the program / erase count and the read count of the block.

[0003] When a block stores some data that is used more frequently, the block has a higher program / erase count and a higher read count, and is more likely to be damaged. A damaged block can have a situation where it cannot store data or has a high bit error rate. Figure 2A A graph of the relationship between the program / erase count and the bit error rate of a block of a flash memory. As seen in the graph, a block with a higher program / erase count also has a higher bit error rate. Figure 2B A graph of the relationship between the read count and the bit error rate of a block of a flash memory. As seen in the graph, a block with a higher read count also has a higher bit error rate. Figure 2C A graph of the relationship between the program / erase count and the data retention period of a block of a flash memory. As seen in the graph, a block with a higher program / erase count has a lower data retention period, and a block with a lower program / erase count has a higher data retention period.

[0004] In order to avoid a single block from being damaged too early due to a too high program / erase count, a controller of a flash memory generally implements wear-leveling to evenly use the blocks of the flash memory so that the blocks have an average program / erase count. Figure 1 A graph of the distribution of the program / erase counts of the blocks of a flash memory of the prior art. Each block of the flash memory has a different physical location. After the controller implements wear-leveling, each block of different physical locations has the same program / erase count in an ideal situation. This avoids a situation where some blocks are used too much and are damaged too early.

[0005] However, the data stored in the flash memory also has different data importance. For example, system data has higher data importance, and user data has lower data importance. The system data is, for example, partition table data and root directory data. When the controller performs wear leveling without considering data importance, it is easy to cause data with high importance to be stored in blocks with high write / delete frequencies. Since the data error rate of blocks with high write / delete frequencies is large, if the high importance data stored therein is damaged, it will cause problems in the operation of the system. For example, when the partition table data is erroneous, the data in the entire flash memory cannot be read. When the root directory data is erroneous, the data stored in the erroneous directory cannot be read. Therefore, a flash memory write method is needed to avoid such a situation. SUMMARY

[0006] The present application provides a flash memory write method to solve the problems of the known art. First, a plurality of blocks of a flash memory are divided into a plurality of block groups according to the number of deletions of the blocks. Next, a data address range of a host is divided into a plurality of address sections, wherein the address sections correspond to one of the block groups respectively. Next, a write data is received from the host. Next, a target address section corresponding to a logical address of the write data is determined from the address sections. Next, a target block group corresponding to the target address section is determined from the block groups. Next, a target block is selected from the blocks included in the target block group. Finally, the write data is written to the target block.

[0007] The present application also provides a flash memory device. In one embodiment, the flash memory device is coupled to a host, and includes a flash memory and a controller. The flash memory includes a plurality of blocks, and the blocks are divided into a plurality of block groups according to the number of deletions of the blocks. The controller receives a write data from the host, determines the data importance of the write data, selects a target block group from the block groups according to the data importance of the write data, selects a target block from the blocks included in the target block group, and writes the write data to the target block.

[0008] The present application also provides a flash memory device. In one embodiment, the flash memory device is coupled to a host and includes a flash memory and a controller. The flash memory includes a plurality of block groups, each of which includes a plurality of blocks, the block groups include blocks having different ranges of deletion counts, and the block groups correspond to different address sections of a data address range of the host. The controller receives a write data from the host, determines a target address section corresponding to a logical address of the write data from the address sections, determines a target block group corresponding to the target address section from the block groups, selects a target block from blocks included in the target block group, and writes the write data into the target block.

[0009] The present application is described in detail below with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 Distribution of write / delete counts of blocks of a flash memory of the prior art;

[0011] Figure 2A Relationship between write / delete counts of blocks of a flash memory and data error rate;

[0012] Figure 2B Relationship between read counts of blocks of a flash memory and data error rate;

[0013] Figure 2C Relationship between write / delete counts of blocks of a flash memory and data retention period;

[0014] Figure 3 Distribution of logical addresses of a host using a flash memory to store data according to the present application;

[0015] Figure 4 Block diagram of a flash memory device according to the present application;

[0016] Figure 5 Correspondence between logical block addresses and deletion counts of a flash memory according to the present application;

[0017] Figure 6 Flowchart of a write method of a flash memory according to the present application.

[0018] REFERENCE NUMERALS:

[0019] 301 partition table;

[0020] 302 BIOS parameter area;

[0021] 303, 304 file allocation table;

[0022] 305 root directory;

[0023] 306 user data;

[0024] 450 host;

[0025] 400 flash memory device;

[0026] 402 controller;

[0027] 406 erase count table;

[0028] 404 flash memory;

[0029] 410 first block group;

[0030] 420 second block group;

[0031] 430 third block group;

[0032] 411-41x, 421-42y, 431-43z ~ blocks. DETAILED DESCRIPTION

[0033] The following description sets forth numerous specific details to provide a thorough understanding of the application. The following description includes

[0034] Figure 4 A block diagram of a flash memory device 400 according to the present application. The flash memory device 400 is coupled to a host 450. In one embodiment, the flash memory device 400 includes a controller 402 and a flash memory 404. The flash memory 404 includes a plurality of blocks for storing data. Each block has an erase count to record the number of times the data in the block has been erased by the controller 402. The controller 402 includes an erase count table 406 to record the erase count of each block. All blocks in the flash memory 404 are divided into a plurality of block groups by the controller 402 according to the erase count. Each block group includes a plurality of blocks, and the number of blocks in each block group is not necessarily the same.

[0035] When the controller 402 receives a write data from the host 450, the controller 402 has to write the write data into the flash memory 404. At this time, the controller 402 first determines the data importance of the write data, and then selects a target block group from the block groups of the flash memory 404 according to the data importance of the write data. Next, the controller 402 selects a target block from the blocks included in the target block group, and writes the write data into the target block. In an embodiment, the blocks in the flash memory 404 are divided into two block groups with high and low deletion frequencies. When the controller 402 determines that the write data is system data with high data importance, in order to ensure the data correctness of the system data, the block group with low deletion frequency is selected as the target block group for storing the system data. When the controller 402 determines that the write data is user data with low data importance, since the user data can tolerate a higher data error rate, the block group with high deletion frequency is selected as the target block group for storing the user data.

[0036] In an embodiment, the controller 402 determines the data importance of the write data according to the logical address of the write data. Figure 3 A diagram showing the logical address distribution of the data stored in the flash memory according to the host of the present application. The data stored in the flash memory 404 by the host 450 includes a master boot record or a partition table 301, a BIOS parameter block 302, file allocation tables 303 and 304, a root directory 305, and user data 306. The master boot record 301 is stored at the beginning of the logical address, and then the BIOS parameter block 302, the file allocation table 1 303, the file allocation table 2 304, the root directory 305, and the user data 306 are stored in sequence, and the importance of each data decreases with the increase of the logical address.

[0037] In one embodiment, the host 450 uses the address range of the flash memory 404 to be divided into three address segments. The first address segment is used to store the master boot record 301 and the BIOS parameter block 302, between logical address 0 and logical address P. The second address segment is used to store the file allocation table 303, 304 and the root directory 305, between logical address P and logical address Q. The third address segment is used to store user data, after logical address Q. For example, in a FAT16 file system, the value of P can be 63-8192, and Q is equal to P+210. For example, in a FAT32 file system, the value of P can be 63-8192, and Q is equal to P+221. The data in the first address segment has the highest importance, the data in the second address segment has the middle importance, and the data in the third address segment has the lowest importance. Therefore, the controller 402 can determine the importance of the data to be written according to the logical address of the data to be written, and find the corresponding block group from the flash memory 404 to store the data to be written. For example, the blocks in the flash memory 404 are divided into a first block group 410 with low number of erasures, a second block group 420 with middle number of erasures, and a third block group 430 with high number of erasures. The controller 402 stores the data to be written in the first address segment with high importance in the blocks of the first block group 410, and stores the data to be written in the second address segment with middle importance in the blocks of the second block group 420, to ensure the correctness of the data. The controller 402 also stores the data to be written in the third address segment with low importance in the blocks of the third block group 430. Since the lengths of the first address segment, the second address segment, and the third address segment are not equal, the number of blocks contained in the corresponding first block group 410, the second block group 420, and the third block group 430 are also not equal.

[0038] Figure 5Fig. 4 is a diagram showing the correspondence between the logical block addresses and the number of erasures of the flash memory according to the present application. The logical address section 0-P corresponds to data of high importance, and thus the blocks storing the logical address section 0-P are the blocks belonging to the first block group 410 and have the lowest number of erasures S. The logical address section P-Q corresponds to data of medium importance, and thus the blocks storing the logical address section P-Q are the blocks belonging to the second block group 420 and have the medium number of erasures T. The logical address section above the logical address Q corresponds to data of low importance, and thus the blocks storing this logical address section are the blocks belonging to the third block group 430 and have the highest number of erasures U. The preferable ratio of the numbers of erasures S, T and U is 1:10:100, for example, when S is 50, T should be 500, and U should be 5000 for the best. In an embodiment, the numbers of erasures of the blocks of the first block group 410, the second block group 420 and the third block group 430 each have different ranges of the number of erasures. When the number of erasures of a particular block included in one of the block groups 410, 420, 430 exceeds the range of the number of erasures of the corresponding block group, the controller 402 will move the particular block to the other block group corresponding to the number of erasures of the particular block. In addition, in order to maintain the independence of each block group, in an embodiment, the controller performs wear leveling only on the blocks included in each of the block groups 410, 420, 430, respectively. For example, the controller 410 performs wear leveling on the blocks 411-41x alone, on the blocks 421-42y alone, and on the blocks 431-43z alone.

[0039] Figure 6A flowchart of the write method 600 for the flash memory according to the present application is shown in FIG. 6. First, the controller 402 divides all blocks in the flash memory 404 into a plurality of block groups 410, 420, 430 according to the number of erasures of the blocks (step 602). Next, the controller 402 divides the logical addresses of the data into a plurality of address sections (step 604), wherein each address section corresponds to one of the block groups 410, 420, 430 according to the importance of the data. In one embodiment, the address sections with higher importance of data correspond to the block groups with lower number of erasures, and the address sections with lower importance of data correspond to the block groups with higher number of erasures. Next, the controller 402 receives a write data from the host 450 (step 606). Next, the controller 402 determines a target block group from the block groups 410, 420, 430 according to the address section corresponding to the write data (step 608). Next, the controller 402 selects a target block from the target block group (step 610), and stores the write data in the target block (step 612). Finally, if the host 450 sends new write data (step 612), the controller 402 repeats steps 606-612 to select a target block group for storing the new write data. In this way, the controller 402 can store the write data in the blocks with corresponding number of erasures according to the importance of the data, so as to ensure the data correctness when storing important data.

[0040] Although the present application has been disclosed in its preferred embodiments with reference to the drawings, it will be understood that it is not limited to the above-disclosed embodiments, but is intended to cover any modifications or variations thereof within the spirit and scope of the present application as defined by the appended claims.

Claims

1. A method for writing to a flash memory, comprising the steps of: dividing a plurality of blocks of a flash memory into a plurality of block groups according to a number of erasures of the blocks; dividing a data address range of a host into a plurality of address sections, wherein the address sections respectively correspond to one of the block groups; receiving a write data from the host; deciding a target address section corresponding to a logical address of the write data from the address sections; deciding a target block group corresponding to the target address section from the block groups; selecting a target block from a block included in the target block group; and writing the write data to the target block, wherein when performing wear-leveling to the blocks of the flash memory, wear-leveling is performed only to the blocks respectively included in the block groups. wherein the address sections are ordered according to data importance, the address sections having higher data importance correspond to the block groups having lower number of erasures, and the address sections having lower data importance correspond to the block groups having higher number of erasures.

2. The write method of flash memory according to claim 1, wherein, wherein the address sections include a first address section for storing a system data and a second address section for storing a user data.

3. The method of claim 1, wherein the write operation is performed on a flash memory. wherein the block groups include a first block group having lower number of erasures and a second block group having higher number of erasures, the first address section corresponds to the first block group, and the second address section corresponds to the second block group.

4. The write method of flash memory according to claim 3, wherein, wherein the address sections include a first address section for storing a master boot record and a BIOS parameter block, a second address section for storing a file allocation table and a root directory, and a third address section for storing a user data.

5. The method of claim 1, wherein the write operation is performed on the flash memory. wherein the block groups include a first block group having lowest number of erasures, a second block group having middle number of erasures, and a third block group having highest number of erasures, the first address section corresponds to the first block group, the second address section corresponds to the second block group, and the third address section corresponds to the third block group.

6. The write method of flash memory as claimed in claim 5, wherein, wherein the block groups respectively include blocks having different ranges of number of erasures, and the method further comprises the steps of:

7. The method of claim 1, wherein the write operation is performed on a flash memory. when a number of erasures of a particular block included in a particular block group of the block groups exceeds a range of number of erasures corresponding to the particular block group, moving the particular block from the particular block group to another block group corresponding to the number of erasures of the particular block.

8. A flash memory device coupled to a host, comprising: a flash memory including a plurality of blocks, the blocks being divided into a plurality of block groups according to a number of erasures of the blocks; and a controller coupled to the flash memory and the host, wherein the controller is configured to: ​ A controller receives a write data from the host, determines data importance of the write data, selects a target block group from the block groups according to the data importance of the write data, selects a target block from blocks included in the target block group, and writes the write data into the target block.

9. The flash memory device of claim 8, wherein, The controller distinguishes the write data as a system data having high data importance or a user data having low data importance, selects a block group having a low number of deletions as the target block group from the block groups when the write data is the system data, and selects a block group having a high number of deletions as the target block group from the block groups when the write data is the user data.

10. The flash memory device of claim 8, wherein, The controller distinguishes the write data as a partition table and BIOS parameter block data having high data importance, a file allocation table and root directory data having medium data importance, or a user data having low data importance, selects a block group having a low number of deletions as the target block group from the block groups when the write data is the partition table and BIOS parameter block data, selects a block group having a medium number of deletions as the target block group from the block groups when the write data is the file allocation table and root directory data, and selects a block group having a high number of deletions as the target block group from the block groups when the write data is the user data.

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