Adaptive device and method compatible with different MCIO connector Pin definitions

Abstract

The invention relates to an adaptation device and method compatible with different MCIO connector Pin definitions. The device comprises a first MCIO port, a second MCIO port, a first interface and a second interface, the main board clock generator is arranged on the main board and is connected with the first MCIO port; a second MCIO port, wherein the first MCIO port is connected with the second MCIO port through a standard MCIO cable; the back plate processor is arranged on the back plate of the server, and the back plate processor is connected with the second MCIO port; the backboard clock expander is used for expanding a clock port, and the backboard clock expander is arranged on a backboard of the server; and the module connecting port is used for connecting a downstream module, the module connecting port is arranged on a backboard of the server, and the second MCIO port and the backboard clock expander are respectively connected with the module connecting port. On the premise that a standard MCIO cable is used in the hard disk backboard, different MCIO connector Pin definitions of OCSP and MGX are compatible.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of servers, and particularly relates to an adapter device and method compatible with different MCIO connector pin definitions. BACKGROUND

[0002] With the gradual development of modular servers, the server whole machine is decoupled into CPU mainboards, power backboards, fan backboards, hard disk backboards and different modules, reduces the interdependence between different modules, and provides convenience for independent replacement and maintenance of each module. In order to further realize the complete compatibility and replacement of each module, two major server design specifications, Intel OCSP and Nvidia MGX, appear in the server industry. The specifications not only make requirements for system architecture, whole machine size and the like, but also make strict constraints on the interface definition involved in the interconnection of different modules.

[0003] Taking the interconnection between the CPU mainboard and the hard disk backboard as an example, the MCIO connector definition is one of them. However, since the two specifications are not the same in the definition of the MCIO connector, even if there are two hard disk backboards meeting different specifications, in the case of completely consistent structure and size, they cannot be compatible in function.

[0004] The prior art usually designs two different hard disk backboards for the two specifications respectively and adapts them. However, the following disadvantages exist: 1) Re-design and production are needed, resulting in increased overall cost and increased research and development period.

[0005] 2) If other specifications appear subsequently, the number of backboards increases, and the maintenance difficulty becomes greater and greater, and different backboards are easily confused.

[0006] 3) Changing the standard MCIO cable pin definition means that each length of MCIO cable needs to be re-customized, which increases the cost and is more prone to errors in the whole machine assembly and later maintenance process. SUMMARY

[0007] The present application provides an adapter device and method compatible with different MCIO connector pin definitions, aiming to at least solve one of the technical problems existing in the prior art.

[0008] The technical scheme of the present application relates to an adapter device compatible with different MCIO connector pin definitions, which is used to adapt to the differences in MCIO connector pin definitions based on the Open Common Server Platform (OCSP) specification and the Modular GPU Acceleration Platform (MGX) specification, The adapter device compatible with different MCIO connector pin definitions is arranged in a server, and the server comprises at least a mainboard and a backboard. a first MCIO port arranged on the mainboard of the server; a mainboard clock generator arranged on the mainboard and connected with the first MCIO port; a second MCIO port arranged on the backboard of the server, and the first MCIO port is connected with the second MCIO port through a standard MCIO cable; a backboard processor arranged on the backboard of the server, and the backboard processor is connected with the second MCIO port; a backboard clock expander for expanding clock ports, and the backboard clock expander is arranged on the backboard of the server; a module connection port for connecting downstream modules, and the module connection port is arranged on the backboard of the server, and the second MCIO port and the backboard clock expander are respectively connected with the module connection port.

[0009] Further, based on the OCSP specification or the MGX specification, an adapter pin connected with the backboard processor is arranged on each of the second MCIO ports, and the adapter pin is used for simultaneously adapting the OCSP specification and the MGX specification, and for each of the second MCIO ports, the adapter pin comprises: an A11 pin, an A12 pin, an A26 pin, an A27 pin, an A29 pin, an A30 pin, a B9 pin, a B26 pin and a B27 pin.

[0010] Further, the adapter pin is connected with the backboard processor, and a port type of the adapter pin is set as bidirectional inout.

[0011] Further, the A11 pin and the A12 pin in the adapter pin are used for the backboard processor to perform logical processing and then output to external circuits.

[0012] Further, at least a central processing unit (CPU), a baseboard management controller (BMC) and a mainboard processor for basic logic control of the mainboard are arranged on the mainboard, and the central processing unit (CPU) and the mainboard processor are respectively connected with the first MCIO port; The backboard comprises at least one or more combinations of a hard disk backboard, a power supply backboard and a fan backboard, and when the backboard is the hard disk backboard, the module connection port is a hard disk connector. The first MCIO port and the second MCIO port are equal in number and at least one, and the corresponding first MCIO port and the second MCIO port are connected through a standard MCIO cable; The backboard processor is a complex programmable logic device (CPLD), a field programmable logic gate array (FPGA) or a microprocessor; The backboard clock expander is used for expanding the input clock signal REFCLK_P / N of at least one MCIO connector, and the backboard clock expander is connected with at least one MCIO input clock signal.

[0013] Further, the backboard further comprises: The project serial number acquisition module is used for indicating that the current connection mode is based on the Open Common Server Platform (OCSP) specification or the Modular GPU Acceleration Platform (MGX) specification, and the project serial number acquisition module is one or a combination of both of the IIC communication acquisition module and the hardware control mode acquisition module.

[0014] Further, after the backboard processor obtains the project serial number ID, it is judged that the current connection mode is based on the OCSP specification or the MGX specification, and the specific pin definition of each adaptive pin is locked, If the corresponding adaptive pin is an input pin, the corresponding function variable of the backboard processor is assigned, and if the adaptive pin is an output pin, the logic variable generated by the backboard processor is output to the pin, and finally output to the target device through the second MCIO port.

[0015] Further, the application also provides an adaptive method compatible with different MCIO connector pin definitions, which is applied to an adaptive device compatible with different MCIO connector pin definitions, the adaptive device compatible with different MCIO connector pin definitions comprises a first MCIO port and a second MCIO port connected through a standard MCIO cable, a central processing unit (CPU) and a mainboard clock generator connected with the first MCIO port, a backboard processor connected with the second MCIO port, a backboard clock expander and a module connection port, and the adaptive method compatible with different MCIO connector pin definitions comprises the following steps: S100, the backboard processor obtains a project serial number ID after power on, determines the current connection based on an Open Common Server Platform (OCSP) specification or a Modular GPU Acceleration Platform (MGX) specification through the project serial number ID; S200, if the current connection is based on the Open Common Server Platform (OCSP) specification, the adaptation pins are defined as PERST0#, PRSNT0#, PERST1#, PRSNT1#, HP_SMB_CLK, HP_SMB_DAT, N / C, N / C and HP_SMB_ALERT# in sequence; S300, if the current connection is based on the Modular GPU Acceleration Platform (MGX) specification, the adaptation pins are defined as PERST0#, PRSNT0#, N / C, N / C, N / C, N / C, HP_SMB_ALERT#, HP_SMB_DAT and HP_SMB_CLK in sequence; S400, when the adaptation pin is an input pin, the pin level value is assigned to the corresponding function module, and when the adaptation pin is an output pin, the pin level value is output to the external circuit in the form of backboard processor control.

[0016] Further, step S100 comprises: S110, when the project serial number acquisition module is based on an IIC communication acquisition module, the backboard processor communicates with a management controller BMC arranged on the mainboard through an IIC protocol, and the management controller BMC writes the current project serial number ID into the register of the IIC Slave module of the backboard processor through the IIC protocol; S120, when the project serial number acquisition module is based on a hardware control mode acquisition module, the backboard processor obtains the current project serial number ID by querying the level signal of a jumper cap or a dial switch arranged on the mainboard or the backboard; S130, when the project serial number acquisition module comprises an IIC communication acquisition module and a hardware control mode acquisition module, the backboard processor outputs the final project serial number ID by performing bitwise AND operation on the two obtained project serial number IDs.

[0017] Further, the application further provides a computer readable storage medium, which has program instructions stored thereon, and the program instructions are executed by a processor to implement the adaptation method compatible with different MCIO connector pin definitions.

[0018] Compared with the prior art, the present application has the following characteristics: The application provides an adapter and a method for adapting different MCIO connector pin definitions. Under the premise of using a standard MCIO cable for a hard disk backboard, the adapter is compatible with different MCIO connector pin definitions of OCSP and MGX, has good compatibility with new MCIO definitions that may appear later, and finally achieves the purpose of adapting OCSP, MGX and other models by one backboard. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 Structure diagram of the adapter for adapting different MCIO connector pin definitions.

[0020] Figure 2 Diagram of pin definitions of MCIO under the compatibility of OCSP and MGX.

[0021] Figure 3 Structure diagram of one embodiment of the adapter for adapting different MCIO connector pin definitions.

[0022] Figure 4 Structure diagram of a hard disk backboard having multiple MCIO connectors, and each Sideband of the MCIOs needs to be connected to a CPLD.

[0023] Figure 5 Structure diagram of a backboard clock expander that expands multiple hard disk connectors and connects only one input.

[0024] Figure 6 Diagram of one embodiment of a module for obtaining a serial number based on IIC communication.

[0025] Figure 7 Flowchart of the method for adapting different MCIO connector pin definitions.

[0026] Figure 8 Flowchart of one embodiment of the method for adapting different MCIO connector pin definitions. DETAILED DESCRIPTION

[0027] To make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described in detail below with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0028] The concept, specific structure and generated technical effects of the present application will be described clearly and completely in combination with the embodiments and the drawings below, so as to fully understand the purpose, scheme and effect of the present application.

[0029] It should be noted that, unless otherwise specified, when a certain feature is referred to as being "fixed" or "connected" to another feature, it can be directly fixed or connected to the other feature, or indirectly fixed or connected to the other feature. The singular forms "a", "said" and "the" used herein are also intended to include the plural forms, unless the context clearly indicates otherwise. In addition, unless otherwise defined, all technical and scientific terms used herein have the same meaning as understood by those skilled in the art. The terms used in the specification herein are only for the purpose of describing specific embodiments and are not intended to limit the present application. The term "and / or" used herein includes any combination of one or more related listed items.

[0030] It should be understood that although the terms first, second, third, etc. are used to describe various elements in the present disclosure, these elements should not be limited to these terms. These terms are only used to distinguish elements of the same type from each other. For example, without departing from the scope of the present disclosure, the first element can also be referred to as the second element, and similarly, the second element can also be referred to as the first element. The use of any and all examples or exemplary language provided herein (e.g., "for example", "for instance", etc.) is intended merely to better illustrate the embodiments of the present application and should not impose a limitation on the scope of the present application unless otherwise required. In addition, the industry term "pose" used herein refers to the position and attitude of a certain element relative to a spatial coordinate system.

[0031] Referring to Figures 1 to 8 The embodiments of the present application provide an adaptation device compatible with different MCIO connector pin definitions, which is used to be compatible with different MCIO connector pin definitions based on the Open Common Server Platform (OCSP) specification and the Modular GPU Acceleration Platform (MGX) specification, The adaptation device compatible with different MCIO connector pin definitions is arranged in a server, and the server at least includes a mainboard and a backboard. The adaptation device compatible with different MCIO connector pin definitions includes: A first MCIO port, which is arranged on the mainboard of the server; A mainboard clock generator, which is arranged on the mainboard and connected with the first MCIO port; a second MCIO port, the second MCIO port being disposed on a backplane of the server, the first MCIO port being connected to the second MCIO port through a standard MCIO cable; a backplane processor, the backplane processor being disposed on the backplane of the server, the backplane processor being connected to the second MCIO port; a backplane clock expander, for expanding a clock port, the backplane clock expander being disposed on the backplane of the server; a module connection port, for connecting a downstream module, the module connection port being disposed on the backplane of the server, the second MCIO port and the backplane clock expander being connected to the module connection port respectively.

[0032] Compared with the prior art, the application has the following characteristics: The application provides an adaptation device and method compatible with different MCIO connector Pin definitions, which are compatible with different MCIO connector Pin definitions of OCSP and MGX under the premise of using a standard MCIO cable on a hard disk backplane, have good compatibility for new MCIO definitions that may appear subsequently, and finally achieve the purpose of adapting OCSP, MGX and other models by one backplane.

[0033] Further, based on the OCSP specification or the MGX specification, an adaptation pin connected to the backplane processor is disposed on each second MCIO port, the adaptation pin being used for adapting the OCSP specification and the MGX specification simultaneously, and for each second MCIO port, the adaptation pin comprises: an A11 pin, an A12 pin, an A26 pin, an A27 pin, an A29 pin, an A30 pin, a B9 pin, a B26 pin and a B27 pin.

[0034] Specifically, when drawing a hard disk backplane principle diagram, for the first MCIO port and the second MCIO port, refer to Tables 1 to 3 and Figure 2 Table 1 is an MCIO definition table based on the OCSP specification, Table 2 is an MCIO definition table based on the MGX specification, The MCIO connector is designed according to the Pin pin definition in Table 3, and except for the A11 pin (Sideband0), the A12 pin (Sideband1), the A26 pin (Sideband2), the A27 pin (Sideband3), the A29 pin (Sideband4), the A30 pin (Sideband5), the B9 pin (Sideband6), the B26 pin (Sideband7) and the B27 pin (Sideband8), other pins are consistent in the OCSP specification and the MGX specification.

[0035] Table 1:

[0036] Table 2:

[0037] Table 3:

[0038] Further, the adaptation pin is connected with the backboard processor, and a port type of the adaptation pin is set as bidirectional inout.

[0039] Further, the A11 pin and the A12 pin in the adaptation pin are used for the backboard processor to output to an external circuit after logical processing.

[0040] Further, with reference to Figure 3 , at least a central processing unit CPU, a management controller BMC and a mainboard processor for basic logic control of the mainboard are arranged on the mainboard, and the central processing unit CPU and the mainboard processor are respectively connected with the first MCIO port; The backboard at least includes one or more combinations of a hard disk backboard, a power supply backboard and a fan backboard, when the backboard is the hard disk backboard, the module connection port is a hard disk connector; The first MCIO port and the second MCIO port are equal in number and at least one, and the corresponding first MCIO port and the second MCIO port are connected through a standard MCIO cable; The backboard processor is a complex programmable logic device (CPLD), a field programmable logic gate array (FPGA) or a microprocessor; The backboard clock expander is used for expanding the input clock signal REFCLK_P / N of at least one MCIO connector, and the backboard clock expander is connected with at least one MCIO input clock signal.

[0041] Specifically, with reference to Figure 3 and Figure 4 , all 9 Sideband signals of MCIO in Table 1 are connected to the backboard processor (backboard CPLD logic device), if there are multiple MCIO connectors on the hard disk backboard, the Sideband of each MCIO needs to be connected to the CPLD.

[0042] With reference to Figure 5Because one MCIO in the MGX specification only defines one set of 100M clock signals, but in fact one MCIO will be connected with two hard disks, so two sets of clock signals are needed, so it is necessary to use a Clock Buffer (an independent clock expansion chip, which can be selected according to the actual number of hard disks, 4-Output / 8-Output, etc.) to expand the input clock on the hard disk backboard. The input of the Clock buffer is connected to the REFCLK_P / N provided by the MCIO1 (Pin B11 / B12 of the MCIO1 connector), and the output is connected to the hard disk connector. If there are multiple MCIO connectors on the hard disk backboard, the input clock signal Pin of other MCIOs can not be connected.

[0043] Further, the backboard further comprises: The project serial number acquisition module is used to indicate that the current connection mode is based on the Open Common Server Platform (OCSP) specification or the Modular GPU Acceleration Platform (MGX) specification, and the project serial number acquisition module is one of the IIC communication acquisition module and the hardware control mode acquisition module or a combination of the two.

[0044] Further, after the backboard processor obtains the project serial number ID, it is judged that the current connection mode is based on the OCSP specification or the MGX specification, and the specific pin definition of each adaptation pin is locked, If the corresponding adaptation pin is an input pin, it is assigned to the corresponding function variable of the backboard processor, and if the adaptation pin is an output pin, the logic variable generated by the backboard processor is output to this pin, and finally output to the target device through the second MCIO port.

[0045] Further, the application also proposes an adaptation method compatible with different MCIO connector Pin definitions, which is applied to an adaptation device compatible with different MCIO connector Pin definitions, and the adaptation device compatible with different MCIO connector Pin definitions comprises a first MCIO port and a second MCIO port connected through a standard MCIO cable, a central processing unit CPU and a main board clock generator connected with the first MCIO port, a backboard processor connected with the second MCIO port, a backboard clock expander and a module connection port, referring to Figure 7 and Figure 8 The adaptation method compatible with different MCIO connector Pin definitions comprises the following steps: S100, the backplane processor obtains a project serial number ID after power on, determines the current connection based on the Open Common Server Platform (OCSP) specification or the Modular GPU Acceleration Platform (MGX) specification through the project serial number ID; S200, if the current connection is based on the Open Common Server Platform (OCSP) specification, the adaptation pins are defined as PERST0#, PRSNT0#, PERST1#, PRSNT1#, HP_SMB_CLK, HP_SMB_DAT, N / C, N / C and HP_SMB_ALERT# in turn; S300, if the current connection is based on the Modular GPU Acceleration Platform (MGX) specification, the adaptation pins are defined as PERST0#, PRSNT0#, N / C, N / C, N / C, N / C, HP_SMB_ALERT#, HP_SMB_DAT and HP_SMB_CLK in turn; S400, when the adaptation pin is an input pin, the pin level value is assigned to the corresponding function module, and when the adaptation pin is an output pin, the pin level value is output to the external circuit through the backplane processor control.

[0046] Further, step S100 comprises: S110, when the project serial number acquisition module is based on an IIC communication acquisition module, the backplane processor communicates with the management controller BMC set on the mainboard through the IIC protocol, and the management controller BMC writes the current project serial number ID into the register of the IIC Slave module of the backplane processor through the IIC protocol; S120, when the project serial number acquisition module is based on a hardware control mode acquisition module, the backplane processor obtains the current project serial number ID by querying the level signal of the jumper cap or the dial switch set on the mainboard or the backplane; S130, when the project serial number acquisition module comprises an IIC communication acquisition module and a hardware control mode acquisition module, the backplane processor outputs the final project serial number ID by bitwise AND operation of the two obtained project serial number IDs.

[0047] Specifically, with reference to Figure 6 , the acquisition of the project serial number ID (Project_ID) must be one of the following two methods on the hardware, and both methods are reserved in some embodiments.

[0048] Method one: a group of BMC management I2C signals are connected to the CPLD, and the BMC directly writes the current ID into the register of the I2C Slave module inside the CPLD; Method two: a group of hardware signals are connected to the CPLD, and the external device realizes the conversion of different IDs by controlling the jumper cap or the dial switch.

[0049] For method one, after power-on, the BMC writes the current project ID (corresponding to Figure 6 SMB_BMC_SCL and SMB_BMC_SDA in the middle) to the hard disk backplane CPLD through I2C. For method two, the jumper cap / dial switch on the hard disk backplane is used to input the signal to the CPLD to obtain the hardware ID (corresponding to Figure 6 HW_ID0 to HW_ID7 in the middle).

[0050] The above two methods of obtaining Project_ID can be selected according to the actual situation, and if both methods are reserved, the two IDs obtained will be finally output as the final Project_ID after being bitwise ANDed in the CPLD code.

[0051] Referring to Table 4, the project ID obtained is used to confirm whether the MCIO Pin definition of the CPU mainboard connected to the hard disk backplane adopts the OCSP specification or the MGX specification.

[0052] Table 4:

[0053] After confirming the specific functions of Sideband0-8 according to the specification definition, if it is an input signal, it is assigned to the corresponding function variable of the CPLD, and if it is an output signal, the value of the logic variable generated inside the CPLD is output to this signal, and finally output to the target device through the MCIO.

[0054] It should be noted that the port type of Sideband0-8 should be set to bidirectional inout. In addition, if there are multiple MCIO connectors, the Sideband0-8 signals of each MCIO are processed in a similar manner.

[0055] For example, if the project ID obtained by the CPLD power-on indicates that the MCIO Pin definition is the OCSP specification, then the function of Sideband0 at this time is to input the PCIe reset signal of hard disk 0 to the CPLD, and in the CPLD, Sideband0 should be assigned to the corresponding module for controlling the PCIe reset of hard disk 0.

[0056] Further, the application also provides a computer readable storage medium, which stores program instructions, and the program instructions are executed by a processor to implement the adaptation method compatible with different MCIO connector pin definitions.

[0057] Part of the code is as follows: module top ( input wire cpld_clk, / / input, cpld 25M clock input wire Rst_n, / / input, cpld reset signal input wire [7:0] Hw_ID, / / input, hardware ID signal inout wire SMB_BMC_SCL, / / BMC SMBus clock signal inout wire SMB_BMC_SDA, / / BMC SMBus data signal inout wire Sideband0, / / input / output, connected to MCIO Pin A11 inout wire Sideband1, / / input / output, connected to MCIO Pin A12 inout wire Sideband2, / / input / output, connected to MCIO Pin A26 inout wire Sideband3, / / input / output, connected to MCIO Pin A27 inout wire Sideband4, / / input / output, connected to MCIO Pin A29 inout wire Sideband5, / / input / output, connected to MCIO Pin A30 inout wire Sideband6, / / input / output, connected to MCIO Pin B9 inout wire Sideband7, / / input / output, connected to MCIO Pin B26 inout wire Sideband8 / / input / output, connected to MCIO Pin B27 ); localparam OCSP = 8'd0; localparam MGX = 8'd1; wire [7:0] Project_ID; wire [7:0] wReg_ID; wire SMB_HP_SCL, SMB_HP_SDA, HP_SMB_ALERT; wire PERST0_N, PRSNT0_N, PERST1_N, PRSNT1_N; wire wOESDA_EXP1; / / hot plug module HP_SDA output, 1: HP_SDA output high impedance 0: HP_SDA output low / / *********** core part code *********** / / assign Project_ID = wReg_ID & Hw_ID; / / Get the current Project_ID to confirm the MCIOPin definition specification assign SMB_HP_SCL = (Project_ID == OCSP)? Sideband4 : ((Project_ID == MGX)? Sideband8 : Sideband2); / / Confirm the hot plug module input signal HP_SCL, OCSP: Sideband4, MGX: Sideband8, others: Sideband2 assign SMB_HP_SDA = (Project_ID == OCSP)? Sideband5 : ((Project_ID == MGX)? Sideband7 : Sideband3); / / Confirm the hot plug module input signal HP_SDA, OCSP: Sideband5, MGX: Sideband7, others: Sideband3 assign Sideband5 = (Project_ID == OCSP)? (wOESDA_EXP1? 1'bz : 1'b0) : PRSNT1_N; / / Assign value to Sideband5 when it is output, OCSP: HP_SDA output, others: hard disk in place assign Sideband7 = (Project_ID == MGX)? (wOESDA_EXP1? 1'bz : 1'b0) : PRSNT1_N; / / Assign value to Sideband7 when it is output, MGX: HP_SDA output, others: hard disk in place assign Sideband8 = (Project_ID == MGX)? 1'bz : HP_SMB_ALERT; / / Sideband8 is assigned a value when it is an output, MGX: N / C, others: HP_SMB_ALERT assign Sideband6 = (Project_ID == MGX)? HP_SMB_ALERT : 1'bz; / / Sideband6 is assigned a value when it is an output, MGX: HP_SMB_ALERT, others: N / C assign Sideband1 = (Project_ID == MGX)? (PRSNT0_N && PRSNT1_N) : PRSNT0_N; / / Sideband1 is assigned a value when it is an output, MGX: hard disk 0 or hard disk 1 is in place, others: hard disk 0 is in place assign Sideband3 = (Project_ID == MGX)? 1'bz : ((Project_ID == OCSP)? PRSNT1_N : (wOESDA_EXP1? 1'bz : 1'b0)); / / Sideband3 is assigned a value when it is an output, MGX: N / C, OCSP: hard disk 1 is in place, others: HP_SDA output assign PERST0_N = (Project_ID == OCSP)? Sideband0 : (PRSNT0_N? 1'b0 : Sideband0); / / reset signal of hard disk 0 output signal of hard disk control module, OCSP: Sideband0, others: according to hard disk 0 in place signal to make a judgment assign PERST1_N = (Project_ID == OCSP)? Sideband2 : (PRSNT1_N? 1'b0 : Sideband0); / / reset signal of hard disk 1 output signal of hard disk control module, OCSP: Sideband2, others: according to hard disk 1 in place signal to make a judgment / / The following two modules are general PCA9555 modules and I2C Slave modules, which are general modules, only for assisting understanding of the above logic, so only the top-level code is listed / / PCA9555 module, parse SMB_HP_SCL / SDA signal used to manage hard disk hot plug PCA9555 mIO_exp ( .iModule_Address(7'b0100000), / / ADDR = 7'h20 ->8'h40 .iClk(cpld_clk), .iRst(Rst_n), .iSCL(SMB_HP_SCL), .iSDA(SMB_HP_SDA), .onSDAOE(wOESDA_EXP1), .onIntOE(HP_SMB_ALERT) ); / / I2C Slave module, used to receive Project_ID from BMC to CPLD IIC_Slave IIC_Slave_inst ( .iClk(cpld_clk), .iRst(Rst_n), .iModule_Address(7'h68), .iSCL(SMB_BMC_SCL), .iSDA(SMB_BMC_SDA), .oReg_ID(wReg_ID) ); endmodule It should be appreciated that the steps of the methods in embodiments of the application can be realized or implemented by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable memory. The methods can use standard programming techniques. Each program can be implemented in a high-level procedural or object-oriented programming language to be used in conjunction with a computer system. However, if desired, the programs can be implemented in assembly or machine language, which can be made up of binaries. In any case, such a language can be a compiled or interpreted language. Furthermore, such programs can be run on a dedicated integrated circuit that is programmed for this purpose.

[0058] Further, the operations of the processes described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The processes described herein (or variations and / or combinations thereof) can be performed under the control of one or more computer systems configured with executable instructions (e.g., computer-executable instructions, one or more computer programs, or one or more applications) to perform the processes, and the computer programs can be stored on computer program distribution media, such as magnetic or optical storage media, flash memories, memory cards, or other non-transitory computer-readable media.

[0059] Further, the methods can be implemented in any type of computing platform operatively connected to a suitable computing platform, including but not limited to a personal computer, mini-computer, mainframe, workstation, network or distributed computing environment, separate or integrated computer platforms, or in communication with charged particle tools or other imaging devices, and the like. Aspects of the present application can be implemented in machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated to the computing platform, such as a hard disk, optical read and / or write storage media, RAM, ROM, and the like, such that it can be read by a programmable computer to configure and operate the computer to perform the processes described herein when the storage medium or device is read by the computer. In addition, the machine-readable code, or portions thereof, can be transmitted over wired or wireless networks. The present application described herein includes these and other different types of non-transitory computer readable storage media when such media include instructions or programs implementing the steps described above in conjunction with a microprocessor or other data processor. The present application can also include the computer itself when programmed in accordance with the methods and techniques described herein.

[0060] The computer program can be applied to input data to perform the functions described herein to transform the input data to generate output data that is stored to non-volatile memory. The output information can also be applied to one or more output devices such as a display. In a preferred embodiment of the present application, the transformed data represents a physical and tangible object, including a particular visual depiction of the physical and tangible object produced on a display.

[0061] The above description is only preferred embodiments of the present application, and the present application is not limited to the above-described embodiments, as long as the same means achieve the technical effects of the present application, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application should be included in the scope of protection of the present application. The technical solutions and / or embodiments of the present application can have various modifications and changes within the scope of protection.

Claims

1. An adapter device compatible with different MCIO connector pin definitions, used to be compatible with the different MCIO connector pin definitions based on open general server platform specifications and modular flexible architecture computing platform specifications, characterized in that, The adapter compatible with different MCIO connector pin definitions is installed within the server, which includes at least a motherboard and a backplane. The adapter compatible with different MCIO connector pin definitions includes: The first MCIO port is located on the server's motherboard. A motherboard clock generator, wherein the clock generator is mounted on the motherboard and connected to the first MCIO port; The second MCIO port is located on the backplane of the server, and the first MCIO port and the second MCIO port are connected via a standard MCIO cable; A backplane processor is disposed on the backplane of the server and is connected to the second MCIO port; A backplane clock extender is used to extend the clock port, and the backplane clock extender is installed on the backplane of the server; A module connection port is used to connect downstream modules. The module connection port is set on the backplane of the server. The second MCIO port and the backplane clock extender are respectively connected to the module connection port.

2. The adapter device compatible with different MCIO connector pin definitions according to claim 1, characterized in that, Based on the OCSP or MGX specification, each of the second MCIO ports is provided with an adapter pin for connection to the backplane processor. This adapter pin is used to adapt to both the OCSP and MGX specifications simultaneously. For each of the second MCIO ports, the adapter pin includes: Pins A11, A12, A26, A27, A29, A30, B9, B26, and B27.

3. The adapter device compatible with different MCIO connector pin definitions according to claim 2, characterized in that, The adapter pin is connected to the backplane processor, and the port type of the adapter pin is set to bidirectional inout.

4. The adapter device compatible with different MCIO connector pin definitions according to claim 2, characterized in that, Among the adapter pins, pins A11 and A12 are used by the backplane processor to perform logic processing and output to the external circuit.

5. The adapter device compatible with different MCIO connector pin definitions according to claim 1, characterized in that, The motherboard is provided with at least a central processing unit (CPU), a management controller (BMC), and a motherboard processor for basic logic control of the motherboard. The CPU and the motherboard processor are respectively connected to the first MCIO port. The backplate includes at least one or more of a hard drive backplate, a power supply backplate, and a fan backplate. When the backplate is a hard drive backplate, the module connection port is a hard drive connector. The number of the first MCIO port and the second MCIO port are equal and at least one, and the corresponding first MCIO port and second MCIO port are connected through a standard MCIO cable; The backplane processor is a complex programmable logic device, a field-programmable gate array, or a microprocessor; The backplane clock extender is used to extend the input clock signal REFCLK_P / N of at least one MCIO connector, and the backplane clock extender is connected to at least one MCIO input clock signal.

6. The adapter device compatible with different MCIO connector pin definitions according to claim 1, characterized in that, The back plate also includes: The project serial number acquisition module is used to indicate whether the current connection method is based on the open general server platform specification or the modular and flexible architecture computing platform specification. The project serial number acquisition module is one or a combination of IIC communication acquisition module and hardware control method acquisition module.

7. The adapter device compatible with different MCIO connector pin definitions according to claim 6, characterized in that, After obtaining the project serial number ID, the backplane processor determines whether the current connection method is based on the OCSP or MGX specification, and then locks the specific pin definition for each adapter pin. If the corresponding adapter pin is an input pin, it is assigned to the corresponding function variable of the backplane processor. If the adapter pin is an output pin, the logic variable generated inside the backplane processor is output to this pin, and finally output to the target device through the second MCIO port.

8. An adaptation method compatible with different MCIO connector pin definitions, applied to an adaptation device compatible with different MCIO connector pin definitions, wherein the adaptation device includes a first MCIO port and a second MCIO port connected via a standard MCIO cable, a central processing unit (CPU) and a motherboard clock generator connected to the first MCIO port, a backplane processor, a backplane clock extender, and a module connection port connected to the second MCIO port, characterized in that... The aforementioned adaptation method for compatibility with different MCIO connector pin definitions includes the following steps: S100: After power-on, the backplane processor obtains the project serial number ID and determines whether the current connection is based on the Open General Server Platform Specification or the Modular Flexible Architecture Computing Platform Specification. S200. If the current connection is based on the Open General Server Platform Specification, the adapter pins are defined sequentially as PERST0#, PRSNT0#, PERST1#, PRSNT1#, HP_SMB_CLK, HP_SMB_DAT, N / C, N / C and HP_SMB_ALERT#. S300. If the current connection is based on the modular flexible architecture computing platform specification, the adapter pins are defined sequentially as PERST0#, PRSNT0#, N / C, N / C, N / C, N / C, HP_SMB_ALERT#, HP_SMB_DAT and HP_SMB_CLK. S400: When the adapter pin is an input pin, the pin level value is assigned to the corresponding functional module. When the adapter pin is an output pin, the pin level value is output to the external circuit through the backplane processor.

9. The adaptation method for compatibility with different MCIO connector pin definitions according to claim 8, characterized in that, Step S100 includes: S110. When the project serial number acquisition module is an IIC communication-based acquisition module, the backplane processor communicates with the management controller BMC set on the motherboard through the IIC protocol. The management controller BMC writes the current project serial number ID into the register of the IIC Slave module of the backplane processor through the IIC protocol. S120. When the project serial number acquisition module is a hardware control-based acquisition module, the backplane processor obtains the current project serial number ID by querying the level signal of the jumper cap or DIP switch set on the motherboard or backplane. S130. When the project serial number acquisition module includes an IIC communication-based acquisition module and a hardware control-based acquisition module, the backplane processor performs a bitwise AND operation on the two acquired project serial number IDs and outputs the final project serial number ID.

10. A computer-readable storage medium having program instructions stored thereon, characterized in that, When the program instructions are executed by the processor, they implement the adaptation method as described in any one of claims 8 to 9, which is compatible with different MCIO connector pin definitions.

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