Interconnection method for accessing external equipment by multiple FPGAs, electronic equipment and medium
By constructing the initial topology of the data interconnect and solving the maximum matching graph, the connection between the FPGA and external devices is automatically determined, solving the interconnection problem in multi-FPGA systems with manual intervention and improving system frequency and performance.
Patent Information
- Application Number
- CN202511099311.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-07
- Publication Date
- 2025-11-18
AI Technical Summary
In existing multi-FPGA systems, manual intervention is required, which reduces system security and lifespan. Furthermore, the fixed interconnect structure limits circuit partitioning and layout optimization, affecting system performance.
By constructing an initial topology based on the first and second data cable controllers, the communication combination information between the FPGA and external devices is obtained, a bipartite graph is generated and the maximum matching graph is solved, the port connections of the data cable controllers are automatically determined, and a topology for multiple FPGAs to access external devices is generated.
It enables flexible adjustments without human intervention, increases system frequency, and optimizes system performance.
Smart Images
Figure CN120975002A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and more particularly to an interconnection method, electronic device, and medium for multiple FPGAs to access external devices. Background Technology
[0002] In multi-FPGA (Field-Programmable Gate Array) systems, circuit designs require access to external devices via the FPGA. The connection relationship between external devices and the FPGA significantly impacts the circuit partitioning and placement scheme, thereby affecting the overall system performance. Current technologies, when constructing multi-FPGA systems, involve selecting specific FPGAs and external devices, manually plugging and unplugging cables between the FPGA and the external devices to establish a fixed interconnection. This method not only relies heavily on manual intervention and experience, but repeated cable plugging and unplugging also reduces system security and lifespan. Furthermore, because it cannot accommodate the communication needs of different circuit designs, this fixed interconnection structure between the FPGA and external devices severely limits the optimization space for circuit partitioning and placement, thus affecting the overall system performance. Therefore, reducing manual intervention in the interconnection of multi-FPGA access to external devices, enabling flexible adjustments, thereby increasing the system frequency of multi-FPGA access to external devices, and optimizing the system performance of multi-FPGA access to external devices has become an urgent technical problem to be solved. Summary of the Invention
[0003] The purpose of this invention is to provide an interconnection method, electronic device, and medium for multiple FPGAs to access external devices, thereby increasing the system frequency and optimizing the system performance of multiple FPGAs accessing external devices.
[0004] According to a first aspect of the present invention, an interconnection method for multiple FPGAs to access external devices is provided, comprising: Step S1: Obtain an initial topology consisting of M FPGAs, K first data cable controllers, second data cable controllers, and T external devices. The first data cable controller includes multiple ports, the second data cable controller includes multiple ports, each FPGA is connected to at least one port of the first data cable controller, at least one port of each first data cable controller is connected to a port of the second data cable controller, and each external device is connected to one port of the second data cable controller. Step S2: Obtain the communication combination information between the FPGA and external devices {(F1,P1,L1),(F2,P2,L2),...,(F n ,P n ,L n ),...,(F N ,P N ,L N)},(F n ,P n ,L n ) represents the combined communication information between the nth FPGA and external devices, F n For the nth FPGA with a corresponding external device, P n For F n The corresponding external device, L n The first data cable and the second data cable can be used for F n and P n The list of connection identifiers for communication, where n ranges from 1 to N, where N is the external device being accessed, and N≤T; Step S3, based on each group (F) n ,P n Establish a corresponding first node A n Based on the x-th connection R between the first data connector and the second data connector x Establish a corresponding second node B x The value of x ranges from 1 to X, where X is the total number of connections between the first and second data connectors. Each L... n Includes at least one R x In A n With corresponding L n In each R x Corresponding B x Establish connections between them to generate a bipartite graph; Step S4: Obtain the maximum matching graph of the bipartite graph, wherein in the maximum matching graph, each A n Only with one B x Connect, and each B x At most one A n connect; Step S5: Based on each A in the maximum matching graph n Corresponding B x Establish connections between the internal ports of the first and second data cable connectors to generate a topology for multiple FPGAs to access external devices.
[0005] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in the first aspect of the present invention.
[0006] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions for performing the method described in the first aspect of the present invention.
[0007] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the interconnection method, electronic device, and medium for multiple FPGAs to access external devices provided by this invention achieve considerable technological advancement and practicality, and have broad industrial application value. It has at least the following beneficial effects: This invention first constructs an initial topology based on a first data connector and a second data connector. Then, it acquires the communication combination information between the FPGA and external devices. Based on the communication combination information between the FPGA and external devices and the initial topology, it constructs a bipartite graph, solves for the maximum matching graph of the bipartite graph, and determines each A in the maximum matching graph. n Corresponding B x The connection between the internal ports of the first and second data cable connectors is established to generate a topology for multiple FPGAs to access external devices. This requires no manual intervention, allows for flexible adjustments, improves the system frequency for multiple FPGAs accessing external devices, and optimizes the system performance. Attached Figure Description
[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0009] Figure 1 A flowchart illustrating the interconnection method for multiple FPGAs accessing external devices provided in an embodiment of the present invention. Detailed Implementation
[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0011] This invention provides an interconnection method for multiple FPGAs to access external devices, such as... Figure 1 As shown, it includes: Step S1: Obtain an initial topology consisting of M FPGAs, K first data cable controllers, second data cable controllers, and T external devices. The first data cable controllers include multiple ports, the second data cable controllers include multiple ports, each FPGA is connected to at least one port of the first data cable controller, at least one port of each first data cable controller is connected to a port of the second data cable controller, and each external device is connected to one port of the second data cable controller.
[0012] It should be noted that both the first and second data hubs are data hubs with multiple ports. The number of ports on the first and second data hubs can be the same or different, but the port numbers on both must meet the interconnection requirements between the FPGA and external devices. Each port on the first data hub can only connect to one external port and one internal port. The external port on the first data hub is either an FPGA port or a port on the second data hub. Similarly, each port on the second data hub can only connect to one external port and one internal port. The external port on the second data hub is either a port on the first data hub or a port on an external device. Each external device can only be accessed by one FPGA, therefore each external device is connected to one port on the second data hub. In the initial topology, no connections are established between the internal ports of the first data hub or between the internal ports of the second data hub.
[0013] Step S2: Obtain the communication combination information between the FPGA and external devices {(F1,P1,L1),(F2,P2,L2),...,(F n ,P n ,L n ),...,(F N ,P N ,L N )},(F n ,P n ,L n ) represents the combined communication information between the nth FPGA and external devices, F n For the nth FPGA with a corresponding external device, P n For F n The corresponding external device, L n The first data cable and the second data cable can be used for F n and P n The list of connection identifiers for communication, where n ranges from 1 to N, where N is the external device being accessed, and N≤T.
[0014] It should be noted that each group (F) n ,P n It can communicate through at least one connection between the first data cable and the second data cable, therefore each L n It includes at least one first data connector and one second data connector that can be used for F n and P n Communication connection identifiers.
[0015] Step S3, based on each group (F) n ,P n Establish a corresponding first node A n Based on the x-th connection R between the first data connector and the second data connector x Establish a corresponding second node B x The value of x ranges from 1 to X, where X is the total number of connections between the first and second data connectors. Each L... n Includes at least one R x In A n With corresponding L n In each R x Corresponding B x Establish connections between them to generate a bipartite graph.
[0016] It should be noted that step S3 can transform the problem of determining the internal port connections of the first and second data cable connectors into a bipartite graph problem, thereby improving the accuracy and efficiency of determining the strategy for determining the internal port connections of the first and second data cable connectors.
[0017] Step S4: Obtain the maximum matching graph of the bipartite graph, wherein in the maximum matching graph, each A n Only with one B x Connect, and each B x At most one A n connect.
[0018] Step S5: Based on each A in the maximum matching graph n Corresponding B x Establish connections between the internal ports of the first and second data cable connectors to generate a topology for multiple FPGAs to access external devices.
[0019] It should be noted that the maximum matching graph determines each (F) n ,P n The connection between the corresponding first and second data connectors required by the group, therefore, based on each A in the maximum matching graph n Corresponding B xThis allows you to determine the connection relationship between the internal ports of the first and second data cable connectors.
[0020] In a preferred embodiment, the first data cable and the second data cable have the same structure and number of ports, which facilitates the unified design and verification of the first data cable and the second data cable.
[0021] In a preferred embodiment, the connections between the M FPGAs and K first data crosslinkers are evenly distributed, and the connections between the K first data crosslinkers and second data crosslinkers are also evenly distributed to improve system performance. It should be noted that the even distribution of connections between the M FPGAs and K first data crosslinkers means that the connections between the M FPGAs and K first data crosslinkers are distributed as evenly as possible. That is, when it is possible to allocate the same number of connection ports to each FPGA on each first data crosslinker, then the same number of connection ports are allocated to each FPGA on each first data crosslinker. If an even distribution is not possible, then the number of connection ports allocated to each FPGA on each first data crosslinker is as close as possible. For example, the connections can be evenly distributed first, and the ports corresponding to the remainder number of first data crosslinkers can be allocated to the FPGAs corresponding to the remainder number. Similarly, the even distribution of connections between the K first data crosslinkers and second data crosslinkers is also to be as evenly distributed as possible.
[0022] As one embodiment, taking the first data cable and the second data cable as having the same structure and number of ports as an example. The number of ports of the first data cable and the number of ports of the second data cable are values in [max{⌈M / K⌉+1,K+N},2×P×M], where ⌈M / K⌉ represents rounding up the value of M / K, max{⌈M / K⌉+1,K+N} represents taking the maximum value between ⌈M / K⌉+1 and K+N, and ⌈M / K⌉+1 represents the minimum number of ports of the first data cable obtained under the condition that each FPGA is connected to one port of the first data cable, and each first data cable has one port connected to a port of the second data cable. K+N represents the minimum number of ports in the second data cable, provided that one port of the first data cable is connected to a port of the second data cable, and each external device is connected to one port of the second data cable. Since the first and second data cable have the same structure and number of ports, the maximum value of ⌈M / K⌉+1 and K+N is taken as the minimum range for the number of ports in both the first and second data cable. Because an FPGA may include multiple ports, and each external device can only be connected to a port of the second data cable, the maximum range for the number of ports in both the first and second data cable can be set to 2×P×M. This means that each port of each FPGA is connected to a port of the first data cable, and each port of each FPGA accesses a corresponding external device. It should be noted that an FPGA can access multiple external devices, but an external device can only be accessed by one FPGA. P is the number of ports in each FPGA used for connecting to ports of the first data cable.
[0023] As one embodiment, step S2 includes: Step S21: Divide the simulation design and set the divided simulation design on M FPGAs.
[0024] It should be noted that setting the simulation design on M FPGAs after partitioning is based on the premise that the initial topology can meet the requirements of interconnection between the FPGAs and external devices that need to communicate.
[0025] Step S22: Determine each group (F) based on the distribution of the segmented simulation design across M FPGAs. n ,P n ).
[0026] Step S23: Determine each group (F) based on the initial topology. n ,P n The corresponding L n ; Step S24, based on each (F n ,P n ,L n Generate {(F1,P1,L1),(F2,P2,L2),...,(F n ,P n ,L n ),...,(F N ,P N ,L N )}.
[0027] As one embodiment, step S4 includes: Step S41: Set n=1.
[0028] Step S42: Determine if the current bipartite graph contains a variable A. n Connected B x If it exists, proceed to step S43; otherwise, return to step S41.
[0029] It should be noted that if the current bipartite graph does not contain a node with A... n Connected B x If not, the maximum matching graph cannot be generated, and you need to return to step S41 and re-execute.
[0030] Step S43, for A n Choose B x Retain A in the bipartite graph n With the currently selected B x The connection is cleared from the bipartite graph to the currently selected B. x The corresponding other connections.
[0031] Step S44: If n=N, then the current bipartite graph is determined as the maximum matching graph; otherwise, set n=n+1 and return to step S42.
[0032] As one embodiment, step S4 can be implemented based on the Hopcroft-Karp algorithm, the Hungarian algorithm, or the network maximum flow algorithm.
[0033] As one embodiment, in step S5, the step is based on each A in the maximum matching graph. n Corresponding B x Establish connections between the internal ports of the first and second data cable connectors, including: Step S51, Place A n Corresponding B x The first data cable connected is identified as A. n The corresponding first data cable to be connected.
[0034] Step S52: Connect A to the first data cable to be connected. n Corresponding F n One port connected to the first data cable to be connected and B x The corresponding R x Establish a connection with the port of the first data cable to be connected.
[0035] Step S53: In the second data concatenation device, A n Corresponding B x The corresponding R x The port connected to the second data cable is A n Corresponding P n Establish a connection to one of the ports connected to the second data cable.
[0036] It should be noted that the initial topology consisting of M FPGAs, K first data cable connectors, second data cable connectors, and T external devices, plus the internal connections of the first and second data cable connectors, constitutes a topology for multiple FPGAs to access external devices.
[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0038] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of these steps can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. A process can be terminated when its operation is complete, but it may also have additional steps not included in the figures. A process can correspond to a method, function, procedure, subroutine, subroutine, etc.
[0039] This invention first constructs an initial topology based on a first data connector and a second data connector. Then, it acquires the communication combination information between the FPGA and external devices. Based on the communication combination information between the FPGA and external devices and the initial topology, it constructs a bipartite graph, solves for the maximum matching graph of the bipartite graph, and determines each A in the maximum matching graph. n Corresponding B xThe connection between the internal ports of the first and second data cable connectors is established to generate a topology for multiple FPGAs to access external devices. This requires no manual intervention, allows for flexible adjustments, improves the system frequency for multiple FPGAs accessing external devices, and optimizes the system performance.
[0040] This invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in this invention.
[0041] This invention also provides a computer-readable storage medium storing computer-executable instructions for performing the methods described in this invention.
[0042] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. A method for interconnecting multiple FPGAs to access external devices, characterized in that, include: Step S1: Obtain an initial topology consisting of M FPGAs, K first data cable controllers, second data cable controllers, and T external devices. The first data cable controller includes multiple ports, the second data cable controller includes multiple ports, each FPGA is connected to at least one port of the first data cable controller, at least one port of each first data cable controller is connected to a port of the second data cable controller, and each external device is connected to one port of the second data cable controller. Step S2: Obtain the communication combination information between the FPGA and external devices {(F1,P1,L1),(F2,P2,L2),...,(F n ,P n ,L n ),...,(F N ,P N ,L N )},(F n ,P n ,L n ) represents the combined communication information between the nth FPGA and external devices, F n For the nth FPGA with a corresponding external device, P n For F n The corresponding external device, L n The first data cable and the second data cable can be used for F n and P n The list of connection identifiers for communication, where n ranges from 1 to N, where N is the external device being accessed, and N≤T; Step S3, based on each group (F) n ,P n Establish a corresponding first node A n Based on the x-th connection R between the first data connector and the second data connector x Establish a corresponding second node B x The value of x ranges from 1 to X, where X is the total number of connections between the first and second data connectors. Each L... n Includes at least one R x In A n With corresponding L n In each R x Corresponding B x Establish connections between them to generate a bipartite graph; Step S4: Obtain the maximum matching graph of the bipartite graph, wherein in the maximum matching graph, each A n Only with one B x Connect, and each B x At most one A n connect; Step S5: Based on each A in the maximum matching graph n Corresponding B x Establish connections between the internal ports of the first and second data cable connectors to generate a topology for multiple FPGAs to access external devices.
2. The method according to claim 1, characterized in that, The first data cable and the second data cable have the same structure and number of ports.
3. The method according to claim 1 or 2, characterized in that, The connections between the M FPGAs and the K first data copiers are evenly distributed, and the connections between the K first data copiers and the second data copiers are evenly distributed.
4. The method according to claim 2, characterized in that, The number of ports of the first data cable and the number of ports of the second data cable are values in [max{⌈M / K⌉+1,K+N},2×P×M], where ⌈M / K⌉ represents the value of M / K rounded up, max{⌈M / K⌉+1,K+N} represents the maximum value between ⌈M / K⌉+1 and K+N, and P is the number of ports in each FPGA for connecting to the ports of the first data cable.
5. The method according to claim 1, characterized in that, Step S2 includes: Step S21: Divide the simulation design and set the divided simulation design on M FPGAs; Step S22: Determine each group (F) based on the distribution of the segmented simulation design across M FPGAs. n ,P n ); Step S23: Determine each group (F) based on the initial topology. n ,P n The corresponding L n ; Step S24, based on each (F n ,P n ,L n Generate {(F1,P1,L1),(F2,P2,L2),...,(F n ,P n ,L n ),...,(F N ,P N ,L N )}.
6. The method according to claim 1, characterized in that, Step S4 includes: Step S41: Set n=1; Step S42: Determine if the current bipartite graph contains a variable A. n Connected B x If it exists, proceed to step S43; otherwise, return to step S41. Step S43, for A n Choose B x Retain A in the bipartite graph n With the currently selected B x The connection is cleared from the bipartite graph to the currently selected B. x Other corresponding connections; Step S44: If n=N, then the current bipartite graph is determined as the maximum matching graph; otherwise, set n=n+1 and return to step S42.
7. The method according to claim 6, characterized in that, Step S4 is implemented based on the Hopcroft-Karp algorithm, the Hungarian algorithm, or the network maximum flow algorithm.
8. The method according to claim 1, characterized in that, In step S5, the step is based on each A in the maximum matching graph. n Corresponding B x Establish connections between the internal ports of the first and second data cable connectors. include: Step S51, Place A n Corresponding B x The first data cable connected is identified as A. n The corresponding first data cable to be connected; Step S52: Connect A to the first data cable to be connected. n Corresponding F n One port connected to the first data cable to be connected and B x The corresponding R x Establish a connection with the port of the first data cable to be connected; Step S53: In the second data concatenation device, A n Corresponding B x The corresponding R x The port connected to the second data cable is A n Corresponding P n Establish a connection to one of the ports connected to the second data cable.
9. An electronic device, characterized in that, include: At least one processor; And, a memory communicatively connected to the at least one processor; The memory stores instructions that are executed by the at least one processor, the instructions being configured to perform the method of any one of claims 1-8.
10. A computer-readable storage medium, characterized in that, The device stores computer-executable instructions for performing the method of any one of claims 1-8.