Driving method of display panel, pixel driving circuit and display device

Abstract

The invention discloses a driving method of a display panel, a pixel driving circuit and a display device, and the driving method comprises the steps: obtaining a flag bit state of the display panel, and judging whether the flag bit state reaches a preset trigger control condition or not; in response to the condition that the flag bit state reaches the preset trigger control condition, controlling the clock signal to stop outputting through the control module; a gate driving signal is output through the control module so as to conduct the switching transistor; through conduction of the switch transistor, the gate driving unit starts a level transmission signal so as to charge the pixel unit of the corresponding row of the gate driving unit through the data line. And in response to completion of charging of the pixel units in the corresponding row, outputting a gate driving signal through the control module, closing the switching transistor and resetting the stage transmission signal. According to the method, the problems of display picture tearing and jamming caused by mismatching of the display card output frame rate and the display panel refresh rate can be solved, and the display effect and the visual experience are improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a driving method for a display panel, a pixel driving circuit, and a display device. Background Technology

[0002] Display technology has always been a crucial research area in electronic devices. Current mainstream display technologies include Liquid Crystal Display (LCD) and Organic Light-Emitting Diode (OLED), with the display panel serving as the primary window for displaying image data. However, in these technologies, a mismatch between the graphics card's output frame rate and the display panel's refresh rate frequently occurs during graphics display, leading to screen tearing or stuttering, thus impacting the visual experience. Summary of the Invention

[0003] In view of this, this application provides a display panel driving method, pixel driving circuit and display device to solve the problem of screen tearing or stuttering in the prior art, which affects the visual experience.

[0004] To address the aforementioned technical problems, the first technical solution provided in this application is: a driving method for a display panel, comprising: acquiring the flag state of the display panel and determining whether the flag state reaches a preset trigger control condition; responding to the flag state reaching the preset trigger control condition, controlling a clock signal to stop outputting via a control module; outputting a gate driving signal via the control module to turn on a switching transistor; enabling a gate driving unit to activate a cascade signal via the cascade signal, thereby charging the pixel units of the corresponding row of the gate driving unit via a data line; responding to the completion of charging of the pixel units of the corresponding row, outputting the gate driving signal via the control module to turn off the switching transistor and reset the cascade signal.

[0005] In one embodiment, the step of enabling the gate driving unit to turn on the transmission signal via the switching transistor to charge the pixel units of the corresponding row of the gate driving unit through the data line includes:

[0006] The gate driving unit controls the scanning line of the corresponding row to be turned on, and the data line charges the pixel unit of the m-th row corresponding to the gate driving unit until the pixel unit of the m-th row is fully charged.

[0007] In response to the completion of charging of the pixel unit in the m-th row, the pixel unit in the (m+4)-th row is controlled to start charging via the cascading signal until the pixel unit in the (m+4)-th row is fully charged; where m≥1.

[0008] In one embodiment, before the control module outputs a gate drive signal to turn on the switching transistor, the following steps are included:

[0009] Obtain the closing time of the last scan line of the current display screen of the display panel;

[0010] The step of outputting a gate drive signal through the control module to turn on the switching transistor includes:

[0011] Based on the closing time of the last row of scan lines, a preset delay time is added to obtain the start display time of the next frame of the display panel;

[0012] Based on the start display time of the next frame of the displayed image, the control module outputs a gate drive signal to turn on the switching transistor.

[0013] In one embodiment, after the pixel unit in the corresponding row has completed charging, the control module outputs the gate drive signal, turns off the switching transistor, and resets the stage transmission signal, the process includes:

[0014] The control module outputs a start signal and controls the clock signal recovery signal output to start the next frame of the display.

[0015] In one embodiment, each of the next frame displays a picture starting from the first scan line of the display panel.

[0016] In one embodiment, after the control module outputs a start signal and controls the clock signal recovery signal output to start the next frame display, the process includes:

[0017] The flag state is reset, awaiting the next trigger control condition.

[0018] In one embodiment, obtaining the flag state of the display panel and determining whether the flag state meets a preset trigger control condition includes:

[0019] Obtain the currently displayed screen and determine whether the currently displayed screen contains duplicate content;

[0020] In response to the current display screen being repetitive content, it is determined whether the next frame of the current display screen has been drawn.

[0021] In response to the completion of the rendering of the next frame of the currently displayed screen, the state of the flag bit reaches the preset trigger control condition.

[0022] In one embodiment, each frame of the display includes eight clock signals;

[0023] The gate driving unit includes (8n+1) clock signals, and the (8n+1) clock signals are connected to the same input source of the gate driving unit; where n≥0.

[0024] To address the aforementioned technical problems, the second technical solution provided in this application is: a pixel driving circuit, comprising:

[0025] Multiple scan lines and multiple data lines, and multiple pixel units driven by the multiple scan lines and multiple data lines respectively;

[0026] Multiple cascaded gate drive units are respectively coupled to multiple scan lines one by one;

[0027] Multiple switching transistors are configured and connected one-to-one with multiple cascaded gate driving units. Each switching transistor is used to control the state switching of the gate driving unit in the corresponding row. Each switching transistor includes a gate, a source, and a drain. The gate is used to connect to the control signal line of the control module of the display device, the drain is connected to the input terminal of the gate driving unit in the corresponding row of the switching transistor, and the source is used to connect to the power supply voltage.

[0028] To solve the above-mentioned technical problems, the third technical solution provided in this application is: to provide a display device, comprising:

[0029] A control module is used to execute the driving method of the display panel described in any of the above-mentioned embodiments;

[0030] The display panel is electrically connected to the control module; the display panel includes the pixel driving circuit described in any of the above claims.

[0031] The beneficial effects of this application are as follows: Unlike existing technologies, the driving method for the display panel in this application includes: acquiring the flag state of the display panel and determining whether the flag state meets a preset trigger control condition; in response to the flag state meeting the preset trigger control condition, stopping the output of the clock signal through the control module; outputting a gate drive signal through the control module to turn on the switching transistor; enabling the gate drive unit to turn on the stage transmission signal through the turn-on transistor, thereby charging the pixel units of the corresponding row of the gate drive unit via the data line; and in response to the completion of charging of the pixel units of the corresponding row, outputting a gate drive signal through the control module to turn off the switching transistor and reset the stage transmission signal. This application, through improvements to the display panel hardware structure and redesign of the display panel circuit control method, enables timely interruption of the scanning of the current repeating frame when the graphics card is ready to display a new frame, quickly switching to display the new frame, solving the problem of screen tearing and stuttering caused by the mismatch between the graphics card output frame rate and the display panel refresh rate, and improving display effects and visual experience. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the structure of the display device provided in this application;

[0034] Figure 2 This is a schematic diagram of the structure of the display panel provided in this application;

[0035] Figure 3 This is a schematic diagram of the pixel driving circuit provided in this application;

[0036] Figure 4 This is a partial schematic diagram of the circuit structure of the pixel driving circuit provided in this application;

[0037] Figure 5 This is a flowchart of the driving method for the display panel provided in the first embodiment of this application;

[0038] Figure 6 This is a schematic diagram of the driving timing of the gate driving unit architecture of the 8T1C provided in this application;

[0039] Figure 7 This is a schematic diagram of the connection structure of the gate drive unit of the 8T1C provided in this application;

[0040] Figure 8This is a schematic diagram of the driving timing of the pixel driving circuit provided in this application;

[0041] Figure 9 yes Figure 5 The flowchart of the sub-steps of step S1 is provided;

[0042] Figure 10 This is a flowchart of the driving method for the display panel provided in the second embodiment of this application;

[0043] Figure 11 yes Figure 5 or Figure 10 The flowchart of the sub-steps of step S3 is provided;

[0044] Figure 12 yes Figure 5 or Figure 10 The flowchart of the sub-steps of step S4 is provided;

[0045] Figure 13 This is a flowchart of the driving method for a display panel provided in the third embodiment of this application.

[0046] Explanation of reference numerals in the attached figures:

[0047] 300. Display device; 301. Control module; 302. Built-in register; 303. Timing controller;

[0048] 200, Display panel; 201, Array substrate; 202, Color filter substrate; 203, Liquid crystal layer; 2031, Liquid crystal molecules;

[0049] 100. Pixel driving circuit; 10. Pixel unit; 20. Switching transistor; 30. Gate driving unit; 40. Source driver; 50. Level conversion unit; Data, data line; Gate, scan line; G, gate; S, source; D, drain; Vss, low level; CLK, clock signal; STV, start signal; KZ, control signal; K2, reference voltage signal; JC, stage signal; HC, scan signal; t1, off time; t2, delay time; RESET, reset signal; H, scan time of one line; INPUT, input terminal; OUTPUT, output terminal. Detailed Implementation

[0050] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0051] The terms "first" and "second" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications will also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0052] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0053] The research process of this application revealed that during the graphics display process on a computer display panel, the time it takes for a graphics card to render a frame typically depends on the complexity of the image. Because the complexity of the image constantly changes—that is, when the image is complex, the graphics card takes longer to render a frame, and when the image is simple, the rendering time is shorter—this causes the frame rate output by the graphics card to fluctuate accordingly.

[0054] However, the refresh rate of a display panel is usually fixed, leading to frequent mismatches between the graphics card's output frame rate and the display panel's refresh rate. When the graphics card's output frame rate and the display panel's refresh rate do not match, screen tearing occurs. That is, when the monitor is scanning the current display frame line by line, if the graphics card has already output a new frame, the display panel will simultaneously display a portion of both the new and old frames. For example, the upper half of the display panel may show the new frame, and the lower half may show the old frame, resulting in horizontal screen tearing or stuttering (which occurs when the frame rate is lower than the refresh rate), severely impacting the user's visual experience.

[0055] Currently, common methods to solve the aforementioned screen tearing or stuttering issues are to enable vertical sync (VPS) or variable refresh rate (VRR) technology. VRR technology allows the display panel's refresh rate to dynamically adjust to match the graphics card's output frame rate, alleviating screen tearing and stuttering to some extent. However, even with VRR technology, latency issues still exist because the display panel cannot predict the time required for the graphics card to render the next frame and cannot make timely and accurate refresh rate adjustments, thus affecting further improvements in display quality. Furthermore, when the graphics card's rendering capability is lower than the display panel's high refresh rate, the display panel will repeatedly display past frames. When a new frame is ready, it needs to complete the scanning of the currently repeated frames before displaying the new frame, causing a delay in the display of the new frame, which still affects the visual experience.

[0056] To address the aforementioned problems, this application provides a novel display panel driving method, pixel driving circuit, and display device.

[0057] Please see Figure 1 , Figure 1 This is a schematic diagram of the display device provided in this application.

[0058] The display device 300 provided in this application includes a control module 301 and a display panel 200. The control module 301 is used to execute the driving method of the display panel 200 as described in any one of the following. The display panel 200 is electrically connected to the control module 301. The display panel 200 includes a pixel driving circuit 100 as described in any one of the following.

[0059] The control module 301 is usually located on the main control board (not shown) outside the display panel 200, or integrated inside the processor (not shown) of the display device 300, and is connected to the display panel 200 through an interface (such as RGB, LVDS or MIPI).

[0060] The control module 301 can output control signal KZ and display start signal STV to the display panel 200, and can also monitor the flag status of the display panel 200. The flag status can be understood as the current display state value of the display panel 200, and can be stored in the built-in register 302. The built-in register 302 is connected to the control module 301, which monitors the flag status. For example, the flags can include A and B. Flag A can be used to mark whether the current display content of the display panel 200 is repeated (e.g., initial value 0, value incremented by 1 for each repetition). Flag B can be used to mark whether the graphics card has finished drawing a frame of display content (initial value 0, set to 1 upon completion). The start signal STV is used to restart the display of a new frame. By monitoring the flag status in real time and controlling the clock signal CLK output, the system can quickly respond to the graphics card's new frame completion signal, avoiding display delays caused by repeated frame scanning.

[0061] Please see Figure 1 The display device 300 also includes a timing controller 303 (TCON). The timing controller 303 is mainly responsible for receiving display screen data and instructions sent from the control module 301 and converting them into precise control signals KZ to coordinate the orderly operation of various parts of the display panel 200. For example, the timing controller 303 can generate synchronous timing signals to ensure that the display screen is scanned and refreshed in the correct time and order. It can also drive the source driver 40 (responsible for applying voltage to the pixel unit 10 through the data line Data) and the gate driver (responsible for turning on the TFTs (not shown) of the pixel unit 10 line by line, such as the gate driving unit 30 described below in this application) to control the line-by-line scanning of the display screen and the charging of the pixel unit 10.

[0062] Please see Figure 2 The display panel 200 provided in this application can be an LCD panel or an OLED panel, etc. Taking an LCD panel as an example, the display panel 200 includes an array substrate 201, a color filter substrate 202, and a liquid crystal layer 203 disposed between the array substrate 201 and the color filter substrate 202. The array substrate 201 includes a pixel driving circuit 100. Specifically, the liquid crystal layer 203 includes a plurality of liquid crystal molecules 2031. The pixel driving circuit 100 applies an electric field to the liquid crystal molecules 2031 to change the alignment direction of the liquid crystal molecules 2031, so as to achieve the purpose of light blocking and light transmission, thereby displaying a display image with varying shades and staggered patterns.

[0063] The details of the pixel driving circuit 100 will be described below.

[0064] Please see Figure 3 The pixel driving circuit 100 provided in this application includes: multiple scan lines Gate and multiple data lines Data, multiple pixel units 10 driven by the multiple scan lines Gate and multiple data lines Data respectively, multiple cascaded gate driving units 30 and multiple switching transistors 20.

[0065] like Figure 3 , Figure 4 and Figure 8 As shown, multiple cascaded gate driving units 30 are coupled one-to-one with multiple scan lines (Gates). Specifically, each gate driving unit 30 can be a Gate Driver on Array (GOA) unit, where each stage of the gate driving unit 30 generates a corresponding scan signal HC to drive the corresponding row of pixel units 10 to turn on. A data line (Data) is connected to a source driver 40, allowing the source driver 40 to apply voltage to the pixel unit 10 via the data line (Data).

[0066] Multiple cascaded gate driving units 30 are coupled one-to-one with multiple scan lines (Gates). Each gate driving unit 30 has a switching transistor 20 disposed at one end away from each scan line (Gate). Multiple switching transistors 20 are disposed and connected one-to-one with multiple cascaded gate driving units 30. Each switching transistor 20 is used to control the state switching of the gate driving unit 30 in the corresponding row, for example, turning the gate driving unit 30 on or off. Each switching transistor 20 includes a gate G, a source S, and a drain D. The gate G is connected to the control signal KZ line of the control module 301, and the drain D is connected to the input terminal of the gate driving unit 30 of the corresponding row of the switching transistor 20, specifically the stage carry signal terminal of the gate driving unit 30. The source S is connected to the power supply voltage (Voltage Source Supply, Vss). The control module 301 outputs the control signal KZ (high level), which can turn on the switching transistor 20, reset the stage carry signal JC, and stop the input of the data signal (voltage signal) of the current row. The control module 301 outputs the reference voltage signal K2 to force the clock signal CLK to remain at a low level Vss, cut off the normal clock signal CLK drive of the gate driving unit 30, and stop each gate driving unit 30 from scanning according to the original timing.

[0067] By turning on the gate drive signal using the switching transistor 20, it can be ensured that the pixel unit 10 is turned off in a timely manner after charging is completed, reducing signal interference. Using the switching transistor 20 to control the stage signal JC reset enables global synchronous control and improves the stability of the gate drive signal.

[0068] In this embodiment, the switching transistor 20 can be a TFT (Thin Film Transistor). The TFT can actively and precisely control the "on" and "off" as well as the "bright" and "dark" of each pixel unit 10, thereby displaying a clear, smooth, and colorful display image on the display panel 200.

[0069] In this embodiment, the timing controller 40 is electrically connected to both the control module 301 and the gate driving unit 30. The timing controller 40 receives information from the control module 301 and outputs a corresponding driving signal to the gate driving unit 30 based on this information. This allows the gate driving unit 30 to open or close the scan line gate, thereby enabling data input to the pixel unit 10. For example, by controlling the gate driving unit 30 to open the scan line gate of the first row of the first frame, a corresponding voltage signal can be input to the pixel unit 10 corresponding to the first row of the first frame.

[0070] In one embodiment, such as Figure 1 As shown, the pixel driving circuit 100 also includes a level shifting unit 50, which is coupled to both the timing controller 40 and the gate driving unit 30. The level shifting unit 50 converts the data signal obtained from the timing controller 40 into the signal format required by the gate driving unit 30, and simultaneously transmits the converted data signal to the gate driving unit 30. The level shifting unit 50 can provide various voltages to the gate driving unit 30; for example, a DC-DC converter can be used to convert DC power to different voltages.

[0071] The aforementioned pixel driving circuit 100 and display device 300 are improved based on the existing GOA circuit structure, with the addition of a switching transistor 20. The control logic is simple, the compatibility is good, and it is easy to promote and apply in different display devices 300. It can be expanded to adapt to various display scenario requirements.

[0072] To address the aforementioned issues, this application also provides a driving method for a display panel 200.

[0073] Please see Figure 5 , Figure 5 This is a flowchart of the driving method for the display panel provided in the first embodiment of this application.

[0074] The driving method for the display panel 200 provided in the first embodiment of this application may include the following steps:

[0075] S1: Obtain the flag status of the display panel 200 and determine whether the flag status meets the preset trigger control conditions.

[0076] Specifically, the flag bit can be stored in the built-in register 302, which is electrically connected to the control module 301. The flag bit status can be monitored by the control module 301. The built-in register 302 is connected between the output of the gate driving unit 30 and the gate of the switching transistor (TFT) of the pixel unit 10. It is used for timing control, temporary storage of data signals (such as control signal KZ, clock signal CLK, etc.) or grayscale data, to ensure that the signal is accurately transmitted to the switching transistor 20 at a specific timing (such as the rising edge of the clock), and to avoid insufficient charging or uneven display due to signal delay. For example, the flag bit can include A and B. Flag bit A can be used to mark whether the current display content of the display panel 200 is repeated content (e.g., the initial value of flag bit A is 0, and the value is increased by 1 for each repetition). Flag bit B can be used to mark whether the graphics card has finished drawing a frame of display. Flag bit B has an initial value of 0 and is set to 1 when the drawing is completed.

[0077] The gate driving unit 30 integrates the gate driving circuit on the array substrate 201 of the display panel 200 to achieve a line-by-line scanning driving method, thereby eliminating the gate driving circuit part and having the advantages of reducing production costs and realizing a narrow bezel design for the display panel 200.

[0078] The array of gate driving units 30 can contain multiple gate driving units 30 (GOAs). The gate driving units 30 can have 4T1C driving structures, 8T1C driving structures, etc. Each gate driving unit 30 has a conventional driving circuit, including a clock signal CLK terminal, a low-level Vss input terminal, an input terminal INPUT (input start signal STV or carry-level transfer signal JC), and an output terminal OUTPUT (e.g., ...). Figure 4 The gate driving unit 30 is used to drive the scan lines Gate of the display panel 200 line by line for scanning, including the Gate N terminal and the RESET terminal.

[0079] The preset trigger control condition can be understood as the dynamic frame synchronization control trigger condition. When the states of flags A and B both meet this control condition, the control module 301 outputs the corresponding control signal KZ. The control signal KZ acts on the gate G of the switching transistor 20, turning on the switching transistor 20. The low level Vss is transmitted through the switching transistor 20 to the stage transmission signal JC input terminal INPUT of all gate drive units 30, triggering the stage transmission signal JC reset operation of the gate drive unit 30 and resetting its internal drive state. The specific control method will be described below.

[0080] S2: In response to the flag state reaching the preset trigger control condition, the clock signal CLK is controlled by the control module 301 to stop output.

[0081] Specifically, when the states of flags A and B reach preset trigger control conditions, the clock signal CLK can be stopped by the control module 301. This means the control module 301 outputs a high-level or low-level control signal KZ to the switching transistor 20, causing the gate drive unit 30 to stop outputting the clock signal CLK, thus stopping all current clock signals CLK and keeping CLK at a low level (Vss). This promptly interrupts the normal clock drive output of the gate drive unit 30, quickly switching to display a new frame, significantly reducing display delay caused by waiting time for repeated frames, and improving screen smoothness. Alternatively, grounding the low level Vss can also stop the entire clock signal CLK output.

[0082] S3: The gate drive signal is output through the control module 301 to turn on the switching transistor 20.

[0083] Specifically, the gate drive signal can be a high level or a low level Vss. For example, it can be a high level here. By turning on the switching transistor 20, the gates G of all the switching transistors 20 in the corresponding row can be turned on.

[0084] S4: By turning on the switching transistor 20, the gate driving unit 30 is enabled to transmit the signal JC, so as to charge the pixel unit 10 of the corresponding row of the gate driving unit 30 through the data line Data.

[0085] Specifically, the cascade signal JC can be understood as the output signal of this stage being the input information of the next stage. The principle of cascade transmission is as follows: the output signal of each gate driving unit 30 is the enable signal of the next gate driving unit 30, and also the reset signal RESET of the previous row gate driving unit 30. When the first start signal STV is high (since the first row does not have an output enable signal from the previous row, a separate signal is needed as the start signal STV), when the rising edge of the first row clock signal CLK arrives, the first row output is high. At this time, the second row is enabled and high. When the rising edge of the second row clock signal CLK arrives, the second row output is high. At this time, the third row is enabled, and the first row is reset (i.e., the first row output is set to low Vss).

[0086] For ease of understanding, in practical applications, to reduce the requirements for the rise time of the high level of the scan line gate and improve charging efficiency, pre-charging is usually employed. This involves dividing the gate's on-time for each scan line into two segments: the first segment involves writing the voltages of other pixels of the same polarity to the electrodes of the pixel unit 10 in that row—this is "pre-charging"; the second segment involves writing the actual pixel voltage to the electrodes of the pixel unit 10 in that row. For example... Figure 8As shown, the timing of the high-level outputs of adjacent scan lines (or multiple lines) overlaps, meaning the timing of the high-level outputs of two (or more) adjacent gate drive units 30 overlaps. However, there is no carry or reset relationship between adjacent gate drive units 30. Segmented charging causes the scan signals HC of adjacent lines to overlap in time, optimizing charging efficiency while reducing the requirement for high-level rise time.

[0087] like Figures 6 to 7 As shown, taking the gate drive unit 30 with 8 clock signals CLK as an example, the gate enable time for each scan line is 4H (the first 3H is for pre-charging, and the last 1H is for actual charging). The high-level overlap time between two adjacent clocks is 3H, where H refers to the scan time of one line. OUTPUT N serves as the reset signal RESET for GOA N-4 and as the input signal for GOA N+4 (e.g., through the input terminal INPUT).

[0088] By enabling the stage transmission signal JC through the gate driving unit 30, the corresponding voltage signal can be input to the pixel unit 10 of the corresponding row of the gate driving unit 30 through the data line Data to charge it.

[0089] The embodiments provided in this application achieve global and accurate control of the array of gate driving units 30 by coordinating the control level transmission signal JC of the switching transistor 20 with the clock signal CLK, effectively solving the problems of screen tearing and stuttering, thereby optimizing the visual experience.

[0090] S5: In response to the completion of charging of the corresponding row of pixel unit 10, the control module 301 outputs a gate drive signal to turn off the switching transistor 20 and the reset stage transmission signal JC.

[0091] Specifically, when the pixel unit 10 in the current row is charging, since the current row is already open, it is essential to ensure that the current row is fully charged; otherwise, charging errors will occur, leading to incorrect display images. After the pixel unit 10 in the current row is fully charged, the gate of the switching transistor 20 can be turned off by the gate drive signal (e.g., low voltage) output by the control module 301, and the stage transmission signal JC is reset simultaneously. In this embodiment, after the pixel unit 10 in the current row is charged, a delay time t2 can be set. By setting the delay time t2, direct connection between high voltage and low voltage can be prevented, reducing safety risks. At the same time, setting the delay time t2 ensures the reliability of the operation sequence and prevents voltage direct connection from causing circuit damage. The overall solution effectively solves the problems of screen tearing and stuttering, improving the smoothness and clarity of the displayed image.

[0092] This application improves the hardware structure of the display panel 200 and redesigns the circuit control method of the display panel 200 to realize timely interruption of the scanning of the current repeated frame when the graphics card is ready to display a new frame, and quickly switch to displaying the new frame. This solves the problem of screen tearing and stuttering caused by the mismatch between the output frame rate of the graphics card and the refresh rate of the display panel 200, and improves the display effect and visual experience.

[0093] The control method of the display panel 200 of this application will be described in detail below.

[0094] S1: Obtain the flag status of the display panel 200 and determine whether the flag status meets the preset trigger control conditions.

[0095] like Figure 9 As shown, in any embodiment, step S1, which involves obtaining the flag state of the display panel 200 and determining whether the flag state meets the preset trigger control condition, may include:

[0096] S11: Get the currently displayed screen and determine whether the currently displayed screen contains duplicate content.

[0097] Specifically, when the currently displayed content is repeated, it can be assumed that the displayed content has been shown before. When the display panel 200 starts to repeatedly display a certain frame of content, the control module 301 can automatically increment the flag bit A by 1. For example, the first time it repeats, the flag bit A = 1, and the second time it repeats, the flag bit A = 2. It can be understood that if the currently displayed content is not repeated, step S12 is not executed. If the currently displayed content is not repeated, it is determined whether the states of flag bits A and B are N1, where N ≥ 1, i.e., whether flag bit A is equal to 0 and whether flag bit B is equal to 1. If the states of flag bits A and B are not N1, it waits for the next control condition to be triggered.

[0098] S12: In response to the current display screen being the same content, determine whether the next frame of the current display screen has been drawn.

[0099] Specifically, if the result of step S11 is that the currently displayed content is repeated, it means that the currently displayed content has already been displayed, and the display panel 200 can display a new content. At this time, it is determined whether the next frame of the currently displayed content has been drawn, so that the new frame can be displayed. It can be understood that if the next frame of the currently displayed content has not been drawn, step S13 will not be executed.

[0100] S13: In response to the completion of the next frame of the currently displayed screen, the flag state reaches the preset trigger control condition.

[0101] Specifically, referring to the description of step S11, when the currently displayed content is not repeating, the control module 301 can further determine whether the states of flag bits A and B are N1, where N≥1, i.e., whether flag bit A is equal to 0 and whether flag bit B is equal to 1. If the states of flag bits A and B are N1, it can be considered that the flag bit states have met the preset trigger control conditions. Entering the control flow only when the flag bit states meet the preset trigger control conditions, i.e., when the dynamic frame synchronization control trigger conditions are met, can prevent the system from starting if the graphics card is too fast and the display panel 200 has not yet finished displaying a complete frame of content; instead, it starts only when a complete frame has been refreshed and the currently displayed content is repeating, thus avoiding frame drops.

[0102] S2: In response to the flag state reaching the preset trigger control condition, the clock signal CLK is controlled by the control module 301 to stop output.

[0103] Specifically, stopping the output of the clock signal CLK can be understood as the clock control logic of the control module 301 acting to stop the normal high and low level alternation of the clock signal CLK, forcing the CLK signal to remain at a low level Vss, cutting off the normal clock drive of the gate drive unit 30, and causing each gate drive unit 30 to stop scanning according to the original timing.

[0104] S3: The gate drive signal is output through the control module 301 to turn on the switching transistor 20.

[0105] like Figure 10 As shown, Figure 10 This is a flowchart of the driving method for a display panel provided in the second embodiment of this application.

[0106] In the second embodiment, before step S3, in which the control module 301 outputs a gate drive signal to turn on the switching transistor 20, the following may be included:

[0107] S25: Get the closing time t1 of the last scan line Gate of the current display screen of display panel 200.

[0108] Specifically, the control module 301 obtains the shutdown time t1 of the last scan line gate of the current display screen, which is the time it takes for the last row of pixel units 10 to complete charging, thereby obtaining the display time of the next frame. For example, the calculation starts from the rising edge of the last clock signal CLK, and is increased by the width of one clock signal CLK, which is the shutdown time t1 of the last scan line gate.

[0109] It is understood that the other steps in the second embodiment are the same as those in the first embodiment, and will not be repeated here.

[0110] like Figure 11 As shown, in any embodiment, step S3, in which the control module 301 outputs a gate drive signal to turn on the switching transistor 20, may include:

[0111] S31: Based on the closing time t1 of the last scan line Gate, add a preset delay time t2 to obtain the start display time of the next frame of the display panel 200.

[0112] Specifically, based on the shutdown time t1 of the last scan line gate obtained by the control module 301, it can be further determined whether the shutdown time t1 has been reached. If it has, a delay time t2 can be further set. The specific duration of the delay time t2 can be set as needed. For example, based on the clock cycle of the gate driving unit 30, the relative time range of the delay time t2 can be 0.1H to 1H, preferably 0.1H to 0.5H, where H is the scan time of one line. H can be calculated according to different resolutions and refresh rates. For example, if the display panel 200 has a 4K resolution (effective area Active: 3840*2160, total area Total: 4400*2250) and a refresh rate of 60Hz, the scan time of one line H = 1 / 60 / 2250 ≈ 7.41 microseconds. By setting the delay time t2, it can be ensured that the scan line gate is completely shut off, avoiding the situation where high and low voltages are directly connected before the scan line gate is completely shut off, thereby avoiding safety hazards. It is understandable that adding the gate closing time t1 of the last scan line to the preset delay time t2 will give the actual time when the next frame of the display panel 200 will start displaying.

[0113] S32: Based on the start display time of the next frame, the control module 301 outputs a gate drive signal to turn on the switching transistor 20.

[0114] Specifically, after obtaining the actual time when the next frame of the display will begin, the control module 301 can output a gate drive signal, such as a high-level control signal KZ, to turn on the switching transistor 20.

[0115] S4: By turning on the switching transistor 20, the gate driving unit 30 is enabled to transmit the signal JC, so as to charge the pixel unit 10 of the corresponding row of the gate driving unit 30 through the data line Data.

[0116] like Figure 12As shown, in any embodiment, step S4, which enables the gate driving unit 30 to turn on the transmission signal JC by switching transistor 20, so as to charge the pixel unit 10 of the corresponding row of the gate driving unit 30 through the data line Data, may include:

[0117] S41: The gate driving unit 30 controls the corresponding row's scan line Gate to be turned on, and the data line Data is used to charge the pixel unit 10 of the m-th row corresponding to the gate driving unit 30 until the pixel unit 10 of the m-th row is fully charged.

[0118] Specifically, the gate driving unit 30 is connected to the scan line Gate and controls the scan line Gate of its row to be turned on, so that the data line Data can charge the input voltage signal of the pixel unit 10 corresponding to the gate driving unit 30 until the pixel unit 10 of that row is fully charged. Here, m ≥ 1. For example, the data line Data charges the pixel units 10 of the first, second, third, or fourth rows corresponding to the gate driving unit 30 one by one.

[0119] S42: In response to the completion of charging of pixel unit 10 in row m, control pixel unit 10 in row m+4 to start charging through the transmission signal JC until pixel unit 10 in row m+4 is fully charged.

[0120] Specifically, after the pixel unit 10 in row m has finished charging, the cascading signal JC controls the charging of pixel unit 10 in row m+4. For example, after the pixel unit 10 in row 1 (where m is 1) has finished charging, the cascading signal JC controls the charging of pixel unit 10 in row 5 (m+4). This cascading signal JC serves as both the charging stop signal for pixel unit 10 in row m and the charging start signal for pixel unit 10 in row m+4. That is, after the pixel unit 10 in row m has finished charging, the data line Data starts outputting a low level to pixel unit 10 in row m, and the data line Data corresponding to pixel unit 10 in row m+4 starts outputting a high level to charge pixel unit 10 in row m+4. It can be understood that, considering the delay time t2, after the pixel unit 10 in row m has finished charging, the pixel unit 10 in row m+4 starts charging after the delay time t2 ends.

[0121] In the embodiments provided in this application, the array of gate driving units 30 can adopt an 8T1C driving structure GOA circuit. Each display frame includes 8 clock signals CLK, and the gate driving unit 30 includes (8n+1) clock signals CLK, and the (8n+1) clock signals CLK are connected to the same input source of the gate driving unit 30, where n≥0. That is, in the embodiments of this application, four clock signals CLK are used as a unit. In each display frame, the timing controller 303 (TCON) repeats once every four timing steps, and repeats twice in each display frame.

[0122] The clock signal CLK terminal of the gate drive unit 30 is connected to the clock output of the control module 301. The minimum cycle unit is 8 clock signals CLK (i.e., 8 clock signals CLK are generated from the source, the number of clock signals CLK is (8n+1), n≥0, and (8n+1) clock signals CLK are connected to the same input source, such as CLK1, CLK9, CLK17, etc. are connected together). The high voltage VGH is about 19V~40V, the low voltage VGL is about -14V~-4V, and the negative voltage can be -11V~-5V. The reset signal RESET and the output terminal OUTPUT are connected in the conventional cascaded gate drive unit 30. The carry-level transmission signal JC input terminal INPUT is connected to the drain D of the newly added switching transistor 20.

[0123] For example, after charging the pixel units 10 in the first row corresponding to the gate driving unit 30, charging begins for the pixel units 10 in the fifth row, and so on, until the pixel units 10 in the second row are fully charged. After the pixel units 10 in the second row are fully charged, charging begins for the pixel units 10 in the sixth row, and so on, until all eight clock signals CLK in each frame have been executed, and then a new frame of display is scanned. It can be understood that since the refresh rate is fixed in the embodiments provided in this application, the start time of each frame is also fixed.

[0124] S5: In response to the completion of charging of the corresponding row of pixel unit 10, the control module 301 outputs a gate drive signal to turn off the switching transistor 20 and the reset stage transmission signal JC.

[0125] like Figure 13 As shown, Figure 13 This is a flowchart of the driving method for a display panel provided in the third embodiment of this application.

[0126] In the third embodiment, after step S5, in response to the completion of charging of the pixel unit 10 in the corresponding row, the control module 301 outputs a gate drive signal to turn off the switching transistor 20 and the reset stage transmission signal JC, the following may be included:

[0127] S6: The control module 301 outputs the start signal STV and the control clock signal CLK recovery signal to start the display of the next frame.

[0128] Specifically, after completing the above-mentioned stage transmission signal JC reset, the control module 301 outputs the start signal STV. Since the first scan line Gate does not have the output enable of the previous line, a separate signal is needed as the start signal STV. The start signal STV serves as a new frame scan start instruction, causing the clock control logic of the control module 301 to restore the normal clock signal CLK output, so that the array of the gate drive unit 30 is scanned again according to the normal timing, displaying the newly drawn frame display content of the graphics card, and realizing the update of the display screen.

[0129] Each subsequent frame of the display begins scanning from the first scan line (Gate) of the display panel 200. When the scan line (Gate) reaches the middle line, as soon as the new frame of the display is completed, the control signal KZ is immediately reset, locking the clock signal CLK. The clock signal CLK then stops scanning from the middle, instead of continuing from there. At this point, the clock signal CLK is reset, and scanning of the new frame's scan line (Gate) begins again from the first scan line (Gate). Because the received display image always starts scanning from the first scan line (Gate), screen tearing is avoided.

[0130] In the third embodiment, after step S6, in which the control module 301 outputs the start signal STV and the control clock signal CLK recovery signal to start the display of the next frame, the following may also be included:

[0131] S7: Reset the flag state and wait for the next preset trigger control condition to be triggered.

[0132] Specifically, the control module 301 restores the states of flag bits A and B in the built-in register 302 to their initial states (A=0, B=0), waiting for the next graphics card frame display completion signal and the flag bit state change to trigger the preset trigger control conditions. The clock signal CLK control logic defaults to normal output of the enable signal (outputting high and low levels at the original frequency); the control signal KZ is initially low level Vss (to turn off the switching transistor 20), and the start signal STV is output when the new frame display screen is triggered.

[0133] It is understood that the other steps in the third embodiment are the same as those in the first embodiment, and will not be repeated here.

[0134] The display panel driving method disclosed in this application includes: acquiring the flag state of the display panel and determining whether the flag state meets a preset trigger control condition; in response to the flag state meeting the preset trigger control condition, controlling the clock signal to stop output through a control module; outputting a gate drive signal through the control module to turn on the switching transistor; turning on the switching transistor to enable the gate drive unit to turn on the stage transmission signal, so as to charge the pixel units of the corresponding row of the gate drive unit through the data line; in response to the completion of charging of the pixel units of the corresponding row, outputting a gate drive signal through the control module to turn off the switching transistor and reset the stage transmission signal. This application, through improvements to the display panel hardware structure and redesign of the display panel circuit control method, enables timely interruption of the scanning of the current repeating frame when the graphics card is ready to display a new frame, quickly switching to display the new frame, solving the problem of screen tearing and stuttering caused by the mismatch between the graphics card output frame rate and the display panel refresh rate, and improving display effect and visual experience.

[0135] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A driving method for a display panel, characterized in that, Obtain the flag state of the display panel and determine whether the flag state meets the preset trigger control conditions; In response to the flag state reaching the preset trigger control condition, the clock signal is stopped from being output via the control module. The control module outputs a gate drive signal to turn on the switching transistor. By turning on the switching transistor, the gate driving unit is enabled to transmit signals, so as to charge the pixel units of the corresponding row of the gate driving unit through the data line. In response to the completion of charging of the pixel unit in the corresponding row, the control module outputs the gate drive signal to turn off the switching transistor and reset the stage transmission signal.

2. The driving method for the display panel according to claim 1, characterized in that, The step of enabling the gate driving unit to turn on the transmission signal via the switching transistor, so as to charge the pixel units of the corresponding row of the gate driving unit through the data line, includes: The gate driving unit controls the scanning line of the corresponding row to be turned on, and the data line charges the pixel unit of the m-th row corresponding to the gate driving unit until the pixel unit of the m-th row is fully charged. In response to the completion of charging of the pixel unit in the m-th row, the pixel unit in the (m+4)-th row is controlled to start charging via the cascading signal until the pixel unit in the (m+4)-th row is fully charged; where m≥1.

3. The driving method for the display panel according to claim 1, characterized in that, Before the control module outputs a gate drive signal to turn on the switching transistor, the process includes: Obtain the closing time of the last scan line of the current display screen of the display panel; The step of outputting a gate drive signal through the control module to turn on the switching transistor includes: Based on the closing time of the last row of scan lines, a preset delay time is added to obtain the start display time of the next frame of the display panel; Based on the start display time of the next frame of the displayed image, the control module outputs a gate drive signal to turn on the switching transistor.

4. The driving method for a display panel according to claim 1, characterized in that, After the pixel unit in the corresponding row completes charging, the control module outputs the gate drive signal, turns off the switching transistor, and resets the stage transmission signal, the process includes: The control module outputs a start signal and controls the clock signal recovery signal output to start the next frame of the display.

5. The driving method for a display panel according to claim 4, characterized in that, Each of the next frame displays a picture starting from the first scan line of the display panel.

6. The driving method for a display panel according to claim 4, characterized in that, After the control module outputs a start signal and controls the clock signal recovery signal output to start the next frame display, the process includes: The flag state is reset, awaiting the next trigger control condition.

7. The driving method for a display panel according to claim 1, characterized in that, The step of obtaining the flag state of the display panel and determining whether the flag state meets the preset trigger control condition includes: Obtain the currently displayed screen and determine whether the currently displayed screen contains duplicate content; In response to the current display screen being repetitive content, it is determined whether the next frame of the current display screen has been drawn. In response to the completion of the rendering of the next frame of the currently displayed screen, the state of the flag bit reaches the preset trigger control condition.

8. The driving method for a display panel according to any one of claims 1 to 7, characterized in that, Each frame of the display includes eight clock signals; The gate driving unit includes (8n+1) clock signals, and the (8n+1) clock signals are connected to the same input source of the gate driving unit; where n≥0.

9. A pixel driving circuit, characterized in that, include: Multiple scan lines and multiple data lines, and multiple pixel units driven by the multiple scan lines and multiple data lines respectively; Multiple cascaded gate drive units are respectively coupled to multiple scan lines one by one; Multiple switching transistors are configured and connected one-to-one with multiple cascaded gate driving units. Each switching transistor is used to control the state switching of the gate driving unit in the corresponding row. Each switching transistor includes a gate, a source, and a drain. The gate is used to connect to the control signal line of the control module of the display device, the drain is connected to the input terminal of the gate driving unit in the corresponding row of the switching transistor, and the source is used to connect to the power supply voltage.

10. A display device, characterized in that, include: A control module is used to execute the driving method of the display panel according to any one of claims 1 to 8; The display panel is electrically connected to the control module; the display panel includes the pixel driving circuit as described in claim 9.

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