Circuit structure for solving single particle inversion and method for solving single particle inversion
By modifying the static memory cell to construct an embedded majority voter, the delay and area problems introduced by the external majority voting circuit are solved, high-reliability single-event upset protection is achieved, and the chip design is optimized.
Patent Information
- Application Number
- CN202511066105.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-30
- Publication Date
- 2025-11-18
AI Technical Summary
In the prior art, external majority voting circuits introduce additional signal propagation delays, increase chip area and layout and wiring complexity in integrated circuits, and may also be affected by single-event effects, leading to reliability issues.
The majority voter circuit structure using static memory is constructed by modifying the static memory cells within the chip to build an embedded majority voter. The majority voting logic is implemented using three sets of two-input NAND gates and one three-input NOR gate, reducing the delay and area overhead of external circuits.
Without sacrificing or even improving system performance, it significantly optimizes chip area and design complexity, improves circuit reliability in radiated environments, and effectively shields against the effects of single-event upsets.
Smart Images
Figure CN120977347A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a circuit structure and method for solving single-event inversion. Background Technology
[0002] In high-radiation environments such as aerospace, nuclear industrial facilities, and high-energy physics experiments, integrated circuits face severe challenges posed by high-energy particles. Among these, single-event upsets (SEUs) are a particularly prominent type of soft error. When a high-energy particle (such as a proton, neutron, or heavy ion) passes through the active region of a semiconductor device, it generates a large number of electron-hole pairs along its path, forming a transient current pulse. If this current pulse is strong enough, it can cause the logic state of a memory cell (such as an SRAM cell) to flip unexpectedly (e.g., from "0" to "1" or from "1" to "0"), or interfere with the normal judgment of the logic circuit, thereby causing system malfunctions.
[0003] To improve the reliability of circuits in radiated environments, the industry has developed various hardening techniques. Among them, majority voting circuits are a widely used system-level hardening strategy. However, traditional majority voters are usually implemented as a separate external circuit composed of standard logic gates (such as AND gates and OR gates). In highly integrated chip designs, this approach has some inherent drawbacks. First, introducing an external voting circuit inevitably increases additional signal propagation delay, which can affect the timing performance of the entire system, especially critically in high-frequency applications. Second, the voting circuit itself also requires additional chip area, increasing the complexity and cost of placement and routing. Finally, the voting circuit itself may also be affected by single-event effects, and its reliability must also be considered.
[0004] Therefore, there is an urgent need for a new technical solution that can effectively suppress single-event upsets while reducing or avoiding the delay and area overhead problems caused by traditional external majority voting circuits. Summary of the Invention
[0005] The purpose of this invention is to provide a majority voter circuit structure using static memory and a method for solving single-event inversion, aiming to solve the technical problems in the prior art, such as additional signal propagation delay, increased chip area, and complex layout and wiring caused by using an external majority voter.
[0006] To achieve the above and other related objectives, the present invention provides a circuit structure for solving single-event inversion, comprising:
[0007] Three sets of two-input NAND gates, each set of which is modified from a six-transistor static memory unit; the three sets of two-input NAND gates are configured to receive two of three redundant input signals A, B, and C respectively; and
[0008] A three-input NOR gate, which is modified from at least one second six-transistor static memory cell, wherein the three input terminals of the three-input NOR gate are electrically connected to the output terminals of the three sets of two-input NAND gates respectively, and the output terminal of the three-input NOR gate is used as the voting output terminal of the majority voter circuit structure.
[0009] Preferably, before modification, the first six-transistor static memory cell and the second six-transistor static memory cell each include: a first inverter composed of a first PMOS transistor (M2) and a first NMOS transistor (M1); a second inverter composed of a second PMOS transistor (M4) and a second NMOS transistor (M3), the first inverter and the second inverter being cross-coupled to form a pair of memory nodes (Q, QB); and a first transmission transistor (M5) and a second transmission transistor (M6), the gates of the first transmission transistor and the second transmission transistor being connected to a word line and configured to connect the pair of memory nodes to a pair of bit lines respectively.
[0010] Preferably, the first six-transistor static memory cell modified into the structure of the two-input NAND gate includes: two parallel PMOS transistors (M2, M4), whose sources are connected to the power supply and whose drains are connected to the output of the NAND gate; and two series NMOS transistors (M1, M3), which are connected between the output of the NAND gate and ground; wherein the gates of the PMOS transistors and the gates of the NMOS transistors are respectively used as the two inputs of the two-input NAND gate.
[0011] Preferably, the at least one second six-transistor static memory cell modified into the structure of the three-input NOR gate includes: three parallel NMOS transistors (M1, M3, M3B) connected between the output terminal of the NOR gate and ground, the gates of the three NMOS transistors being used as the three input terminals of the NOR gate respectively; and three parallel PMOS transistors (M2, M4, M4B) connected between the power supply and the output terminal of the NOR gate, the gates of the three PMOS transistors being connected correspondingly to the three input terminals respectively.
[0012] Preferably, the logic function implemented by the majority voter circuit structure is to output the logic state when at least two of the three redundant input signals A, B, and C have the same logic state.
[0013] The present invention also provides a method for solving single-event inversion, comprising:
[0014] Step 1: Provide three redundant input signals A, B, and C;
[0015] Step 2: Construct three sets of two-input NAND gates using the first static memory unit. Use the three sets of two-input NAND gates to perform NAND logic operations on the input signals A and B, A and C, and B and C respectively to generate the first intermediate signal, the second intermediate signal, and the third intermediate signal.
[0016] Step 3: Construct a three-input NOR gate using the second static memory unit, and perform NOR logic operations on the first intermediate signal, the second intermediate signal, and the third intermediate signal to generate the voting output signal of the majority voter circuit.
[0017] Preferably, in step one, the step of providing three redundant input signals A, B and C includes: copying a functional module to be protected against single-event upsets into three copies, and providing the same input to the three functional modules, so that the output terminals of the three functional modules respectively provide the three redundant input signals A, B and C.
[0018] Preferably, the first static memory cell and the second static memory cell are six-transistor static memory cells before being used to construct the two-input NAND gate and the three-input NOR gate. The six-transistor static memory cell includes: a first inverter composed of a first PMOS transistor (M2) and a first NMOS transistor (M1); a second inverter composed of a second PMOS transistor (M4) and a second NMOS transistor (M3), the first inverter and the second inverter being cross-coupled to form a pair of memory nodes (Q, QB); and a first transmission transistor (M5) and a second transmission transistor (M6), the first transmission transistor and the second transmission transistor being controlled by a word line and used to connect the pair of memory nodes to a pair of bit lines.
[0019] Preferably, in step two, the first static memory cell is a six-transistor static memory cell, and the step of constructing the two-input NAND gate includes: disconnecting the first transfer NMOS transistor (M5) and the second transfer NMOS transistor (M6) in the six-transistor static memory cell from the original circuit, and disconnecting the connection between the storage nodes (Q, QB) composed of two cross-coupled inverters; connecting the gates of the two PMOS transistors (M2, M4) in the six-transistor static memory cell as the first input terminal, connecting the sources in parallel to the power supply, and connecting the drains in parallel as the output terminal of the NAND gate; and connecting the gates of the two NMOS transistors (M1, M3) in the six-transistor static memory cell as the second input terminal, and connecting them in series between the output terminal of the NAND gate and ground.
[0020] Preferably, in step three, the second static memory cell is at least two six-transistor static memory cells, and the step of constructing the three-input NOR gate includes: disconnecting the connection of the transfer NMOS transistors (M5, M6) in the at least two six-transistor static memory cells and the cross-coupling connection between the memory nodes (Q, QB); connecting three NMOS transistors (M1, M3, M3B) from the at least two six-transistor static memory cells in parallel between the output terminal of the NOR gate and ground, and using the gates of the three NMOS transistors as the three input terminals of the NOR gate respectively; and connecting three PMOS transistors (M2, M4, M4B) from the at least two six-transistor static memory cells in parallel between the power supply and the output terminal of the NOR gate, and connecting the gates of the three PMOS transistors to the three input terminals of the NOR gate respectively.
[0021] As described above, the circuit structure and method for solving single-event inversion of the present invention have the following beneficial effects:
[0022] This invention constructs an embedded majority voter by reconstructing standard SRAM cells at the circuit level. It not only achieves the core function of resisting single-event upsets, but also significantly optimizes the chip area and design complexity without sacrificing or even improving system performance. Attached Figure Description
[0023] Figure 1 The diagram shows a replica of three standard SRAM cells according to the present invention.
[0024] Figure 2 This is shown as the intended representation of the majority voting logic truth value in this invention;
[0025] Figure 3 The diagram shows a structural schematic of the first six-transistor static memory cell of the present invention being modified into a two-input NAND gate.
[0026] Figure 4 The diagram shows a structure in which at least one second six-transistor static memory cell of the present invention is modified into a three-input NOR gate.
[0027] Figure 5 The diagram shows a schematic of the majority voter circuit structure using a static memory according to the present invention.
[0028] Figure 6 The diagram shown illustrates the method for solving single-event inversion according to the present invention. Detailed Implementation
[0029] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0030] To address the issues of additional delay, area overhead, and reliability problems arising from the use of external majority voting mechanisms to combat single-event effects in existing technologies, embodiments of the present invention provide a method such as... Figure 5 The diagram shows a majority voter circuit structure using static memory. This structure modifies and reconnects the inherent static memory cells within the chip to form a fully functional majority voter. This method makes full use of existing layout resources, avoiding the need to design and lay out independent, external voting circuits to achieve triple modulo redundancy, thus significantly saving chip area, reducing layout and routing complexity, and effectively reducing additional signal propagation delays introduced by external circuits since the voting circuit is embedded, thereby improving the timing performance and integration of the entire system.
[0031] A majority voter circuit structure employing static memory includes: three sets of two-input NAND gates, each set of two-input NAND gates being modified from a first six-transistor static memory cell, the three sets of two-input NAND gates being configured to receive two of three redundant input signals A, B, and C respectively; and a three-input NOR gate, the three-input NOR gate being modified from at least one second six-transistor static memory cell, the three input terminals of the three-input NOR gate being electrically connected to the output terminals of the three sets of two-input NAND gates respectively, the output terminal of the three-input NOR gate being used as the voting output terminal of the majority voter circuit structure.
[0032] In some embodiments, the first six-transistor static memory cell and the second six-transistor static memory cell, before being modified, each include: a first inverter composed of a first PMOS transistor (M2) and a first NMOS transistor (M1); a second inverter composed of a second PMOS transistor (M4) and a second NMOS transistor (M3), the first inverter and the second inverter being cross-coupled to form a pair of memory nodes (Q, QB); and a first transmission transistor (M5) and a second transmission transistor (M6), the gates of the first transmission transistor and the second transmission transistor being connected to a word line and configured to connect the pair of memory nodes to a pair of bit lines respectively.
[0033] To form a bistable latch, the two inverters are cross-coupled. Specifically, the output of the first inverter (i.e., storage node Qn) is connected to the input of the second inverter (i.e., the gates of M4 and M3); simultaneously, the output of the second inverter (i.e., storage node Q) is connected to the input of the first inverter (i.e., the gates of M2 and M1). This positive feedback connection allows the circuit to have two stable states (Q=1, Qn=0 or Q=0, Qn=1), thus enabling the storage of 1 bit of information.
[0034] In some embodiments, please refer to Figure 3 The first six-transistor static memory cell was modified into a two-input NAND gate structure, comprising: two parallel PMOS transistors (M2, M4), with their sources connected to the power supply and their drains connected to the output of the NAND gate; and two series NMOS transistors (M1, M3), connected between the output of the NAND gate and ground; wherein the gates of the PMOS transistors and the NMOS transistors are used as the two inputs of the two-input NAND gate, respectively. This modification cleverly utilizes the original transistors in the 6T-SRAM cell, and by changing their connection relationship, the conversion from a memory cell to a logic gate is achieved. The entire process only requires modification of the metal interconnect layer, without changing the physical layout of the underlying transistors. Therefore, it is highly compatible with standard CMOS processes and has extremely high implementation flexibility and low cost advantages.
[0035] In some embodiments, please refer to Figure 4 At least one second-six transistor static memory cell is modified into a three-input NOR gate structure, comprising: three parallel NMOS transistors (M1, M3, M3B) connected between the output of the NOR gate and ground, with the gates of the three NMOS transistors serving as the three inputs of the NOR gate; and three parallel PMOS transistors (M2, M4, M4B) connected between the power supply and the output of the NOR gate, with the gates of the three PMOS transistors correspondingly connected to the three inputs. By paralleling transistors from two SRAM cells, logic gates can be easily constructed, which is beneficial for implementing majority voting logic. It is crucial because it corresponds precisely to the final NOR gate part of the majority voting logic Boolean expression after NAND-OR-NOT transformation, ensuring the integrity of the circuit function.
[0036] In some embodiments, the majority voting circuit structure implements the following logic function: when at least two of the three redundant input signals A, B, and C have the same logic state, it outputs that logic state. Specifically, this circuit implements the majority voting logic expression. like Figure 2 The truth table shows in detail all eight possible logical combinations of the three redundant input signals A, B, and C, and their corresponding voting outputs Y. For example, when inputs A, B, and C are 0, 0, and 1, logic "0" is in the majority, so the output Y is 0; while when inputs A, B, and C are 0, 1, and 1, logic "1" is in the majority, and the output Y is 1. This ensures that as long as no more than one of the three inputs errs, the output Y will always correctly reflect the state of the majority of modules. This logic function is the core of the triple modular redundancy system, ensuring that even if one of the three input signals errs due to a single-event upset, the final output of the circuit can still adopt the other two correct signals, thus effectively shielding the effects of single-event upsets and greatly improving the reliability of the circuit in a radiated environment.
[0037] This invention also provides a method for solving single-event inversion using a majority voter circuit with static memory, comprising the following steps:
[0038] Step 1: Provide three redundant input signals A, B, and C;
[0039] In some embodiments, step one, providing three redundant input signals A, B, and C, includes: copying a functional module to be protected against single-event upsets three times to form a matrix as shown in the figure. Figure 1 The structure shown provides the same input to the three functional modules, so that the outputs of the three functional modules provide three redundant input signals A, B and C respectively.
[0040] Step 2: Construct three sets of two-input NAND gates using the first static memory unit. Use the three sets of two-input NAND gates to perform NAND logic operations on input signals A and B, A and C, and B and C, respectively, to generate the first intermediate signal, the second intermediate signal, and the third intermediate signal.
[0041] In some embodiments, the first and second static memory cells are six-transistor static memory cells before being used to construct two-input NAND gates and three-input NOR gates. The six-transistor static memory cell includes: a first inverter consisting of a first PMOS transistor (M2) and a first NMOS transistor (M1); a second inverter consisting of a second PMOS transistor (M4) and a second NMOS transistor (M3), the first and second inverters being cross-coupled to form a pair of memory nodes (Q, QB); and a first transmission transistor (M5) and a second transmission transistor (M6), the first and second transmission transistors being controlled by a word line and used to connect the pair of memory nodes to a pair of bit lines.
[0042] To form a bistable latch, the two inverters are cross-coupled. Specifically, the output of the first inverter (i.e., storage node Qn) is connected to the input of the second inverter (i.e., the gates of M4 and M3); simultaneously, the output of the second inverter (i.e., storage node Q) is connected to the input of the first inverter (i.e., the gates of M2 and M1). This positive feedback connection allows the circuit to have two stable states (Q=1, Qn=0 or Q=0, Qn=1), thus enabling the storage of 1 bit of information.
[0043] In some embodiments, based on the above-mentioned six-transistor static memory cell, step two, the step of constructing a two-input NAND gate, includes: disconnecting the first transmission transistor (M5) and the second transmission transistor (M6) in the six-transistor static memory cell from the original circuit, and disconnecting the connection between a pair of memory nodes (Q, QB); connecting the gates of two PMOS transistors (M2, M4) in the six-transistor static memory cell as the first input terminal, connecting their sources in parallel to the power supply, and connecting their drains in parallel as the output terminal of the NAND gate; and connecting the gates of two NMOS transistors (M1, M3) in the six-transistor static memory cell as the second input terminal, and connecting them in series between the output terminal of the NAND gate and ground, forming a... Figure 3 The structure shown is shown. The core of this modification step lies in the reconstruction of the interconnections, rather than the remanufacturing of physical devices. This allows the method to be implemented in the back-end stage of chip design by modifying the metal layer mask, without any changes to the front-end process flow. This greatly shortens the hardened design cycle and reduces the risk of introducing errors.
[0044] Step 3: Construct a three-input NOR gate using the second static memory unit to perform NOR logic operations on the first intermediate signal, the second intermediate signal, and the third intermediate signal to generate the voting output signal of the majority voter circuit.
[0045] In some embodiments, based on the above-described six-transistor static memory cells, in step three, the second static memory cell is at least two six-transistor static memory cells. The step of constructing a three-input NOR gate includes: disconnecting the transmission transistors (M5, M6) and the cross-coupling connections between the memory nodes (Q, QB) in the at least two six-transistor static memory cells; connecting three NMOS transistors (M1, M3, M3B) from the at least two six-transistor static memory cells in parallel between the output terminal of the NOR gate and ground, and using the gates of the three NMOS transistors as the three input terminals of the NOR gate; and connecting three PMOS transistors (M2, M4, M4B) from the at least two six-transistor static memory cells in parallel between the power supply and the output terminal of the NOR gate, and connecting the gates of the three PMOS transistors to the three input terminals, forming a... Figure 4 The structure shown.
[0046] In some embodiments, the majority voting circuit structure implements the following logic function: when at least two of the three redundant input signals A, B, and C have the same logic state, it outputs that logic state. Specifically, this circuit implements the majority voting logic expression. like Figure 2 The truth table shows in detail all eight possible logical combinations of the three redundant input signals A, B, and C, and their corresponding voting outputs Y. For example, when inputs A, B, and C are 0, 0, and 1, logic "0" is in the majority, so the output Y is 0; while when inputs A, B, and C are 0, 1, and 1, logic "1" is in the majority, and the output Y is 1. This ensures that as long as no more than one of the three inputs errs, the output Y will always correctly reflect the state of the majority of modules. This logic function is the core of the triple modular redundancy system, ensuring that even if one of the three input signals errs due to a single-event upset, the final output of the circuit can still adopt the other two correct signals, thus effectively shielding the effects of single-event upsets and greatly improving the reliability of the circuit in a radiated environment.
[0047] Through the above steps, the static unit originally used for data storage is transformed into a circuit that performs logical voting functions, achieving functional reuse. The entire method is clear, highly operable, and the resulting circuit structure is compact, effectively solving the soft error problem caused by single-event upsets, while balancing chip performance, area, and cost. This provides an innovative and practical technical approach for the design of high-reliability integrated circuits.
[0048] In summary, this invention constructs an embedded majority voter by reconstructing standard SRAM cells at the circuit level. This not only achieves the core function of resisting single-event upsets, but also significantly optimizes the chip area and design complexity without sacrificing or even improving system performance.
[0049] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0050] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A circuit structure for solving single-event inversion, characterized in that, include: Three sets of two-input NAND gates, each set of two-input NAND gates is modified from a first six-transistor static memory unit, and the three sets of two-input NAND gates are configured to receive two of the three redundant input signals A, B and C respectively. as well as A three-input NOR gate, which is modified from at least one second six-transistor static memory cell, wherein the three input terminals of the three-input NOR gate are electrically connected to the output terminals of the three sets of two-input NAND gates respectively, and the output terminal of the three-input NOR gate is used as the voting output terminal of the majority voter circuit structure.
2. The circuit structure for solving single-event inversion according to claim 1, characterized in that: Before the modification, the first six-transistor static memory cell and the second six-transistor static memory cell each included: a first inverter composed of a first PMOS transistor (M2) and a first NMOS transistor (M1); a second inverter composed of a second PMOS transistor (M4) and a second NMOS transistor (M3), the first inverter and the second inverter being cross-coupled to form a pair of memory nodes (Q, QB); and a first transmission transistor (M5) and a second transmission transistor (M6), the gates of the first transmission transistor and the second transmission transistor being connected to a word line and configured to connect the pair of memory nodes to a pair of bit lines respectively.
3. The circuit structure for solving single-event inversion according to claim 1, characterized in that: The first six-transistor static memory cell modified into the structure of the two-input NAND gate includes: two parallel PMOS transistors (M2, M4), whose sources are connected to the power supply and whose drains are connected to the output of the NAND gate; and two series NMOS transistors (M1, M3), which are connected between the output of the NAND gate and ground; wherein the gates of the PMOS transistors and the gates of the NMOS transistors are respectively used as the two inputs of the two-input NAND gate.
4. The circuit structure for solving single-event inversion according to claim 1, characterized in that: The at least one second six-transistor static memory cell is modified into the structure of the three-input NOR gate, comprising: three parallel NMOS transistors (M1, M3, M3B) connected between the output of the NOR gate and ground, the gates of the three NMOS transistors being used as the three inputs of the NOR gate; and three parallel PMOS transistors (M2, M4, M4B) connected between the power supply and the output of the NOR gate, the gates of the three PMOS transistors being connected to the three inputs respectively.
5. The circuit structure for solving single-event inversion according to any one of claims 1 to 3, characterized in that: The logic function implemented by the majority voter circuit structure is to output the logic state when at least two of the three redundant input signals A, B, and C have the same logic state.
6. A method for resolving single-event inversion, characterized in that, At least including: Step 1: Provide three redundant input signals A, B, and C; Step 2: Construct three sets of two-input NAND gates using the first static memory unit. Use the three sets of two-input NAND gates to perform NAND logic operations on the input signals A and B, A and C, and B and C respectively to generate the first intermediate signal, the second intermediate signal, and the third intermediate signal. Step 3: Construct a three-input NOR gate using the second static memory unit, and perform NOR logic operations on the first intermediate signal, the second intermediate signal, and the third intermediate signal to generate the voting output signal of the majority voter circuit.
7. The method for solving single-event inversion according to claim 6, characterized in that: In step one, the step of providing three redundant input signals A, B and C includes: copying a functional module to be protected against single-event upsets into three copies, and providing the same input to the three functional modules, so that the output terminals of the three functional modules respectively provide the three redundant input signals A, B and C.
8. The method for solving single-event inversion according to claim 6, characterized in that: Before being used to construct the two-input NAND gate and the three-input NOR gate, the first and second static memory cells are six-transistor static memory cells, each comprising: a first inverter consisting of a first PMOS transistor (M2) and a first NMOS transistor (M1); a second inverter consisting of a second PMOS transistor (M4) and a second NMOS transistor (M3), the first and second inverters being cross-coupled to form a pair of memory nodes (Q, QB); and a first transmission transistor (M5) and a second transmission transistor (M6), the first and second transmission transistors being controlled by a word line and used to connect the pair of memory nodes to a pair of bit lines.
9. The method for solving single-event inversion according to claim 6, characterized in that: In step two, the first static memory cell is a six-transistor static memory cell. The step of constructing the two-input NAND gate includes: disconnecting the first transfer NMOS transistor (M5) and the second transfer NMOS transistor (M6) in the six-transistor static memory cell from the original circuit, and disconnecting the connection between the storage nodes (Q, QB) composed of two cross-coupled inverters; connecting the gates of the two PMOS transistors (M2, M4) in the six-transistor static memory cell as the first input terminal, connecting the sources in parallel to the power supply, and connecting the drains in parallel as the output terminal of the NAND gate; and connecting the gates of the two NMOS transistors (M1, M3) in the six-transistor static memory cell as the second input terminal, and connecting them in series between the output terminal of the NAND gate and ground.
10. The method for solving single-event inversion according to claim 6, characterized in that: In step three, the second static memory cell is at least two six-transistor static memory cells. The step of constructing the three-input NOR gate includes: disconnecting the connection of the transfer NMOS transistors (M5, M6) in the at least two six-transistor static memory cells and the cross-coupling connection between the memory nodes (Q, QB); connecting three NMOS transistors (M1, M3, M3B) from the at least two six-transistor static memory cells in parallel between the output terminal of the NOR gate and ground, and using the gates of the three NMOS transistors as the three input terminals of the NOR gate; and connecting three PMOS transistors (M2, M4, M4B) from the at least two six-transistor static memory cells in parallel between the power supply and the output terminal of the NOR gate, and connecting the gates of the three PMOS transistors to the three input terminals of the NOR gate.