Three-dimensional 2T0C-DRAM memory array, damaged unit replacement method and memory

Abstract

The invention belongs to the field of dynamic random access memory chips, and particularly discloses a three-dimensional 2T0C-DRAM memory array, a damaged unit replacement method and a memory. According to the method and the device, the faulty 2T0C-DRAM storage unit can be quickly detected, and the faulty 2T0C-DRAM storage unit can be accurately replaced on the hardware level on the basis of the stacking mode of the three-dimensional storage array, the replacement writing word line, the replacement reading word line, the replacement writing bit line and the replacement reading bit line group. According to the designed replacement mode, due to the fact that the independent standby storage array layer is arranged, the advantage that the influence on other areas in the storage array is small is achieved, and therefore the situation that the number of units of the storage array is reduced can be effectively avoided; in addition, the hardware replacement mode can effectively reduce the program addressing pressure of the memory device, so that the memory keeps stable operation. By means of the advantages, the storage array can keep relatively stable storage capacity, and the service life of the storage array is prolonged.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of dynamic random access memory chips, and more particularly, to a three-dimensional 2T0C-DRAM storage array, a damaged cell replacement method and a memory. BACKGROUND

[0002] A dynamic random access memory (DRAM) is mainly composed of a DRAM storage array, a data input / output buffer, a readout amplifier, a row address decoder and a column address decoder, wherein the storage array is the core part of the DRAM chip, each DRAM chip contains one or more DRAM storage arrays, the storage cells in the array are usually arranged in a rectangular manner, each storage cell stores 1-bit binary data, and the storage and reading of data are sequentially addressed through word lines and bit lines. The storage cell structure used in the DRAM chip is composed of a storage point and a control switch, wherein the storage point stores electric charge, and the more or less electric charge therein defines a bit binary data 1 or 0; the control switch controls the behavior of storing or dissipating electric charge in the storage point, and changes the data in the storage point.

[0003] The storage cells in the DRAM chip have a certain leakage, that is, the electric charge in the storage point will gradually flow out over time, so the DRAM chip is a volatile storage device, and it needs to be constantly refreshed with dynamic electric charge during operation to maintain the data stored in the storage array. At present, with the continuous improvement of the requirements of applications on the capacity density and access speed of the memory, the number of capacitors and transistors in the DRAM storage array increases sharply, and the size decreases significantly. This change reduces the stability and durability of the DRAM storage cell, greatly affects the service life of the DRAM chip, and becomes an important challenge for the development of the current memory field. SUMMARY

[0004] In view of the defects of the prior art, the purpose of the present application is to provide a three-dimensional 2T0C-DRAM storage array, a damaged cell replacement method and a memory, which aims to solve the problem of reduced service life of the existing DRAM chip.

[0005] To achieve the above-mentioned purpose, in a first aspect, the present application provides a three-dimensional 2T0C-DRAM storage array, comprising:

[0006] a vertically stacked 2T0C-DRAM storage array;

[0007] a 2T0C-DRAM backup storage array stacked above or below the 2T0C-DRAM storage array, used to replace a faulty 2T0C-DRAM storage cell in the 2T0C-DRAM storage array.

[0008] Preferably, the structure of the 2T0C-DRAM backup storage array is the same as that of each layer of the vertically stacked 2T0C-DRAM storage array.

[0009] It should be noted that the application preferably has the above structure design, so that the storage units in the 2T0C-DRAM backup storage array and the corresponding storage units in each layer of the vertically stacked 2T0C-DRAM storage array have a one-to-one corresponding relationship in space, thereby connecting the corresponding storage units through the following replacement wires, so that the 2T0C-DRAM backup storage array has the ability to replace damaged units in hardware; and the 2T0C-DRAM backup storage array itself has the ability to store information.

[0010] Preferably, the 2T0C-DRAM backup storage array is a ferroelectric 2T0C-DRAM backup storage array.

[0011] It should be noted that the application preferably utilizes the high reliability and non-volatile characteristics of ferroelectric memory, so that the 2T0C-DRAM backup storage array is more suitable for use as a backup storage unit, and can to some extent avoid the defect that the ferroelectric memory has lower write / read durability.

[0012] Preferably, the vertically stacked 2T0C-DRAM storage array is a three-layer 2T0C-DRAM storage array.

[0013] It should be noted that it is estimated that the 2T0C-DRAM storage array and the 2T0C-DRAM backup storage array are designed to be stacked in a 3:1 unit quantity ratio; more 2T0C-DRAM storage arrays are not selected to be used, and it is possible to ensure that the replacement units from the ferroelectric 2T0C-DRAM backup storage array are supplemented, so that the entire 2T0C-DRAM storage array remains in a working state, and fewer 2T0C-DRAM storage arrays are not selected to be used, so as to avoid wasting units in the ferroelectric 2T0C-DRAM backup storage array; in addition, the multi-layer stacked structure design of the storage array helps to improve the storage density.

[0014] Preferably, each write word line, each read word line, each write bit line, and each read bit line in the 2T0C-DRAM storage array is connected to the corresponding transistor and the corresponding pin of the corresponding 2T0C-DRAM storage unit through an e-fuse;

[0015] Each write word line, each read word line, each write bit line, and each read bit line in the ferroelectric 2T0C-DRAM backup storage array is connected to the corresponding transistor and the corresponding pin of the corresponding ferroelectric 2T0C-DRAM storage unit through an e-fuse;

[0016] The replacement write word lines, the replacement read word lines, the replacement write bit lines and the replacement read bit lines are respectively connected to corresponding pins of corresponding write word lines, corresponding read word lines, corresponding write bit lines, corresponding read bit lines and corresponding transistors of the ferroelectric 2T0C-DRAM memory cells in the 2T0C-DRAM memory array and the ferroelectric 2T0C-DRAM spare memory array through anti-fuses, and the replacement write word lines, the replacement read word lines, the replacement write bit lines and the replacement read bit lines are perpendicular to the horizontal plane of each layer of the 2T0C-DRAM memory array and the ferroelectric 2T0C-DRAM spare memory array.

[0017] To achieve the above-mentioned purpose, in a second aspect, the application provides a damaged cell replacement method for a three-dimensional 2T0C-DRAM memory array as described in the first aspect, comprising:

[0018] Periodically detecting the state of all 2T0C-DRAM memory cells in each layer of the 2T0C-DRAM memory array;

[0019] Comparing the data written / read in each 2T0C-DRAM memory cell during the global read / write process to determine whether the 2T0C-DRAM memory cell has failed or been damaged;

[0020] Marking the addresses of all damaged 2T0C-DRAM memory cells;

[0021] Performing a damaged cell replacement operation on the damaged 2T0C-DRAM memory cells.

[0022] Preferably, the determination of whether the 2T0C-DRAM memory cell has failed or been damaged is divided into three cases:

[0023] First, the data written in the 2T0C-DRAM memory cell is 1, and the data read is 1, the written and read data are the same, proving that the memory cell has not been damaged;

[0024] Second, the data written in the 2T0C-DRAM memory cell is 1, and the data read is 0, the written and read data are different, proving that the memory cell has been damaged;

[0025] Third, the data written in the 2T0C-DRAM memory cell is 0, and the data read is 0, it cannot be determined whether the memory cell has been damaged, but since the written and read data are the same, it is considered that the memory cell has not been damaged.

[0026] It should be noted that the application preferably designs the above method, which can quickly find and replace the damaged 2T0C-DRAM cell, ensure the normal operation of the storage system, improve the accuracy of the damaged 2T0C-DRAM cell detection, avoid the error replacement of the undamaged 2T0C-DRAM cell, and ensure that the above method can exist in parallel with the existing damaged cell processing method of the general memory device.

[0027] Preferably, the damaged 2T0C-DRAM storage cell is replaced by the damaged cell replacement operation, specifically as follows:

[0028] The damaged 2T0C-DRAM storage cell and the corresponding 2T0C-DRAM backup storage cell and the write word line, the read word line, the write bit line and the read bit line connected thereto are all disconnected, and the replacement write word line, the replacement read word line, the replacement write bit line and the replacement read bit line connected thereto are all connected.

[0029] The address of the 2T0C-DRAM backup storage cell that replaces the damaged 2T0C-DRAM storage cell generated in the damaged cell processing operation is marked as having been replaced.

[0030] It should be noted that the application preferably designs the above method, which can ensure that the damaged 2T0C-DRAM storage cell is normally replaced by the corresponding 2T0C-DRAM backup storage cell, without affecting other 2T0C-DRAM storage cells, and avoids the secondary replacement of the 2T0C-DRAM backup storage cell that has completed the replacement due to the damage of the corresponding other 2T0C-DRAM storage cell.

[0031] Preferably, a high voltage is applied to the write word line, the read word line, the write bit line and the read bit line connected to the damaged 2T0C-DRAM storage cell, and the write word line, the read word line, the write bit line and the read bit line connected to the corresponding ferroelectric 2T0C-DRAM backup storage cell are turned on, so that the electric fuse at the connection between the damaged 2T0C-DRAM storage cell and the write word line, the read word line, the write bit line and the read bit line connected thereto, and the electric fuse at the connection between the corresponding ferroelectric 2T0C-DRAM backup storage cell and the write word line, the read word line, the write bit line and the read bit line connected thereto are both fused, and the anti-fuse at the connection between the write word line, the read word line, the write bit line and the read bit line connected to the damaged 2T0C-DRAM storage cell and the replacement write word line, the replacement read word line, the replacement write bit line and the replacement read bit line connected thereto, and the anti-fuse at the connection between the corresponding ferroelectric 2T0C-DRAM backup storage cell transistor and the replacement write word line, the replacement read word line, the replacement write bit line and the replacement read bit line connected thereto are both turned on.

[0032] It should be noted that the application preferably designs the above method to complete the replacement of the damaged 2T0C-DRAM storage unit and the 2T0C-DRAM standby storage unit at the hardware level, and does not cause damage to the electrical connection of other 2T0C-DRAM storage units and 2T0C-DRAM standby storage units.

[0033] To achieve the above-mentioned purpose, in a third aspect, the application provides a memory comprising the three-dimensional 2T0C-DRAM storage array as described in the first aspect.

[0034] Overall, compared with the prior art, the above technical solutions conceived by the application have the following beneficial effects:

[0035] (1) The application provides a three-dimensional 2T0C-DRAM storage array, which replaces a faulty 2T0C-DRAM storage unit in the 2T0C-DRAM storage array through a 2T0C-DRAM standby storage array stacked above or below the 2T0C-DRAM storage array. By quickly detecting the faulty 2T0C-DRAM storage unit and based on the stacking mode of the three-dimensional storage array and the replacement of the write word line, the replacement of the read word line, the replacement of the write bit line, and the replacement of the read bit line group, the hardware level replacement processing of the faulty 2T0C-DRAM storage unit can be accurately performed. The designed replacement mode has the advantage of small influence on other areas in the storage array due to the setting of a separate standby storage array layer, thereby effectively avoiding the reduction of the number of units in the storage array; in addition, the hardware replacement mode can effectively reduce the program addressing pressure of the storage device, so that the storage memory remains stable operation. The above advantages can keep the storage array relatively stable in storage capacity and improve its service life.

[0036] (2) The application provides a damaged unit replacement method for the above-mentioned three-dimensional 2T0C-DRAM storage array. The method relies on the structure of the above-mentioned three-dimensional 2T0C-DRAM storage array, periodically detects all 2T0C-DRAM storage units in each layer of 2T0C-DRAM storage array, and determines whether each 2T0C-DRAM storage unit is faulty through a complete mechanism. Based on the structural design of the three-dimensional 2T0C-DRAM storage array and the physical properties of the electrical fuse and the anti-fuse used, the hardware replacement of the faulty 2T0C-DRAM storage unit is performed, the faulty 2T0C-DRAM storage unit is isolated from the 2T0C-DRAM storage array, and the corresponding ferroelectric 2T0C-DRAM standby storage unit in the 2T0C-DRAM standby storage array is replaced and applied to the corresponding position in the original 2T0C-DRAM storage array, thereby achieving the purpose of replacing the faulty storage unit. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 is a schematic diagram of a 2T0C-DRAM memory array structure provided by the present application.

[0038] Figure 2-1 is a schematic diagram of a 2T0C-DRAM memory array layer provided by the present application.

[0039] Figure 2-2 is an equivalent circuit diagram of a 2T0C-DRAM memory array layer provided by the present application.

[0040] Figure 3 is a schematic diagram of a 2T0C-DRAM memory cell used in a 2T0C-DRAM memory array layer provided by the present application.

[0041] Figure 4-1 is an equivalent circuit diagram of a 1T0C-DRAM memory cell that can be used in a 2T0C-DRAM memory array layer provided by the present application.

[0042] Figure 4-2 is an equivalent circuit diagram of a non-double-gate 2T0C-DRAM memory cell that can be used in a 2T0C-DRAM memory array layer provided by the present application.

[0043] Figure 4-3 is an equivalent circuit diagram of a 3T0C-DRAM memory cell that can be used in a 2T0C-DRAM memory array layer provided by the present application.

[0044] Figure 4-4 is an equivalent circuit diagram of a 4T0C-DRAM memory cell that can be used in a 2T0C-DRAM memory array layer provided by the present application.

[0045] Figure 5-1 is a schematic diagram of a ferroelectric 2T0C-DRAM backup memory array layer provided by the present application.

[0046] Figure 5-2 is an equivalent circuit diagram of a ferroelectric 2T0C-DRAM backup memory array layer provided by the present application.

[0047] Figure 6 is a schematic diagram of a ferroelectric 2T0C-DRAM memory cell used in a ferroelectric 2T0C-DRAM backup memory array layer provided by the present application.

[0048] Figure 7-1 is an equivalent circuit diagram of a ferroelectric 1T0C-DRAM memory cell that can be used in a ferroelectric 2T0C-DRAM backup memory array layer provided by the present application.

[0049] Figure 7-2is an equivalent circuit diagram of a ferroelectric 2T0C-DRAM memory cell that can be used in a ferroelectric 2T0C-DRAM spare memory array layer provided by the present application.

[0050] Figure 7-3 is an equivalent circuit diagram of a ferroelectric 3T0C-DRAM memory cell that can be used in a ferroelectric 2T0C-DRAM spare memory array layer provided by the present application.

[0051] Figure 7-4 is an equivalent circuit diagram of a ferroelectric 4T0C-DRAM memory cell that can be used in a ferroelectric 2T0C-DRAM spare memory array layer provided by the present application.

[0052] Figure 8 is an equivalent circuit diagram of a spare cell replacement wire group provided by the present application.

[0053] Figure 9 is a flow chart of a method for replacing a failed cell in a three-dimensional 2T0C-DRAM memory array provided by the present application.

[0054] In all the drawings, the same reference numerals are used to represent the same elements or structures, in which:

[0055] 101 - first 2T0C-DRAM memory array layer, 102 - second 2T0C-DRAM memory array layer, 103 - third 2T0C-DRAM memory array layer, 104 - ferroelectric 2T0C-DRAM spare memory array layer, 105 - spare cell replacement wire array, 1051 - spare cell replacement wire group;

[0056] 201 - 2T0C-DRAM memory cell matrix, 2011 - 2T0C-DRAM memory cell, 202 - write word line group, 2021 - write word line, 203 - read word line group, 2031 - read word line, 204 - write bit line group, 2041 - write bit line, 205 - read bit line group, 2051 - read bit line, 206 - ground line group, 2061 - ground line;

[0057] 301 - insulating fill medium, 302 - write transistor, 3021 - gate, 3022 - gate dielectric layer, 3023 - semiconductor thin film layer, 3024 - source, 3025 - drain, 303 - storage node, 304 - dual-gate read transistor, 3041 - first gate, 3042 - first gate dielectric layer, 3043 - semiconductor thin film layer, 3044 - source, 3045 - drain, 3046 - second gate dielectric layer, 3047 - second gate;

[0058] 501 - matrix of ferroelectric 2T0C-DRAM memory cells, 5011 - ferroelectric 2T0C-DRAM memory cell, 502 - set of replacement write word lines, 5021 - replacement write word line, 503 - set of replacement read word lines, 5031 - replacement read word line, 504 - set of replacement write bit lines, 5041 - replacement write bit line, 505 - set of replacement read bit lines, 5051 - replacement read bit line, 506 - set of ground lines, 5061 - ground line;

[0059] 601 - insulating fill medium, 602 - write transistor, 6021 - gate, 6022 - gate dielectric layer, 6023 - semiconductor thin film layer, 6024 - source, 6025 - drain, 603 - storage node, 604 - ferroelectric dual gate read transistor, 6041 - first gate, 6042 - ferroelectric thin film layer, 6043 - floating gate layer, 6044 - first oxide dielectric layer, 6045 - source, 6046 - drain, 6047 - second oxide dielectric layer, 6048 - second gate;

[0060] 801 - replacement write word line, 802 - replacement read word line, 803 - replacement write bit line, 804 - replacement read bit line, 811 - first 2T0C-DRAM memory cell, 812 - second 2T0C-DRAM memory cell, 813 - third 2T0C-DRAM memory cell, 814 - ferroelectric 2T0C-DRAM memory cell. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not used to limit the present application.

[0062] The term "and / or" herein is a description of an association relationship of associated objects, which means that there can be three relationships, for example, A and / or B can mean that there are three cases of A alone, A and B together, and B alone. The symbol " / " herein represents an or relationship of associated objects, for example, A / B represents A or B.

[0063] The terms "first" and "second" and the like in the description and claims herein are used to distinguish different objects, and not to describe a specific order of the objects. For example, the first response message and the second response message are used to distinguish different response messages, and not to describe a specific order of the response messages.

[0064] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0065] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, for example, multiple processing units means two or more processing units, multiple elements means two or more elements, etc.

[0066] Next, the technical solutions provided in the embodiments of this application will be described.

[0067] like Figure 1 As shown, this application proposes a three-dimensional 2T0C-DRAM (2transistors-0capacitor-DRAM) memory array, comprising a first part and a second part stacked sequentially, and a third part vertically penetrating the first part and the second part;

[0068] Preferably, the first part includes: a first 2TOC-DRAM memory array layer 101, a second 2TOC-DRAM memory array layer 102, and a third 2TOC-DRAM memory array layer 103; the second part includes: a ferroelectric 2TOC-DRAM spare memory array layer 104; and the third part includes: a spare cell replacement wire array 105 that penetrates the first 2TOC-DRAM memory array layer 101, the second 2TOC-DRAM memory array layer 102, the third 2TOC-DRAM memory array layer 103, and the ferroelectric 2TOC-DRAM spare memory array layer 104.

[0069] like Figure 1 As shown, preferably, the first, second, and third 2TOC-DRAM memory array layers 101, 102, and 103 are stacked sequentially from bottom to top; the three 2TOC-DRAM memory array layers have the same structure, and their projections on the plane completely overlap. The ferroelectric 2TOC-DRAM spare memory array layer 104 is located directly above the third 2TOC-DRAM memory array layer 103.

[0070] The number and stacking method of the 2T0C-DRAM memory array layers described herein do not represent a mandatory requirement for the number or stacking method of the DRAM memory array layers. In practice, the number or stacking method of the DRAM memory array layers needs to be designed according to factors such as the process technology, yield, demand, and cost of the memory chip.

[0071] Preferably, as shown in Figure 2-1 and Figure 2-2 The 2T0C-DRAM memory array layer includes: a 2T0C-DRAM memory cell matrix 201, a write word line group 202, a read word line group 203, a write bit line group 204, a read bit line group 205, and a ground line group 206.

[0072] The 2T0C-DRAM memory cell matrix includes: X*Y 2T0C-DRAM memory cells 2011 arranged in a square matrix in the horizontal direction;

[0073] The write word line group includes: X write word lines 2021 arranged in parallel in the horizontal direction, and each write word line 2021 is connected in series with a column of 2T0C-DRAM memory cells 2011;

[0074] The read word line group includes: X read word lines 2031 arranged in parallel in the horizontal direction, and each read word line 2031 is connected in series with a column of 2T0C-DRAM memory cells 2011;

[0075] The write bit line group includes: Y write bit lines 2041 arranged in parallel in the horizontal direction, and each write bit line 2041 is connected in series with a row of 2T0C-DRAM memory cells 2011;

[0076] The read bit line group includes: Y read bit lines 2051 arranged in parallel in the horizontal direction, and each read bit line 2051 is connected in series with a row of 2T0C-DRAM memory cells 2011;

[0077] The ground line group includes: Y ground lines 2061 arranged in parallel in the horizontal direction, and each ground line 2061 is connected in series with a row of 2T0C-DRAM memory cells 2011.

[0078] In the 2T0C-DRAM memory cell matrix 201, the write word line group 202, the read word line group 203, the write bit line group 204, the read bit line group 205, and the ground line group 206, X is the number of columns of 2T0C-DRAM memory cells 2011 in the 2T0C-DRAM memory cell matrix 201, and Y is the number of rows of 2T0C-DRAM memory cells 2011 in the 2T0C-DRAM memory cell matrix 201.

[0079] Preferably, as shown in Figure 3 The 2T0C-DRAM memory cell includes: an insulating filling medium 301, one write transistor 302, a storage node 303, and one double-gate read transistor 304, wherein,

[0080] Each write transistor 302 includes: a gate 3021, a gate dielectric layer 3022, a semiconductor thin film layer 3023, a source 3024, a drain 3025; the gate 3021 is connected to the write word line of the storage cell in series through an electrically fusible material, the source 3024 is connected to the write bit line of the storage cell in series through an electrically fusible material, and the drain 3025 is connected to the storage node 303.

[0081] Each double-gate read transistor 304 includes: a first gate 3041, a first gate dielectric layer 3042, a semiconductor thin film layer 3043, a source 3044, a drain 3045, a second gate dielectric layer 3046, and a second gate 3047; the first gate 3041 is connected to the storage node 303, the source 3044 is connected to the read bit line of the storage cell in series through an electrically fusible material, the drain 3045 is connected to the ground line of the storage cell in series, and the second gate 3047 is connected to the read word line of the storage cell in series through an electrically fusible material.

[0082] The insulating filling medium 301 fills the above structure and sufficiently covers the exposed surface of the above structure.

[0083] The electrically fusible material is a special kind of conductive material, which is characterized in that when a high voltage is applied to both ends of the material, a high current passing through the material will melt the material, causing the material to change from conductive to non-conductive.

[0084] The insulating medium layer wraps the above structure, sufficiently fills the exposed surface of the above structure, and isolates the first, second, and third 2T0C-DRAM storage array layers.

[0085] The 2T0C-DRAM storage cell matrix, write word line group, read word line group, write bit line group, read bit line group, and ground line group described herein do not represent a mandatory requirement for the type, structure, and arrangement of the storage cells, and the type, number, and arrangement of the corresponding lines. In some embodiments, the storage cells used in the storage array layer can also be other volatile memory cells, and there are different types, numbers, and connection methods of lines, including but not limited to: Figure 4-1 1T0C-DRAM (1 transistor-0 capacitor-DRAM, single transistor without capacitor DRAM) storage cell as shown in FIG. 1; Figure 4-2 non-double-gate 2T0C-DRAM storage cell as shown in FIG. 2; Figure 4-3 3T0C-DRAM (3 transistors-0 capacitor-DRAM, three transistors without capacitor DRAM) storage cell as shown in FIG. 3; Figure 4-4as shown, 4T0C-DRAM (3transistors-0capacitor-DRAM, four transistor capacitorless DRAM) memory cell, etc.

[0086] Preferably, as shown, the ferroelectric 2T0C-DRAM memory cell matrix 501 comprises X*Y ferroelectric 2T0C-DRAM memory cells 5011 arranged in a square matrix distribution in the horizontal direction. Figure 5-1 and Figure 5-2 Preferably, as shown, the ferroelectric 2T0C-DRAM memory cell matrix 501 comprises X*Y ferroelectric 2T0C-DRAM memory cells 5011 arranged in a square matrix distribution in the horizontal direction.

[0087] Preferably, as shown, the ferroelectric 2T0C-DRAM memory cell matrix 501 comprises X*Y ferroelectric 2T0C-DRAM memory cells 5011 arranged in a square matrix distribution in the horizontal direction.

[0088] Preferably, as shown, the ferroelectric 2T0C-DRAM memory cell matrix 501 comprises X*Y ferroelectric 2T0C-DRAM memory cells 5011 arranged in a square matrix distribution in the horizontal direction.

[0089] Preferably, as shown, the ferroelectric 2T0C-DRAM memory cell matrix 501 comprises X*Y ferroelectric 2T0C-DRAM memory cells 5011 arranged in a square matrix distribution in the horizontal direction.

[0090] Preferably, as shown, the ferroelectric 2T0C-DRAM memory cell matrix 501 comprises X*Y ferroelectric 2T0C-DRAM memory cells 5011 arranged in a square matrix distribution in the horizontal direction.

[0091] Preferably, as shown, the ferroelectric 2T0C-DRAM memory cell matrix 501 comprises X*Y ferroelectric 2T0C-DRAM memory cells 5011 arranged in a square matrix distribution in the horizontal direction.

[0092] Preferably, as shown, the ferroelectric 2T0C-DRAM memory cell matrix 501 comprises X*Y ferroelectric 2T0C-DRAM memory cells 5011 arranged in a square matrix distribution in the horizontal direction.

[0093] In the ferroelectric 2T0C-DRAM memory cell matrix 501, the replacement write word line group 502, the replacement read word line group 503, the replacement write bit line group 504, the replacement read bit line group 505 and the ground line group 506, X is the column number of the ferroelectric 2T0C-DRAM memory cell 5011 in the ferroelectric 2T0C-DRAM memory cell matrix 501, and Y is the row number of the ferroelectric 2T0C-DRAM memory cell 5011 in the ferroelectric 2T0C-DRAM memory cell matrix 501. Here, X and Y should be the same as X and Y described above in the 2T0C-DRAM memory array, respectively.

[0094] Preferably, as shown in the ferroelectric 2T0C-DRAM memory cell includes: an insulating filling medium 601, a write transistor 602, a storage node 603 and a ferroelectric double gate read transistor 604, wherein: Figure 6

[0095] Each write transistor 602 includes: a gate 6021, a gate dielectric layer 6022, a semiconductor thin film layer 6023, a source 6024, a drain 6025; the gate 6021 is connected to the replacement write word line of the ferroelectric memory cell in series through the electric fuse material, the source 6024 is connected to the replacement write bit line of the ferroelectric memory cell in series through the electric fuse material, and the drain 6025 is connected to the storage node 603.

[0096] Each ferroelectric double gate read transistor 604 includes: a first gate 6041, a ferroelectric thin film layer 6042, a floating gate layer 6043, a first oxide dielectric layer 6044, a source 6045, a drain 6046, a second oxide dielectric layer 6047, and a second gate 6048; the first gate 6041 is connected to the storage node 603, the source 6045 is connected to the replacement read bit line of the ferroelectric memory cell in series through the electric fuse material, the drain 6046 is connected to the ground line of the ferroelectric memory cell in series, and the second gate 6048 is connected to the replacement read word line of the ferroelectric memory cell in series through the electric fuse material.

[0097] The insulating filling medium 601 fills the above structure and sufficiently covers the exposed surface of the above structure.

[0098] The insulating dielectric layer wraps the above structure, sufficiently fills the exposed surface of the above structure, and separates the second part from the first part.

[0099] ​The ferroelectric 2T0C-DRAM memory cell matrix, replacement write word line group, replacement read word line group, replacement write bit line group, replacement read bit line group, and ground line group described herein do not imply mandatory requirements on the type, structure, and arrangement of memory cells and the type, quantity, and arrangement of corresponding lines. In some embodiments, the memory cells used by the memory array layer may also be other volatile memory cells, and correspond to different types, quantities, and connection methods of lines, including but not limited to: such as Figure 7-1 As shown, a ferroelectric 1T0C-DRAM (1 transistor-0 capacitor-DRAM, ferroelectric single-transistor capacitor-free DRAM) memory cell; as Figure 7-2 As shown, a ferroelectric non-dual-gate 2T0C-DRAM memory cell; as Figure 7-3 As shown, a ferroelectric 3T0C-DRAM (3-transistors-0-capacitor-DRAM, ferroelectric three-transistor capacitor-free DRAM) memory cell; as Figure 7-4 As shown, ferroelectric 4TOC-DRAM (3 transistors-0 capacitor-DRAM, ferroelectric four-transistor capacitor-free DRAM) memory cells, etc.; however, in order for the normal operation of the following damaged cell handling operation, in the ferroelectric 2TOC-DRAM spare memory array layer, except that the memory device structure uses a ferroelectric layer, the selected ferroelectric memory cell type and the type and relative spatial position of each device in the ferroelectric memory cell must be the same as the memory cell used in the first part.

[0100] Preferably, the spatial relationship between the second part and the first part can be as follows: In the second part, the write transistors in each ferroelectric 2TOC-DRAM memory cell of the ferroelectric 2TOC-DRAM spare memory array layer coincide sequentially with the write transistors in each 2TOC-DRAM memory cell of the three-layer 2TOC-DRAM memory array layer in a horizontal projection; the ferroelectric dual-gate read transistors in each ferroelectric 2TOC-DRAM memory cell of the ferroelectric 2TOC-DRAM spare memory array layer coincide with the write transistors in each 2TOC-DRAM memory cell of the three-layer 2TOC-DRAM memory array layer in a horizontal projection. The dual-gate read transistors in the memory cell are sequentially located at the same position on the horizontal projection; in the second part, the replacement write word line group and replacement write bit line group in the ferroelectric 2T0C-DRAM spare memory array layer coincide with the horizontal projection of the write word line group and write bit line group of the three-layer 2T0C-DRAM memory array layer in the first part; in the second part, the replacement read word line group, replacement read bit line group and ground line group in the ferroelectric 2T0C-DRAM spare memory array layer coincide with the horizontal projection of the read word line group, read bit line group and ground line group of the three-layer 2T0C-DRAM memory array layer in the first part.

[0101] The spatial relationship of the two parts described herein does not represent a mandatory requirement for the spatial relationship of the two parts. In actual operation, the spatial relationship between the ferroelectric 2T0C-DRAM backup storage array layer and the 2T0C-DRAM storage array layer needs to be designed by itself according to the type of storage unit used by the storage chip, design requirements, manufacturing process, test results and other factors.

[0102] As shown in Figure 1 , the backup unit replacement wire array 105 includes X*Y backup unit replacement wire groups 1051; wherein X is the number of columns of 2T0C-DRAM storage units in the 2T0C-DRAM storage unit matrix 101, and Y is the number of rows of 2T0C-DRAM storage units in the 2T0C-DRAM storage unit matrix 101.

[0103] As shown in Figure 8 , the backup unit replacement wire group includes one replacement write word line 801, one replacement read word line 802, one replacement write bit line 803, and one replacement read bit line 804.

[0104] Preferably, the connection mode of the backup unit replacement wire group with the three 2T0C-DRAM storage units 811-813 in the first part and the ferroelectric 2T0C-DRAM storage unit 814 in the second part located in the same position in the horizontal projection is as shown in Figure 8 .

[0105] The replacement write word line 801 is perpendicular to the plane where the first part and the second part are located, and is connected in series with the corresponding three 2T0C-DRAM storage units 811-813 and one ferroelectric 2T0C-DRAM storage unit 814; the specific connection mode is that the replacement write word line 801 is connected with each write word line where the three 2T0C-DRAM storage units 811-813 are located through anti-fuse material at the gate position of the write transistor of the three 2T0C-DRAM storage units 811-813, and the anti-fuse material and the above-mentioned electrical fuse material are respectively located on both sides of the write word line and do not directly contact, that is, the gate and the replacement write word line do not directly contact; the replacement write word line 801 is connected with the gate of the write transistor of the ferroelectric 2T0C-DRAM storage unit 814 through anti-fuse material, and the anti-fuse material does not directly contact with the above-mentioned electrical fuse material.

[0106] The replacement read word line 802 is perpendicular to the plane where the first part and the second part are located, and is connected in series with the corresponding three 2T0C-DRAM memory cells 811-813 and one ferroelectric 2T0C-DRAM memory cell 814; the specific connection mode is that the replacement write word line 801 is connected with each read word line where the three 2T0C-DRAM memory cells 811-813 are located through anti-fuse material at the second gate position of the double-gate read transistor of the three 2T0C-DRAM memory cells 811-813, and the anti-fuse material and the above-mentioned electrical fuse material are respectively located on both sides of the read word line and do not directly contact, that is, the second gate and the replacement read word line do not directly contact; the replacement read word line 802 is connected with the second gate of the ferroelectric double-gate read transistor of the ferroelectric 2T0C-DRAM memory cell 814 through anti-fuse material, and the anti-fuse material does not directly contact with the above-mentioned electrical fuse material.

[0107] The replacement write bit line 803 is perpendicular to the plane where the first part and the second part are located, and is connected in series with the corresponding three 2T0C-DRAM memory cells 811-813 and one ferroelectric 2T0C-DRAM memory cell 814; the specific connection mode is that the replacement write bit line 803 is connected with each write bit line where the three 2T0C-DRAM memory cells 811-813 are located through anti-fuse material at the source position of the write transistor of the three 2T0C-DRAM memory cells 811-813, and the anti-fuse material and the above-mentioned electrical fuse material are respectively located on both sides of the write bit line and do not directly contact; the replacement write bit line 803 is connected with the source of the write transistor of the ferroelectric 2T0C-DRAM memory cell 814 through anti-fuse material, and the anti-fuse material does not directly contact with the above-mentioned electrical fuse material.

[0108] The replacement read bit line 804 is perpendicular to the plane where the first part and the second part are located, and is connected in series with the corresponding three 2T0C-DRAM memory cells 811-813 and one ferroelectric 2T0C-DRAM memory cell 814; the specific connection mode is that the replacement read bit line 804 is connected with each read bit line where the three 2T0C-DRAM memory cells 811-813 are located through anti-fuse material at the source position of the double-gate read transistor of the three 2T0C-DRAM memory cells 811-813, and the anti-fuse material and the above-mentioned electrical fuse material are respectively located on both sides of the read bit line and do not directly contact; the replacement read bit line 804 is connected with the source of the ferroelectric double-gate read transistor of the ferroelectric 2T0C-DRAM memory cell 814 through anti-fuse material, and the anti-fuse material does not directly contact with the above-mentioned electrical fuse material.

[0109] The antifuse material is a special kind of insulating material, which is characterized in that when a high voltage is applied across the material, a high current passing through the material will break down the material, causing the material to change from non-conductive to conductive.

[0110] The arrangement and connection of the cell replacement wire group described herein do not represent a mandatory requirement for the arrangement of the cell replacement wire group and the connection with the storage cell array layer. In actual applications, the cell replacement wire group needs to be designed by itself according to the type of storage cell, the size of the storage array, and other factors.

[0111] The present application only provides the main structure of the storage array embodiment, and does not include the use of materials, other additional structures, and subsequent packaging steps; in actual production, other structures and packaging can be designed by themselves according to the specific circumstances of function, technology, cost, etc.

[0112] As shown in Figure 9 Based on the above-mentioned three-dimensional 2T0C-DRAM storage array, the present application proposes a damaged cell replacement method for a three-dimensional 2T0C-DRAM storage array, which specifically includes:

[0113] S1. When the DRAM chip is in a working state, perform a global data write and read operation on the three-layer 2T0C-DRAM storage array layer once every four hours of working time, accompanied by an array refresh operation of the DRAM chip, to periodically detect the state of all 2T0C-DRAM storage cells in the 2T0C-DRAM storage array layer.

[0114] The DRAM chip is the upper layer architecture of the three-dimensional 2T0C-DRAM storage array proposed in the present application, and has complete DRAM functions. The array refresh operation is one of the necessary operations of the DRAM chip, which is a write operation on all DRAM storage arrays in the chip with the original saved data in the DRAM chip, to refresh the saved state of all DRAM storage cells and maintain the storage of the data in the storage cells.

[0115] The array refresh operation will have different operation strategies according to different DRAM chip types, such as setting different refresh speeds and refresh timing, but will not affect the global read and write operation of a single storage array. The DRAM storage space is divided into multiple arrays, and the refresh timing is the smallest unit of a single array, so the refresh in the three-dimensional 2T0C-DRAM storage array proposed in the present application must be performed according to the same timing.

[0116] S2. Compare the data written and read out of each 2T0C-DRAM storage cell in S2, and determine whether each 2T0C-DRAM storage cell is damaged based on the comparison.

[0117] All possible write and read results are divided into four cases, in which:

[0118] The first, the data written in the 2T0C-DRAM memory cell is 1, and the data read is 1;

[0119] The second, the data written in the 2T0C-DRAM memory cell is 1, and the data read is 0;

[0120] The third, the data written in the 2T0C-DRAM memory cell is 0, and the data read is 0;

[0121] The fourth, the data written in the 2T0C-DRAM memory cell is 0, and the data read is 1.

[0122] If the 2T0C-DRAM memory cell is damaged during operation, there are three possible reasons: first, the channel layer of the write transistor is broken down, causing the write transistor to fail to normally implement the behavior of controlling charge storage or dissipation, that is, the data cannot be stored in the double-gate read transistor; second, the channel layer of the double-gate read transistor is broken down, causing the double-gate read transistor to fail to normally perform the data read operation; third, the word line or bit line that controls the write and read of the memory cell is damaged, causing the memory cell to fail to receive data. The damage results of the 2T0C-DRAM memory cell caused by the three reasons are that the double-gate read transistor cannot read data in the read operation, that is, the data read is 0. Here, according to the data marking method commonly used by all DRAMs on the market, 1 corresponds to high voltage and 0 corresponds to low voltage, so the default cannot read data / cannot read voltage is read as 0. Due to the above reasons, according to the four cases of all possible write and read results, the following judgments can be made for whether the 2T0C-DRAM memory cell is damaged, in which:

[0123] The first, the data written and read in the 2T0C-DRAM memory cell are the same and both are 1, proving that the memory cell is not damaged;

[0124] The second, the data written and read in the 2T0C-DRAM memory cell are different, proving that the memory cell is damaged;

[0125] The third, under the premise that the written data is 0, whether the 2T0C-DRAM memory cell is damaged or not, the data read will be 0, so it is impossible to judge whether the 2T0C-DRAM memory cell is damaged or not, but since the data written and read in the 2T0C-DRAM memory cell are the same, it is temporarily considered that the memory cell is not damaged;

[0126] The fourth, on the premise that the written data is 0, the read data will be 0 regardless of whether the 2T0C-DRAM memory cell is damaged, so there is no such case.

[0127] The determination method of whether the 2T0C-DRAM memory cell is damaged in this step is also applicable to other DRAM memory cells.

[0128] S3. Mark the address of all damaged 2T0C-DRAM memory cells, and compare it with the lookup table in the code program responsible for recording the address of the ferroelectric 2T0C-DRAM backup storage array containing the code program to determine whether the address of the ferroelectric 2T0C-DRAM backup storage cell located directly above the cell has been replaced. If so, do not perform the following damaged cell replacement operation, but perform the existing faulty cell processing operation of other DRAM chips; otherwise, perform the damaged cell replacement operation S4.

[0129] S4. Apply high voltage to the write word line, read word line, write bit line and read bit line connected to the damaged 2T0C-DRAM memory cell; at the same time, turn on the write word line, read word line, write bit line and read bit line connected to the ferroelectric 2T0C-DRAM backup memory cell located directly above the damaged 2T0C-DRAM memory cell. Here, it is not necessary to apply voltage to the write word line, read word line, write bit line and read bit line connected to the ferroelectric 2T0C-DRAM memory cell located directly above the damaged 2T0C-DRAM memory cell. Because of the existence of the backup replacement wire group, the word line and bit line connected to the damaged 2T0C-DRAM memory cell pass through the backup replacement wire group and the word line and bit line connected to the ferroelectric 2T0C-DRAM memory cell located directly above the damaged 2T0C-DRAM memory cell one by one and form an electric circuit, so that the replacement write word line, replacement read word line, replacement write bit line and replacement read bit line connected to the damaged 2T0C-DRAM memory cell and the corresponding ferroelectric 2T0C-DRAM memory cell all pass through high current, and the corresponding 2T0C-DRAM memory cells located in other 2T0C-DRAM memory array layers do not pass through current.

[0130] Under the above operation, the damaged 2T0C-DRAM memory cell and the electrical fuse material between the write transistor gate, the second gate of the dual-gate read transistor, the write transistor source, the source of the dual-gate read transistor of the damaged 2T0C-DRAM memory cell and the corresponding connection of the write word line, the read word line, the write bit line and the read bit line, and the ferroelectric 2T0C-DRAM backup memory cell located directly above the damaged 2T0C-DRAM memory cell and the electrical fuse material between the write transistor gate, the second gate of the ferroelectric dual-gate read transistor, the write transistor source, the source of the ferroelectric dual-gate read transistor of the ferroelectric 2T0C-DRAM backup memory cell and the corresponding connection of the write word line, the read word line, the write bit line and the read bit line are all fused. At the same time, the anti-fuse material between the replacement write word line, the replacement read word line, the replacement write bit line, the replacement read bit line and the write word line, the read word line, the write bit line and the read bit line connected with the replacement line, and the anti-fuse material between the replacement write word line, the replacement read word line, the replacement write bit line, the replacement read bit line and the write transistor gate, the second gate of the ferroelectric dual-gate read transistor, the write transistor source, the source of the ferroelectric dual-gate read transistor of the ferroelectric 2T0C-DRAM backup memory cell connected with the replacement line are all turned on. Thus, the damaged 2T0C-DRAM memory cell and the corresponding ferroelectric 2T0C-DRAM memory cell and the write word line, the read word line, the write bit line and the read bit line connected with them are all disconnected, and the replacement write word line, the replacement read word line, the replacement write bit line and the replacement read bit line connected with them are all turned on.

[0131] At this time, the damaged 2T0C-DRAM memory cell is isolated from the 2T0C-DRAM memory array it belongs to; and the ferroelectric 2T0C-DRAM backup memory cell directly above it is also isolated from the ferroelectric 2T0C-DRAM backup memory array it belongs to, and then is accessed to the corresponding position of the damaged 2T0C-DRAM memory cell in the 2T0C-DRAM memory array. Thus, the ferroelectric 2T0C-DRAM backup memory array covers and replaces the damaged 2T0C-DRAM memory cell, and the cell replacement operation is completed.

[0132] S5. Mark the address of the ferroelectric 2T0C-DRAM memory cell replacing the damaged 2T0C-DRAM memory cell generated in step S4 as having been replaced. The purpose of this step is to avoid the disorder of the 2T0C-DRAM memory array caused by the continuous execution of step S4 when the 2T0C-DRAM memory cell in other layers corresponding to the ferroelectric 2T0C-DRAM memory cell is damaged.

[0133] Through steps S1-S5, the processing mode of the 2T0C-DRAM storage unit damage problem generated in the working process of the 2T0C-DRAM storage array can be effectively supplemented; and since the electrical stability of the electric fuse material and the anti-fuse material is lower than that of the general conductor and insulator material, and the cycle endurance of the ferroelectric 2T0C-DRAM storage unit is lower than that of the general DRAM, it is necessary to avoid step S4 from being implemented too much, otherwise it will cause the local stability of the 2T0C-DRAM storage array to be reduced. Therefore, in combination with the cycle endurance of the ferroelectric 2T0C-DRAM storage unit and the average failure time of the 2T0C-DRAM storage unit, the three-dimensional 2T0C-DRAM storage array proposed in the present application selects to contain three layers of 2T0C-DRAM storage array layers, that is, each ferroelectric 2T0C-DRAM standby storage unit undertakes the fault replacement work of the corresponding three 2T0C-DRAM storage units, which can better balance the damage unit replacement effect of the three-dimensional 2T0C-DRAM storage array and the utilization rate of the ferroelectric 2T0C-DRAM standby storage array.

[0134] Since the entire storage array region contains many individual 2T0C-DRAM arrays, the ferroelectric 2T0C-DRAM arrays located at the edge part of the 2T0C-DRAM storage region are generally used for storing programs. At the same time, the three-dimensional 2T0C-DRAM storage array proposed in the present application selects to contain three layers of 2T0C-DRAM storage array layers is also based on this consideration, that is, it is set in combination with the cycle endurance of the ferroelectric 2T0C-DRAM storage unit and the average failure time of the 2T0C-DRAM storage unit.

[0135] It can be understood that the detailed function implementation of each unit / module described above can refer to the description in the foregoing method embodiments, which will not be repeated here.

[0136] It should be understood that the above device is used to execute the method in the above embodiments, and the corresponding program modules in the device have similar implementation principles and technical effects to those described in the above method. The working process of the device can refer to the corresponding process in the above method, which will not be repeated here.

[0137] Based on the method in the above embodiments, the present embodiment provides an electronic device, which can include a processor, a communications interface, a memory, and a communications bus, wherein the processor, the communications interface, and the memory complete mutual communication through the communications bus. The processor can invoke the logical instructions in the memory to execute the method in the above embodiments.

[0138] In addition, the logic instructions in the above-mentioned memory can be implemented in the form of a software function unit and sold or used as an independent product, and can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, and the computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application.

[0139] Based on the method in the above-mentioned embodiments, the embodiments of the present application provide a computer readable storage medium, which stores a computer program, and when the computer program runs on a processor, the processor executes the method in the above-mentioned embodiments.

[0140] Based on the method in the above-mentioned embodiments, the embodiments of the present application provide a computer program product, and when the computer program product runs on a processor, the processor executes the method in the above-mentioned embodiments.

[0141] It can be understood that the processor in the embodiments of the present application can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor.

[0142] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, which can be stored in a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable read-only memory (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), a register, a hard disk, a mobile hard disk, a CD-ROM, or any other form of storage medium well known in the art. An exemplary storage medium is coupled to a processor, so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and the storage medium can be located in an ASIC.

[0143] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware, or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in or transmitted by a computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center through a wired (such as a coaxial cable, an optical fiber, a digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) manner. The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media sets. The available media can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0144] It can be understood that the various numerical numbers involved in the embodiments of the present application are only used for differentiation for convenience of description, and do not limit the scope of the embodiments of the present application.

[0145] Those skilled in the art can easily understand that the above description is only the preferred embodiment of the present application, and is not used to limit the present application, and any modification, equivalent replacement and improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A three-dimensional 2T0C-DRAM memory array, characterized in that, include: Vertically stacked 2T0C-DRAM memory array; A 2T0C-DRAM spare memory array stacked above or below the 2T0C-DRAM memory array is used to replace faulty 2T0C-DRAM memory cells in the 2T0C-DRAM memory array.

2. The three-dimensional 2TOC-DRAM memory array as described in claim 1, characterized in that, The structure of the 2T0C-DRAM spare memory array is the same as that of each layer in a vertically stacked 2T0C-DRAM memory array.

3. The three-dimensional 2TOC-DRAM memory array as described in claim 2, characterized in that, The 2T0C-DRAM spare storage array is a single-layer ferroelectric 2T0C-DRAM spare storage array.

4. The three-dimensional 2TOC-DRAM memory array as described in claim 2, characterized in that, The vertically stacked 2T0C-DRAM memory array is a three-layer 2T0C-DRAM memory array.

5. The three-dimensional 2TOC-DRAM memory array as described in claim 1, characterized in that, In the 2T0C-DRAM memory array, each write word line, each read word line, each write bit line, and each read bit line is connected to the corresponding pin of the corresponding transistor in the corresponding 2T0C-DRAM memory cell via an electric fuse. In the ferroelectric 2T0C-DRAM spare storage array, each write word line, each read word line, each write bit line, and each read bit line is connected to the corresponding pin of the corresponding transistor of the corresponding ferroelectric 2T0C-DRAM storage cell through an electric fuse. Each of the replacement write word lines, replacement read word lines, replacement write bit lines, and replacement read bit lines is connected to the corresponding write word lines, read word lines, write bit lines, and read bit lines in the 2T0C-DRAM memory array and the corresponding pins of the corresponding transistors in the corresponding ferroelectric 2T0C-DRAM memory cells via anti-fuse. Each of the replacement write word lines, replacement read word lines, replacement write bit lines, and replacement read bit lines is perpendicular to the horizontal plane of each layer of 2T0C-DRAM memory array and the ferroelectric 2T0C-DRAM spare memory array.

6. A method for replacing damaged cells in a three-dimensional 2TOC-DRAM memory array as described in any one of claims 1 to 5, characterized in that, include: Periodically check the status of all 2T0C-DRAM memory cells in each layer of the 2T0C-DRAM memory array; Compare the data written / read out of each 2T0C-DRAM memory cell during the global read / write process to determine whether the 2T0C-DRAM memory cell has been faulted or damaged. Mark the addresses of all damaged 2T0C-DRAM memory cells; Perform a damaged cell replacement operation on the damaged 2T0C-DRAM memory cell.

7. The method as described in claim 6, characterized in that, The determination of whether the 2T0C-DRAM memory cell is faulty or damaged is divided into three situations: The first scenario is that the data written to the 2T0C-DRAM memory cell is 1, and the data read out is 1. Since the data written and read are the same, it proves that the memory cell is not damaged. The second scenario is that the data written to the 2T0C-DRAM memory cell is 1, and the data read out is 0. The difference between the written and read data proves that the memory cell is damaged. The third scenario is that the data written to the 2T0C-DRAM memory cell is 0, and the data read out is 0. It cannot be determined whether the memory cell is damaged, but since the data written and read out are the same, it is considered that the memory cell is not damaged.

8. The method as described in claim 6, characterized in that, The process of replacing the damaged 2T0C-DRAM memory cell is as follows: Disconnect the damaged 2T0C-DRAM memory cell and the corresponding 2T0C-DRAM spare memory cell, as well as the write word line, read word line, write bit line and read bit line connected to them respectively, and connect the replacement write word line, replacement read word line, replacement write bit line and replacement read bit line connected to them respectively. The address of the 2T0C-DRAM spare memory cell that replaces the damaged 2T0C-DRAM memory cell generated during the damaged cell processing operation is marked as having been replaced.

9. The method as described in claim 8, characterized in that, A high voltage is applied to the write word lines, read word lines, write bit lines, and read bit lines connected to the damaged 2T0C-DRAM memory cell. Simultaneously, the write word lines, read word lines, write bit lines, and read bit lines connected to the ferroelectric 2T0C-DRAM backup memory cell corresponding to the damaged 2T0C-DRAM memory cell are connected. This causes the fuses at the connection points between the damaged 2T0C-DRAM memory cell and the connected write word lines, read word lines, write bit lines, and read bit lines, as well as the fuses at the connection points between the corresponding ferroelectric 2T0C-DRAM backup memory cell and the connected write word lines, read word lines, write bit lines, and read bit lines, to all melt. At the same time, the antifuses at the connection points between the write word lines, read word lines, write bit lines, and read bit lines connected to the damaged 2T0C-DRAM memory cell, and the antifuses at the connection points between each pin of the transistor in the corresponding ferroelectric 2T0C-DRAM backup memory cell and the connected replacement write word lines, replacement read word lines, replacement write bit lines, and replacement read bit lines, are all connected.

10. A memory, characterized in that, Includes the three-dimensional 2TOC-DRAM memory array as described in any one of claims 1 to 5.

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