Memory, operating method thereof, memory system, and electronic device

Abstract

The embodiment of the invention discloses a memory and an operation method thereof, a memory system and electronic equipment, and the memory comprises a memory unit array which comprises a main array and a redundant array; wherein the main array comprises a plurality of memory blocks, and each memory block is coupled with a plurality of bit lines; the redundant array is coupled with a plurality of redundant bit lines, and a repair bit line in the plurality of redundant bit lines is configured to repair a fault bit line in the plurality of bit lines; a peripheral circuit coupled to the memory cell array through a plurality of bit lines and a plurality of redundant bit lines; wherein the peripheral circuit is configured to: determine state information of a target memory block among the plurality of memory blocks; storing the state information of the target storage block into a redundant storage unit coupled with an idle bit line in the plurality of redundant bit lines; wherein the idle bit line and the repair bit line are different redundant bit lines.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and includes, but is not limited to, a memory and its operating method, a memory system, and an electronic device. Background Technology

[0002] A memory controller and one or more memories can be integrated into various types of storage devices, such as solid-state drives (SSDs), universal flash storage (UFS), and embedded multi-media cards (eMMC). The memory controller can control the operation of the memory, such as read, write, or erase operations.

[0003] The memory controller manages and maintains information about memory usage. However, as storage capacity increases, the information that needs to be managed and maintained becomes more complex, increasing the difficulty of maintenance and making it prone to data loss. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a memory is provided, comprising:

[0005] A storage cell array, comprising a primary array and a redundant array; wherein the primary array comprises multiple storage blocks, each storage block being coupled to multiple bit lines; the redundant array is coupled to multiple redundant bit lines, wherein repair bit lines among the multiple redundant bit lines are configured to repair faulty bit lines among the multiple bit lines; peripheral circuitry, coupled to the storage cell array via the multiple bit lines and the multiple redundant bit lines; wherein the peripheral circuitry is configured to:

[0006] Determine the status information of the target storage block among the plurality of storage blocks;

[0007] The status information of the target storage block is stored in a redundant storage cell coupled to an idle bit line among the multiple redundant bit lines; wherein the idle bit line and the repair bit line are different redundant bit lines.

[0008] In some embodiments, the peripheral circuitry is further configured to: determine at least one of the plurality of redundant bit lines as an idle bit line; allocate the at least one idle bit line to at least one of the memory blocks; wherein the redundant memory cell coupled to the idle bit line allocated to the memory block is used to store the status information of the memory block.

[0009] In some embodiments, the peripheral circuitry includes:

[0010] A register circuit configured to register the address of the free bit line;

[0011] A control logic circuit coupled to the register circuit; wherein the control logic circuit is configured to: obtain the free bit line address from the register circuit; and allocate the free bit line address to at least one of the memory blocks.

[0012] In some embodiments, the peripheral circuit is specifically configured to: determine the free bit line allocated to the target memory block based on the free bit line address allocated to the target memory block, and write the status information of the target memory block into the redundant memory cell coupled to the free bit line.

[0013] In some embodiments, the plurality of memory blocks include a configuration block configured to store the free bit line address; the peripheral circuitry is further configured to load the free bit line address into the register circuitry upon power-up of the memory.

[0014] In some embodiments, the peripheral circuitry is specifically configured to determine the status information based on at least one operation command for the target memory block.

[0015] In some embodiments, the peripheral circuit is specifically configured to: determine whether the operation command has been successfully executed; and based on the successful execution of the operation command, increase the status information of the target storage block from a first count value to a second count value.

[0016] In some embodiments, the peripheral circuit is specifically configured to: clear the status information of the target storage block stored in the redundant storage unit based on the failure of the operation command execution.

[0017] In some embodiments, the peripheral circuit is further configured to: acquire the status information of the memory blocks adjacent to the target memory block based on the power-on after the memory has failed an abnormal power loss; and redetermine the status information of the target memory block based on the status information of the adjacent memory blocks.

[0018] In some embodiments, the status information includes the number of erase / write cycles of the storage block.

[0019] According to a second aspect of the present disclosure, a method for operating a memory is provided, the method comprising:

[0020] Determine the state information of a target memory block among multiple memory blocks; wherein each memory block is coupled to multiple bit lines;

[0021] The status information of the target storage block is stored in a redundant storage cell coupled to an idle bit line among multiple redundant bit lines; wherein, the multiple redundant bit lines include the idle bit line and the repair bit line, the repair bit line is used to repair the faulty bit line among the multiple bit lines, and the idle bit line and the repair bit line are different redundant bit lines.

[0022] In some embodiments, the operation method further includes: determining at least one of the plurality of redundant bit lines as an idle bit line; allocating the at least one idle bit line to at least one of the storage blocks; wherein the redundant storage cell coupled to the idle bit line allocated to the storage block is used to store the status information of the storage block.

[0023] In some embodiments, determining at least one of the multiple redundant bit lines as an idle bit line includes: obtaining the idle bit line address of the idle bit line;

[0024] The step of allocating at least one of the free bit lines to at least one of the storage blocks includes: allocating the free bit line address to at least one of the storage blocks.

[0025] In some embodiments, storing the status information of the target storage block into a redundant storage unit coupled to a free bit line among multiple redundant bit lines includes: determining the free bit line allocated to the target storage block based on the free bit line address allocated to the target storage block, and writing the status information of the target storage block into the redundant storage unit coupled to the free bit line.

[0026] In some embodiments, determining the state information of a target storage block among a plurality of storage blocks includes:

[0027] The status information is determined based on at least one operation command targeting the target storage block.

[0028] In some embodiments, determining the status information based on at least one operation command for the target storage block includes: determining whether the operation command was successfully executed; and incrementing the status information of the target storage block from a first count value to a second count value based on the successful execution of the operation command.

[0029] In some embodiments, determining the status information based on at least one operation command for the target storage block includes: clearing the status information of the target storage block stored in the redundant storage unit based on the failure of the operation command execution.

[0030] In some embodiments, the operation method further includes: acquiring the status information of the memory blocks adjacent to the target memory block based on the power-on after the memory has abnormally lost power; and redetermining the status information of the target memory block based on the status information of the adjacent memory blocks.

[0031] According to a third aspect of the present disclosure, a memory system is provided, comprising:

[0032] One or more memories as described in any of the embodiments of the first aspect of this disclosure;

[0033] A memory controller, coupled to the memory and configured to control the memory.

[0034] According to a fourth aspect of the present disclosure, an electronic device is provided, comprising: a memory system as described in a third aspect of the present disclosure.

[0035] In this embodiment, the peripheral circuitry can determine the status information of the target memory block based on its usage, and then store the status information of the target memory block in redundant memory cells coupled to idle bit lines. Firstly, the memory itself can manage and maintain the relevant information, eliminating the need for a memory controller. This not only reduces maintenance difficulty and cost but also ensures that the information is retained even after power loss and is less prone to loss. Secondly, idle repair resources (i.e., idle bit lines and redundant memory cells coupled to idle bit lines) can be utilized without increasing the memory's area or power consumption. Thirdly, the status information of a single memory block can be managed and maintained. Attached Figure Description

[0036] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0037] Figure 1 This is a schematic diagram of an electronic device according to an embodiment of the present disclosure.

[0038] Figure 2a This is a schematic diagram of a memory card according to an embodiment of the present disclosure.

[0039] Figure 2b This is a schematic diagram of a solid-state drive according to an embodiment of the present disclosure.

[0040] Figure 3 This is a schematic block diagram of a three-dimensional NAND memory according to an embodiment of the present disclosure.

[0041] Figure 4 This is a schematic cross-sectional view of a memory according to an embodiment of the present disclosure.

[0042] Figure 5 This is a schematic diagram of a memory including a memory cell array and peripheral circuitry according to an embodiment of the present disclosure.

[0043] Figure 6 This is a schematic block diagram of a memory according to an embodiment of the present disclosure.

[0044] Figure 7 This is a schematic diagram illustrating a redundant bit line and a redundant bit line address according to an embodiment of the present disclosure.

[0045] Figure 8 This is a flowchart illustrating a method of operating a memory according to an embodiment of the present disclosure.

[0046] Figure 9 This is a schematic diagram illustrating the operation process of a memory according to an embodiment of the present disclosure.

[0047] Figure 10 This is a schematic diagram of a memory interface according to an embodiment of the present disclosure. Detailed Implementation

[0048] To facilitate understanding of this disclosure, exemplary embodiments of the disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the disclosure are shown in the drawings, it should be understood that the disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the disclosure and to fully convey the scope of the disclosure to those skilled in the art.

[0049] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with this disclosure, certain technical features well-known in the art are not described; that is, not all features of the actual embodiments, nor well-known functions and structures, may be described herein.

[0050] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the use of "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0051] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit the scope of this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0052] To fully understand this disclosure, detailed steps and structures will be set forth in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0053] Figure 1 This is a schematic diagram illustrating an electronic device 100 according to an embodiment of the present disclosure. The electronic device 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a memory device therein. See also... Figure 1As shown, the electronic device 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor of the electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory 104.

[0054] According to some embodiments, memory controller 106 is coupled to memory 104 and host 108 and is configured to control memory 104. Memory controller 106 can manage data stored in memory 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as Solid State Disk (SSD) or embedded Multi-Media Card (eMMC), and SSDs or eMMCs are used as data storage in mobile devices such as smartphones, tablets, laptops, and enterprise storage arrays.

[0055] The memory controller 106 can be configured to control the operation of the memory 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions related to data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECCs) regarding data read from or written to the memory 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 can communicate with external devices (e.g., according to specific communication protocols) Figure 1The memory controller 106 communicates with the host device 108. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Development Equipment (IDE), FireWire, etc.

[0056] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2a In one example shown, the memory controller 106 and a single memory 104 can be integrated into the memory card 202. The memory card 202 can include a PC card (Personal Computer Memory Card), CF card, SmartMedia (SM) card, memory stick, Multimedia Card (MMC, RS-MMC (Reduced-Size MMC), MMCmicro), SD card (SD, miniSD, microSD, SDHC (Reduced-Size MMC)), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memories 104 can be integrated into the SSD 206. The SSD 206 may also include components for connecting the SSD 206 to a host computer (e.g., ...). Figure 1The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0057] Figure 3 This is a schematic block diagram illustrating a three-dimensional NAND memory 300 according to an embodiment of the present disclosure. The memory 300 may be... Figure 1 An example of memory 104 is provided. Memory 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 is illustrated as a three-dimensional NAND memory cell array, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0058] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal memory values. In one example, if each MLC stores two bits of data, the MLC can be programmed to write one of three possible nominal memory values ​​into the cell, while a fourth nominal memory value in addition to these three nominal memory values ​​can be used to indicate an erase state.

[0059] like Figure 3As shown, each NAND memory string 308 may include a bottom select gate (BSG) 310 at its source end and a top select gate (TSG) 312 at its drain end. The BSG 310 and TSG 312 may be configured to activate the selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0060] like Figure 3As shown, NAND memory strings 308 can be organized into multiple memory blocks 304, each of which may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) biased and coupled to the source line of unselected memory blocks on the same plane as the selected memory block can be used. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some implementations, memory cells 306 coupled to the same word line 318 in memory block 304 may constitute at least one physical page. Each word line 318 may include a plurality of control gates (gate electrodes) at each memory cell 306 of the corresponding physical page and gate lines coupling the control gates.

[0061] Figure 4 This is a schematic cross-sectional view of a memory according to an embodiment of the present disclosure. (Refer to...) Figure 4 As shown, the NAND memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 stacked alternately in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 determines the number of memory cells included in the memory cell array 301.

[0062] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0063] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0064] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0065] Return to reference Figure 3 The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0066] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory cell array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a physical page of memory cell array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0067] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0068] Control logic 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bitline driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0069] NAND flash memory comprises multiple storage planes, each containing multiple storage blocks. The individual blocks may vary due to differences in manufacturing processes, leading to variations in their use by clients. Currently, there is no good solution for obtaining the state information of a storage block when a problem occurs during write / erase operations. This is because a power outage is required between the customer and the manufacturer, potentially resulting in the loss of state information, and subsequent successful reproduction is not guaranteed. Write / erase cycles are crucial information. Here, state information refers to information related to the internal usage of the memory, not just the number of write / erase cycles.

[0070] Write / erase cycles are a crucial indicator of NAND flash memory health and are essential for system applications. For example, different error correction strategies need to be implemented within different write / erase cycle ranges. Typically, write / erase cycles are counted and managed by the memory controller. However, as storage capacity increases and the number of chips to be managed grows, disk-level power-down management becomes increasingly difficult due to board area limitations. This makes the memory controller's management and maintenance of write / erase cycles more complex, further restricting the system's ability to write back relevant information upon power-down, leading to potential data loss. Furthermore, memory controllers generally only maintain the write / erase cycles of individual chips, lacking the resources to maintain the write / erase cycles of individual memory blocks within a chip.

[0071] Based on one or more of the above-mentioned technical problems, this disclosure provides a memory. Figure 6 This is a schematic block diagram illustrating a memory according to an embodiment of the present disclosure. (Refer to...) Figure 6As shown, the memory 600 includes a memory cell array 610, which includes a main array 611 and a redundant array 612. The main array 611 includes multiple memory blocks, each memory block being coupled to multiple bit lines BL; the redundant array 612 is coupled to multiple redundant bit lines RBL, and the repair bit lines in the multiple redundant bit lines RBL are configured to repair faulty bit lines in the multiple bit lines BL. Figure 6 The storage blocks 0, 1, and 2 shown are merely examples; the number of storage blocks in the main array 611 is not limited to these examples. Figure 6 As shown.

[0072] The main array 611 may include multiple storage cells, and the redundant array 612 may include multiple redundant storage cells. A redundant storage cell can be used to repair a faulty storage cell among the multiple storage cells. For example, if a storage cell in the main array 611 fails, that storage cell is considered a faulty storage cell, and a redundant storage cell can be used to replace it for writing or reading data, thereby repairing the faulty storage cell. It is understood that the bit line BL coupled to the faulty storage cell can be considered a faulty bit line, and the redundant bit line RBL coupled to the redundant storage cell replacing the faulty storage cell can be considered a repair bit line. Of course, in other embodiments, the bit line BL itself may also fail, and a repair bit line can be used to replace the faulty bit line, thereby repairing the faulty bit line, such as... Figure 6 As indicated by the dashed arrow. The number of faulty storage units can be one or more. If the number of faulty storage units is multiple and does not exceed the total number of all redundant storage units, a corresponding number of redundant storage units can be used for repair. This disclosure does not impose any special restrictions on this.

[0073] It should be noted that the redundant array 612 has a similar structure to the main array 611. For details on the structures of the main array 611 and the redundant array 612, please refer to [reference needed]. Figure 3 or Figure 4 Related examples. In practical applications, a portion of the wafer is reserved to fabricate a redundant array 612, typically on either side or around the main array 611. The redundant array 612 and the main array 611 can be fabricated using the same process; therefore, the redundant array 612 and the main array 611 have essentially the same structure.

[0074] The memory 600 also includes peripheral circuitry 620, which is coupled to the memory cell array 610 via multiple bit lines BL and multiple redundant bit lines RBL. Peripheral circuitry 620 is configured to: determine the status information of a target memory block among multiple memory blocks; and store the status information of the target memory block in redundant memory cells coupled to idle bit lines in the multiple redundant bit lines RBL. Here, the idle bit lines and the repair bit lines are different redundant bit lines RBL. The number of target memory blocks can be one or more. When there are multiple target memory blocks, the status information corresponding to different target memory blocks can be stored in different redundant memory cells coupled to idle bit lines, thereby avoiding errors in the status information corresponding to different target memory blocks.

[0075] In this embodiment, the peripheral circuit 620 can determine the status information of the target memory block based on its usage, and then store the status information of the target memory block in a redundant memory cell coupled to an idle bit line. The idle bit line can be an unused redundant bit line RBL among multiple redundant bit lines RBL. Thus, firstly, the memory itself can manage and maintain the relevant information without the need for a memory controller, which not only reduces maintenance difficulty and cost, but also ensures retention even after power loss and prevents data loss; secondly, idle repair resources can be utilized without increasing the memory's area and power consumption; and thirdly, it also enables the management and maintenance of the status information of a single memory block.

[0076] It should be noted that NAND flash memory has bad line repair capabilities. These repair resources are usually not fully utilized; idle repair resources (i.e., idle bit lines (BLs) and their coupled redundant memory cells) can be used to store the status information of the target memory block. In practical applications, the repair resources corresponding to chips from different manufacturers may vary, depending on the chip yield. For example, if the chip yield is good, the corresponding repair resources are fewer; conversely, if the chip yield is poor, the corresponding repair resources are more. In one specific embodiment, the repair resources corresponding to each memory plane are approximately 100 bytes.

[0077] In some embodiments, the peripheral circuit 620 is further configured to: determine at least one free bit line among a plurality of redundant bit lines RBL; allocate the at least one free bit line to at least one memory block; wherein the redundant memory cell coupled to the free bit line allocated to the memory block is used to store the state information of the memory block.

[0078] In this embodiment, the peripheral circuit 620 can determine the number of unused redundant bit lines (RBLs) among multiple redundant bit lines (RBLs), and then configure the memory based on these unused bit line resources. For example, it can allocate one or more unused bit lines to a target memory block, and then store the state information of the target memory block in the redundant memory cells coupled to the unused bit lines allocated to the target memory block. Furthermore, as the state information of the target memory block changes, the state information stored in the corresponding redundant memory cells also changes, thereby achieving the management and maintenance of the target memory block's state information.

[0079] In some embodiments, the peripheral circuit 620 includes a register circuit 622 and a control logic circuit 621 coupled to the register circuit 622. The register circuit 622 is configured to register the address of a free bit line; the control logic circuit 621 is configured to: obtain the address of a free bit line from the register circuit 622; and allocate the address of the free bit line to at least one memory block.

[0080] In this embodiment, the control logic circuit 621 can read the free bit line address registered in the register circuit 622 to determine the free bit line resource, and then allocate the free bit line address to the corresponding memory block, thereby configuring the free bit line resource. When storing the status information of the target memory block to the redundant memory cell coupled to the free bit line, the free bit line address allocated to the target memory block can be selected to drive the corresponding free bit line to perform a write operation, so as to write the status information of the target memory block to the redundant memory cell coupled to the free bit line.

[0081] It should be noted that during NAND factory testing, all bit lines (BLs) are typically scanned. If a bit line BL fails, it is replaced using multiple reserved redundant bit lines (RBLs). The address of the redundant RBL that replaced the faulty bit line (i.e., the repair bit line) is then recorded, and the address of the repair bit line is configured in the corresponding repair resource interface. This way, when an external (e.g., Figure 1 When the host (108) in the system sends an access command indicating that a faulty bit line should be accessed, the corresponding repair bit line can be accessed directly through the repair resource interface. This technique is also known as redundant column repair. The reserved multiple redundant bit lines (RBL) are usually not used up. Therefore, the control logic can record and save the addresses of unused redundant bit lines (i.e., free bit line addresses) in the multiple redundant bit lines (RBL).

[0082] Figure 7 This is a schematic diagram illustrating a redundant bit line and a redundant bit line address according to an embodiment of this disclosure. (Refer to...) Figure 7As shown, if a bit line BL fails during factory testing, the faulty bit line is replaced by the redundant bit line col cam[0], and the address of the redundant bit line col cam[0] is configured in the corresponding repair resource interface. When the host needs to access the faulty bit line, it selects the redundant bit line address of the redundant bit line col cam[0]. Therefore, the redundant bit line address of the redundant bit line col cam[0] is enabled. Other unused redundant bit lines col cam[1] to col cam

[12] can be used as idle bit lines. The control logic can record and save the idle bit line addresses corresponding to the idle bit lines col cam[1] to col cam

[12] . Figure 7 The addresses ca[0] to ca

[13] are shown in the figure. The control logic can also allocate the free bit line addresses ca[0] to ca

[13] to different storage blocks. By selecting different free bit line addresses, the management and maintenance of the status information of different storage blocks can be realized.

[0083] In some embodiments, the peripheral circuit 620 is specifically configured to: determine the free bit line allocated to the target memory block based on the free bit line address allocated to the target memory block, and write the status information of the target memory block into the redundant memory cell coupled to the free bit line.

[0084] For example, in combination Figure 6 and Figure 7 As shown, if the target storage block is storage block 0 and the address of the free bit line allocated to the target storage block is ca[0], the control logic circuit 621 determines that the free bit line allocated to storage block 0 is col cam[1] based on the free bit line address ca[0], thereby driving the free bit line col cam[1] to perform a write operation to write the status information of storage block 0 to the redundant storage unit coupled to the free bit line col cam[1]. Here, the target storage block being storage block 0 and the free bit line address being ca[0] is only an example. In other embodiments, the target storage block can also be other storage blocks, and the address of the free bit line allocated to storage block 0 can also be other free bit line addresses. This disclosure does not impose any special restrictions on this.

[0085] The specific process of writing the state information of memory block 0 to the redundant memory cell coupled to the free bit line col cam[1] may include: applying a bit line BL voltage (e.g., 0V) to the free bit line col cam[1] and applying a bit line BL disable voltage (e.g., VDD) to other bit lines; applying a programming voltage V to the selected word line. PGM And apply a pass voltage V to the unselected word line. Pass This allows the status information of storage block 0 to be written to the selected redundant storage unit.

[0086] In some embodiments, the multiple memory blocks include a configuration block configured to store free bit line addresses. The peripheral circuit 620 is further configured to load the free bit line addresses into the register circuit 622 upon power-up of the memory 600. The multiple memory blocks can be categorized according to usage, such as occupied blocks, free blocks, bad blocks, and configuration blocks. Occupied blocks represent memory blocks storing data, free blocks represent memory blocks without stored data, bad blocks represent memory blocks that cannot be used normally, and configuration blocks represent memory blocks storing configuration information. Therefore, the free bit line addresses can be stored in the configuration block and loaded into the fast-accessible register circuit 622 during the power-up initialization process of the memory 600, thus preventing the loss of free bit line addresses. Of course, in other embodiments, the free bit line addresses can be stored in other non-volatile memories 600 or circuits.

[0087] In some embodiments, the peripheral circuit 620 is specifically configured to determine status information based on at least one operation command for the target memory block. The peripheral circuit 620 can determine the status information of the target memory block based on the number of operation commands for the target memory block, where the operation commands include at least one of write commands, erase commands, or read commands. For example, the peripheral circuit 620 can determine the number of writes to the target memory block based on the number of write commands. Similarly, the peripheral circuit 620 can determine the number of erases to the target memory block based on the number of erase commands. Thus, the memory 600 itself can maintain the status information of individual memory blocks.

[0088] In some embodiments, the peripheral circuit 620 is specifically configured to: determine whether the operation command was successfully executed; based on the successful execution of the operation command, increment the status information of the target storage block from a first count value to a second count value; and based on the failure of the operation command, clear the status information of the target storage block stored in the redundant storage unit. Taking an erase command as an example, if the target storage block is successfully erased, the erase count of the target storage block is incremented by one based on the current erase count, and the incremented erase count is written back to the corresponding redundant storage unit. Conversely, if the target storage block is not erased, the status information of the target storage block stored in the redundant storage unit is cleared.

[0089] In this embodiment of the disclosure, the peripheral circuit 620 determines whether the operation command is successfully executed. If the operation command is successfully executed, the status information of the target storage block is increased from the first count value to the second count value, so as to update and maintain the status information of the target storage block in real time. Alternatively, if the operation command fails to execute, the status information of the target storage block stored in the redundant storage unit is cleared, so as to release the idle bit line resources for use by other storage blocks.

[0090] In some embodiments, the peripheral circuit 620 is further configured to: obtain the status information of the memory blocks adjacent to the target memory block based on the power-on after the memory 600 has failed an abnormal power failure; and redetermine the status information of the target memory block based on the status information of the adjacent memory blocks.

[0091] In this embodiment of the disclosure, if the memory 600 suddenly loses power while an operation command is being executed on the target memory block, the state information of the target memory block will be lost. One solution is to tolerate this loss. Another solution is to read the state information of the memory blocks adjacent to the target memory block and, based on the read state information of the adjacent memory blocks, to re-determine the state information of the target memory block. Typically, it is assumed that the erase / write history of adjacent memory blocks is relatively consistent. For example, if memory block 0 has been erased / written 99 times, the erase / write count of memory block 0 is stored in a redundant memory cell coupled to a free bit line. When memory block 1 is erased / written for the 100th time and suddenly loses power, the redundant memory cell storing the erase / write count of memory block 0 is read, the erase / write count of memory block 0 is determined to be 99 times, and the erase / write count of memory block 1 is considered to be equal to or close to 99 times. In this way, even if the memory 600 experiences an abnormal power outage, the loss of the state information of the memory block currently executing the operation command can be avoided.

[0092] In some embodiments, the status information includes the number of erase / write cycles for a storage block. Here, the number of erase / write cycles for a storage block includes the number of current erase cycles and the number of lifetime erase cycles. The current erase cycle count refers to the actual number of times the storage block is erased and written, while the lifetime erase cycle count refers to the upper limit of the allowed number of erase cycles for a storage block; that is, each storage block has a maximum allowed number of erase cycles. When the current erase cycle count of a storage block approaches or reaches the lifetime erase cycle count, writing data to that storage block can be stopped.

[0093] Based on the above-described memory, this disclosure provides a method for operating the memory. Figure 8 This is a flowchart illustrating a method for operating a memory according to an embodiment of the present disclosure. (Refer to...) Figure 8 As shown, this operation method includes at least the following steps:

[0094] Step S710: Determine the status information of the target memory block among multiple memory blocks; wherein, each memory block is coupled to multiple bit lines;

[0095] Step S720: Store the status information of the target storage block into a redundant storage cell coupled to an idle bit line among multiple redundant bit lines; wherein, the multiple redundant bit lines include idle bit lines and repair bit lines, the repair bit lines are used to repair faulty bit lines among the multiple bit lines, and the idle bit lines and repair bit lines are different redundant bit lines.

[0096] In some embodiments, the above-described operation method further includes: determining at least one free bit line among a plurality of redundant bit lines; allocating the at least one free bit line to at least one storage block; wherein the redundant storage cell coupled to the free bit line allocated to the storage block is used to store the state information of the storage block.

[0097] In some embodiments, determining at least one free bit line among multiple redundant bit lines includes: obtaining the free bit line address of the free bit line; allocating at least one free bit line to at least one storage block includes: allocating the free bit line address to at least one storage block.

[0098] In some embodiments, step S720 includes: determining the free bit line allocated to the target storage block based on the free bit line address allocated to the target storage block, and writing the status information of the target storage block into the redundant storage cell coupled to the free bit line.

[0099] In some embodiments, step S710 above includes: determining status information based on at least one operation command for the target storage block.

[0100] In some embodiments, determining the status information based on at least one operation command for the target storage block includes: determining whether the operation command was successfully executed; and incrementing the status information of the target storage block from a first count value to a second count value based on the successful execution of the operation command.

[0101] In some embodiments, determining the status information based on at least one operation command for the target storage block includes: clearing the status information of the target storage block stored in the redundant storage unit based on the failure of the operation command execution.

[0102] In some embodiments, the above operation method further includes: obtaining the status information of the memory blocks adjacent to the target memory block based on the power-on after an abnormal power failure of the memory; and redetermining the status information of the target memory block based on the status information of the adjacent memory blocks.

[0103] In this embodiment, the memory operation method can be executed by the control logic circuit in the memory of any of the foregoing embodiments. The technical effects achievable by the memory in the foregoing embodiments can also be achieved by this memory operation method, and will not be elaborated upon here. Regarding the operation methods in the above embodiments, the specific implementation methods of each step have been described in detail in the relevant device embodiments, and will not be elaborated upon here.

[0104] Figure 9 This is a schematic diagram illustrating the operation process of a memory according to an embodiment of the present disclosure. The following will use an example where the status information is the number of erase / write cycles and the operation command is an erase command, combined with... Figure 9The operation method of the memory provided in the embodiments of this disclosure will be described by way of example.

[0105] Reference Figure 9 As shown, in step S801: factory test. Here, during the factory test of the memory, all bit lines can be scanned. If a bit line is faulty, it is replaced using multiple reserved redundant bit lines. Then, the address of the redundant bit line that replaced the faulty bit line (i.e., the repair bit line) is recorded, and the address of the repair bit line is configured into the corresponding repair resource interface.

[0106] In step S802: The addresses of idle bit lines are recorded and stored in the configuration block. Here, based on the factory test results, unused redundant bit lines (i.e., idle bit lines) among multiple redundant bit lines can be identified. Then, the addresses of the unused redundant bit lines (i.e., idle bit line addresses) are recorded and saved to the configuration block. In a specific embodiment, the idle bit line addresses can be recorded in the form of a table, where A, B, C, ... represent different idle bit line addresses, such as... Figure 9 As shown in the image.

[0107] In step S803: Factory shipment / power-on. After the memory passes acceptance testing, it can be shipped from the factory and then powered on for use.

[0108] In step S804: The free bit line address is loaded into the internal register. Here, the free bit line address stored in the configuration block can be loaded during the memory power-on initialization process. Figure 6 In the register circuit 622.

[0109] In step S805: Determine whether an erase command has been received. If yes, proceed to step S806; otherwise, wait for the next operation command and determine whether the next operation command is an erase command.

[0110] In step S806: The chip is configured according to the free bit line address to read the erase count of the current memory block. Here, the configuration can be based on the free bit line resources; for example, one or more free bit lines can be allocated to a memory block, and then the erase count of the current memory block executing the erase command is read according to the free bit line address allocated to the target memory block. It should be noted that the erase count of the memory block should be 0 upon initial power-on.

[0111] In step S807: Normal erase. However, if an abnormal power outage occurs (i.e., step S812), then step S813 is executed: the erase / write count of the current storage block will be lost; this loss is tolerated; or, after the next power-on, it will be replaced by the erase / write count of an adjacent storage block. Specifically, after the next power-on, the erase / write count of an adjacent storage block can be read, and the erase / write count of the current storage block can be replaced with the erase / write count of the adjacent storage block, thereby avoiding the loss of the erase / write count of the current storage block.

[0112] In step S808: Determine whether the erasure was successful. If yes, proceed to step S809: Increment the erase / write count of the current storage block by 1 and write it back to its original location (i.e., allocate it to the redundant storage cell coupled to the free bit line of the current storage block); if no, proceed to step S810: No erase / write count management is required, thereby clearing the status information of the target storage block stored in the redundant storage cell and releasing the free bit line resources for use by other storage blocks.

[0113] In step S811: This erasure process is complete.

[0114] Thus, by executing the above steps S801 to S813, the management and maintenance of the storage block's status information can be achieved.

[0115] Figure 10 This is a schematic diagram illustrating a memory interface according to an embodiment of the present disclosure. (Refer to...) Figure 10 As shown, the memory provides interfaces P1 and P2 to expose the number of erase / write cycles. For example, the memory controller can obtain the number of erase / write cycles for a memory block through interfaces P1 and P2, thereby scheduling different error correction strategies. Here, interfaces P3 and P4 can be reserved for the implementation of other functions of the memory.

[0116] Based on the above-described memory, this disclosure provides a memory system. The memory system includes: one or more memories as described in any embodiment of this disclosure; and a memory controller coupled to the memory and configured to control the memory. The memory controller can be referenced accordingly. Figure 1 The memory controller 106 in the illustrated embodiment will not be described in detail here, including the functions, applications, and interaction between the memory and the memory controller.

[0117] Based on the above-described memory system, this disclosure provides an electronic device, including the above-described memory system.

[0118] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0119] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0120] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0121] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0122] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory, characterized in that, include: A storage cell array, comprising a primary array and a redundant array; wherein the primary array comprises multiple storage blocks, each storage block being coupled to multiple bit lines; the redundant array is coupled to multiple redundant bit lines, wherein repair bit lines among the multiple redundant bit lines are configured to repair faulty bit lines among the multiple bit lines; Peripheral circuitry, wherein the peripheral circuitry is coupled to the memory cell array via the plurality of bit lines and the plurality of redundant bit lines; wherein the peripheral circuitry is configured as follows: Determine the status information of the target storage block among the plurality of storage blocks; The status information of the target storage block is stored in a redundant storage cell coupled to an idle bit line among the multiple redundant bit lines; wherein the idle bit line and the repair bit line are different redundant bit lines.

2. The memory according to claim 1, characterized in that, The peripheral circuit is also configured to: Identify at least one of the multiple redundant bit lines as an idle bit line; At least one of the free bit lines is allocated to at least one of the storage blocks; wherein the redundant storage cell coupled to the free bit line allocated to the storage block is used to store the status information of the storage block.

3. The memory according to claim 2, characterized in that, The peripheral circuit includes: A register circuit configured to register the address of the free bit line; A control logic circuit coupled to the register circuit; wherein the control logic circuit is configured to: Obtain the address of the free bit line from the register circuit; The free bit line address is allocated to at least one of the storage blocks.

4. The memory according to claim 3, characterized in that, The peripheral circuit is specifically configured as follows: Based on the free bit line address allocated to the target storage block, the free bit line allocated to the target storage block is determined, and the status information of the target storage block is written into the redundant storage cell coupled to the free bit line.

5. The memory according to claim 3, characterized in that, The plurality of storage blocks include configuration blocks configured to store the free bit line address; the peripheral circuitry is further configured to: Upon power-up of the memory, the address of the free bit line is loaded into the register circuit.

6. The memory according to claim 1, characterized in that, The peripheral circuit is specifically configured to determine the status information based on at least one operation command for the target storage block.

7. The memory according to claim 6, characterized in that, The peripheral circuit is specifically configured as follows: Determine whether the operation command was executed successfully; Based on the successful execution of the operation command, the status information of the target storage block is increased from the first count value to the second count value.

8. The memory according to claim 7, characterized in that, The peripheral circuit is specifically configured as follows: If the operation command fails to execute, the status information of the target storage block stored in the redundant storage unit is cleared.

9. The memory according to claim 6, characterized in that, The peripheral circuit is also configured to: Based on the memory's power-on after an abnormal power outage, the status information of the memory blocks adjacent to the target memory block is obtained; Based on the state information of the adjacent storage blocks, the state information of the target storage block is re-determined.

10. The memory according to claim 1, characterized in that, Its features are, The status information includes the number of times the storage block has been erased and written.

11. A method for operating a memory, characterized in that, The operation method includes: Determine the state information of a target memory block among multiple memory blocks; wherein each memory block is coupled to multiple bit lines; The status information of the target storage block is stored in a redundant storage cell coupled to an idle bit line among multiple redundant bit lines; wherein, the multiple redundant bit lines include the idle bit line and the repair bit line, the repair bit line is used to repair the faulty bit line among the multiple bit lines, and the idle bit line and the repair bit line are different redundant bit lines.

12. The operating method according to claim 11, characterized in that, The operation method further includes: Identify at least one of the multiple redundant bit lines as an idle bit line; At least one of the free bit lines is allocated to at least one of the storage blocks; wherein the redundant storage cell coupled to the free bit line allocated to the storage block is used to store the status information of the storage block.

13. The operating method according to claim 12, characterized in that, Determining at least one of the multiple redundant bit lines as an idle bit line includes: obtaining the idle bit line address of the idle bit line; The step of allocating at least one of the free bit lines to at least one of the memory blocks includes: The free bit line address is allocated to at least one of the storage blocks.

14. The operating method according to claim 13, characterized in that, The step of storing the state information of the target storage block into a redundant storage cell coupled to a free bit line among multiple redundant bit lines includes: Based on the free bit line address allocated to the target storage block, the free bit line allocated to the target storage block is determined, and the status information of the target storage block is written into the redundant storage cell coupled to the free bit line.

15. The operating method according to claim 11, characterized in that, Determining the status information of the target storage block among multiple storage blocks includes: The status information is determined based on at least one operation command targeting the target storage block.

16. The operating method according to claim 15, characterized in that, Determining the status information based on at least one operation command targeting the target storage block includes: Determine whether the operation command was executed successfully; Based on the successful execution of the operation command, the status information of the target storage block is increased from the first count value to the second count value.

17. The operating method according to claim 16, characterized in that, Determining the status information based on at least one operation command targeting the target storage block includes: If the operation command fails to execute, the status information of the target storage block stored in the redundant storage unit is cleared.

18. The operating method according to claim 15, characterized in that, The operation method further includes: Based on the memory's power-on after an abnormal power outage, the status information of the memory blocks adjacent to the target memory block is obtained; Based on the state information of the adjacent storage blocks, the state information of the target storage block is re-determined.

19. A memory system, characterized in that, include: One or more memories as described in any one of claims 1 to 10; A memory controller, coupled to the memory and configured to control the memory.

20. An electronic device, characterized in that, include: The memory system as described in claim 19.

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