Memory device and error correction method thereof

Abstract

The invention provides a memory device and an error correction method thereof. The error correction method of the memory device comprises the following steps: generating a first write bit and a second write bit according to write data, and respectively writing the first write bit and the second write bit into a corresponding first memory cell and a corresponding second memory cell; in a read mode, a page buffer circuit is provided to read a first read bit of a first memory cell and a second read bit of a second memory cell; and causing the page buffer circuit to generate correct read data according to the fixed error mode, the first read bit, and the second read bit of the memory device.

Description

Technical Field

[0001] This disclosure relates to a memory device and a method for correcting errors thereon, and more particularly to a memory device and a method for correcting errors thereon that can quickly correct read data. Background Technology

[0002] In memory devices, the generation of some faulty storage cells is unavoidable. In known technical fields, the read data generated by faulty storage cells can be corrected using error-correction code (ECC) algorithms and corresponding circuitry. However, in modern applications, such as using memory devices in high-speed multiply-accumulate operations, error correction via ECC algorithms may cause delays in computation and reduce the performance of the memory device. Summary of the Invention

[0003] This disclosure provides a memory device and an error correction method thereof, which can quickly and effectively improve the accuracy of read data.

[0004] The error correction method for the memory device disclosed herein includes: generating a first write bit and a second write bit based on write data; writing the first write bit and the second write bit to corresponding first memory cells and second memory cells, respectively; providing a page buffer circuit in read mode to read a first read bit of the first memory cell and a second read bit of the second memory cell; and causing the page buffer circuit to generate correct read data based on the fixed error mode of the memory device, the first read bit, and the second read bit.

[0005] The memory device disclosed herein includes a memory cell array and a page buffer circuit. The memory cell array includes a plurality of memory cells, wherein a first memory cell and a second memory cell correspond to the same word line, and the first memory cell and the second memory cell are respectively used to store a first write bit and a second write bit corresponding to written data. The page buffer circuit is coupled to the first bit line and the second bit line of the corresponding first memory cell and the second memory cell, respectively. In read mode, the page buffer circuit reads the first read bit of the first memory cell and the second read bit of the second memory cell, and generates correct read data based on the fixed error mode of the memory device, the first read bit, and the second read bit.

[0006] Based on the above, the memory device of this disclosure stores one write data using two memory cells. The memory device of this disclosure also configures a page buffer circuit to generate a read data mechanism according to its fixed error mode. In this way, the page buffer circuit can quickly correct the read bits generated by the memory cells in the memory device, thus obtaining the correct read data. Attached Figure Description

[0007] Figure 1 A flowchart illustrating an error correction method for a memory device according to an embodiment of the present disclosure is shown.

[0008] Figure 2 A schematic diagram illustrating a memory device according to an embodiment of the present disclosure is shown.

[0009] Figure 3 A circuit diagram illustrating one embodiment of the memory device disclosed herein is shown.

[0010] Figure 4 Illustration published Figure 3 The operating waveform diagram of the memory device 300 in the embodiment.

[0011] Figure 5 A circuit diagram illustrating another embodiment of the memory device disclosed herein is shown.

[0012] Figure 6 A circuit diagram of a memory device according to another embodiment of the present disclosure is shown.

[0013] Figure 7 Illustration published Figure 6 Operating waveform diagram of the memory device 600 in the embodiment.

[0014] Figure 8 A circuit diagram illustrating another embodiment of the memory device disclosed herein is shown.

[0015] Explanation of reference numerals in the attached figures

[0016] 200, 300, 500, 600, 800: Memory devices

[0017] 210, 310, 510, 610, 810: Memory cell array

[0018] 220, 320, 520, 620, 820: Page buffer circuits

[0019] 521, 522, 821, 822: Buffers

[0020] 523, 823: Logic circuits

[0021] MC1, MC2: Storage units

[0022] BL1~BLM, BLA, BLA+1: Bit lines

[0023] WL0~WLn: Word lines

[0024] 321, 621: Data Holder

[0025] Q: Inverting data output terminal

[0026] QB: Data output end

[0027] 322, 623: Pull-up switches

[0028] 323, 622: Pull-down circuits

[0029] Lcell, Rcell: Control signals

[0030] Dout: Read data

[0031] GSL: Grounding Control Signal

[0032] SSL: String Select Signal

[0033] MS1, MS2: Switches

[0034] T1~T6: Time interval

[0035] MP1~MP3, MN1~MN5: Transistors

[0036] GND: Reference ground voltage

[0037] INV1, INV2: Inverters

[0038] VCC: Power supply voltage

[0039] SEN: Sensing signal

[0040] PLOAD, STB, PDL, PBLCH, SO: Signals

[0041] PBRST: Reset signal

[0042] S110~S130: Steps Detailed Implementation

[0043] Please refer to Figure 1 , Figure 1A flowchart illustrating an error correction method for a memory device according to an embodiment of the present disclosure is provided. In step S110, the memory device generates a first write bit and a second write bit based on write data, and writes the first write bit and the second write bit to corresponding first and second memory cells, respectively. In the memory device of this embodiment, two corresponding memory cells can be used to jointly store the same write data. For example, in the memory device of this embodiment, a first memory cell and a second memory cell connected to the same word line can be used to store the write data, and the first and second memory cells can be located on adjacent bit lines. The memory device generates the first write bit and the second write bit based on the write data, and the first write bit and the second write bit can, for example, have the same logic value. The first write bit and the second write bit are then written to the first and second memory cells, respectively.

[0044] In step S120, in the read mode of the memory device, by enabling the word line commonly coupled to the first and second memory cells, the memory device can provide page buffer circuits corresponding to the first and second memory cells to read the first read bit provided by the first memory cell and the second read bit provided by the second memory cell. In step S130, the page buffer circuit can generate correct read data based on the memory device's stuck-at-fault mode, the first read bit, and the second read bit.

[0045] In this embodiment, depending on the process conditions, the memory device may have different fixed error modes, such as a fixed error mode stuck at logic value 1 or a fixed error mode stuck at logic value 0. In step S130, the page buffer circuit of the memory device can generate correct read data based on the fixed error mode of the memory device and the obtained first read bit and second read bit.

[0046] Please note that in a memory device, faulty memory cells exhibiting fixed error patterns are randomly distributed across the memory cell array. Therefore, the probability that both the first and second memory cells, connected to the same word line and located on adjacent bit lines, are faulty memory cells is extremely low. Thus, using both the first and second memory cells to jointly store written data ensures the correctability of the written data.

[0047] In detail, when the fixed error mode of the memory device is fixed at logic value 1 (i.e., the fixed logic value of the fixed error mode is equal to logic value 1), it means that all read bits provided by the erroneous memory cell are logic values ​​1. Under such conditions, if the page buffer circuit determines that one of the first and second read bits is a logic value 1, and the other of the first and second read bits is not a logic value 1 (is a logic value 0), the page buffer circuit can determine that the read bit that produces a logic value 1 in the first and second memory cells is an erroneous memory cell; while the read bit that produces a logic value 0 is a correct memory cell. Accordingly, the page buffer circuit can generate read data with a logic value of 0.

[0048] When the fixed error mode of a memory device is fixed at logic value 0 (i.e., the fixed logic value of the fixed error mode is equal to logic value 0), it means that all read bits provided by the faulty memory cell are logic values ​​0. Under this condition, if the page buffer circuit determines that one of the first and second read bits is a logic value 0, and the other of the first and second read bits is not a logic value 0 (is a logic value 1), the page buffer circuit can determine that the read bit that produces a logic value 0 in the first and second memory cells is a faulty memory cell; while the read bit that produces a logic value 1 is a correct memory cell. Accordingly, the page buffer circuit can generate read data with a logic value of 1.

[0049] Incidentally, regardless of the fixed error mode of the memory device, in this embodiment, if both the first read bit and the second read bit are the same logic value (logic value 1 or 0), it indicates that both the first memory cell and the second memory cell are normal memory cells, and the page buffer circuit can generate read data based on the same logic value of the first read bit and the second read bit.

[0050] Please refer to Figure 2 , Figure 2 A schematic diagram of a memory device according to an embodiment of the present disclosure is shown. The memory device 200 includes a memory cell array 210 and a page buffer circuit 220. The memory cell array 210 includes a plurality of memory cells, wherein, corresponding to a write data, memory cells MC1 and MC2 in the memory cell array 210 can be used to store a first write bit and a second write bit generated according to the write data. For example, if the write data is a logic value 1, the first write bit and the second write bit can both be the same logic value 1 and are written to memory cells MC1 and MC2 respectively. If the write data is a logic value 0, the first write bit and the second write bit can both be the same logic value 0 and are written to memory cells MC1 and MC2 respectively.

[0051] Furthermore, memory cells MC1 and MC2 are coupled to the same word line WLn and respectively coupled to adjacent bit lines BL1 and BL2. Since faulty memory cells exhibiting fixed error patterns are randomly distributed across multiple locations in the memory cell array 210 within the memory device 200, the probability that memory cells MC1 and MC2 are both faulty memory cells simultaneously is very low.

[0052] Page buffer circuit 220 is coupled to memory cells MC1 and MC2 via bit lines BL1 and BL2. Furthermore, in read mode, page buffer circuit 220 can determine whether memory cells MC1 and MC2 contain erroneous memory cells based on the fixed error mode of memory device 200 and the first and second read bits transmitted from memory cells MC1 and MC2. It then generates read data Dout by outputting the read bit of the correct memory cell, thereby ensuring the correctness of the read data Dout.

[0053] It is noteworthy that, in this embodiment of the present disclosure, the page buffer circuit 220, through the fixed logic value of the fixed error mode, the logic value between the first read bit and the second read bit, can quickly correct the first read bit and the second read bit transmitted by the memory cells MC1 and MC2, and generate the correct read data Dout. This completes the error correction of the read data Dout without requiring complex error-correction code (ECC) calculations, thereby improving the operating efficiency of the memory device 200.

[0054] Incidentally, the fixed error modes of the memory device 200 are determined by the manufacturing process of the memory device 200. Designers can determine the fixed error modes of the memory device 200 based on its manufacturing process. They can then design the page buffer circuit 220 according to these fixed error modes to perform corresponding actions and effectively correct errors in the read data Dout.

[0055] Please refer to the following: Figure 3 , Figure 3 A circuit diagram illustrating one embodiment of the memory device disclosed herein is shown. The memory device 300 includes a memory cell array 310 and a page buffer circuit 320. In this embodiment, the memory cell array 310 is, for example, a NAND flash memory cell array. In other embodiments of this disclosure, the memory cell array 310 may also be any other form of memory array, without any limitation.

[0056] The memory cell array 310 has multiple memory cell strings, each coupled to word lines WL0~WLN. Each memory cell string has a ground selection switch and a memory cell string selection switch at both ends, controlled by a ground control signal GSL and a memory cell string selection signal SSL, respectively. The ground selection switch and the memory cell string selection switch are coupled to a reference ground voltage GND and the corresponding bit lines BL0~BLM, respectively.

[0057] On the other hand, the page buffer circuit 320 is coupled to bit lines BL2 and BL3 respectively via switches MS1 and MS2. Switches MS1 and MS2 can both be transistor switches. The page buffer circuit 320 is used to read the read bits transmitted from the memory cells on bit lines BL2 and BL3, and generate read data Dout accordingly.

[0058] In terms of circuit details, the page buffer circuit 320 of this embodiment is provided for a memory device 300 with a fixed error mode corresponding to a fixed logic value of logic 0. The page buffer circuit 320 includes a sensing signal generator constructed by transistor MP1, a data sustainer 321, a pull-up switch 322, and a pull-down circuit 323. One end of transistor MP1 receives the power supply voltage VCC; the other end of transistor MP1 is coupled to switches MS1 and MS2 and is used to generate a sensing signal SEN; the control terminal of transistor MP1 receives the signal PLOAD. The pull-up switch 322 is coupled to the inverted data output terminal Q of the data sustainer 321. The pull-up switch 322 is composed of transistor MP2, the first end of which receives the power supply voltage VCC; the second end of transistor MP2 is coupled to the inverted data output terminal Q of the data sustainer 321; transistor MP2 is controlled by the reset signal PBRST.

[0059] The pull-down circuit 323 includes transistors MN2, MN4, and MN5. Transistors MN2, MN4, and MN5 are connected in series between the inverted data output terminal Q of the data sustain circuit 321 and the reference ground voltage GND. Transistors MN2, MN4, and MN5 are controlled by signals PDL, STB, and the sensing signal SEN, respectively.

[0060] Incidentally, the page buffer circuit 320 also includes transistors MN1 and MN3. Transistor MN1 is coupled between the data output terminal QB of the data sustainer 321 and transistor MP1. In this embodiment, the control terminal of transistor MN1 receives a 0V bias voltage and is in a cutoff state. Transistor MN3 is coupled between the data output terminal QB of the data sustainer 321 and transistor MN4. In this embodiment, the control terminal of transistor MN3 receives a 0V signal PDLB and is also in a cutoff state.

[0061] For details regarding the operation of the memory device 300, please refer to [the relevant documentation / reference]. Figure 3 as well as Figure 4 ,in Figure 4 Illustration published Figure 3 A waveform diagram illustrating the operation of the memory device 300 in this embodiment. Figure 4 During time interval T1, the reset signal PBRST is pulled low and enters the reset period, turning on transistor MP2. Consequently, the voltage at the inverted data output terminal Q of data sustainer 321 is pulled high (e.g., equal to the power supply voltage VCC). Correspondingly, the read data Dout at the data output terminal QB of data sustainer 321 is pulled low.

[0062] During time interval T2, the signal PLOAD is pulled low and transistor MP1 is turned on. Correspondingly, transistor MP1 can provide the power supply voltage VCC to generate the sensing signal SEN, and pull the sensing signal SEN high to the power supply voltage VCC.

[0063] During time interval T3, switch MS1 is turned on according to the pulled-high control signal Lcell. With word line WLN-1 enabled, memory cell MC1 provides a first read bit to bit line BL2. The first read bit is transmitted to the second terminal of transistor MP1 via the turned-on switch MS1. Taking the first read bit as a logic value of 1 as an example, the first read bit can maintain the sense signal SEN at a logic value of 1.

[0064] During time interval T4, signals STB and PDL are pulled high to logic 1, and transistors MN2 and MN4 are turned on accordingly. Since the sense signal SEN is also at logic 1, transistor MN5 is also turned on synchronously. Therefore, pull-down circuit 323 provides a discharge path between the inverting data output terminal Q and the reference ground voltage GND, pulling the voltage on the inverting data output terminal Q down to the reference ground voltage GND. Correspondingly, the read data Dout on the data output terminal QB of data sustainer 321 is pulled high to logic 1.

[0065] Through the above actions, the memory device 300 can load the read bit provided by the memory cell MC1 during the time interval T3 to T4 via the page buffer circuit 320. When the read bit provided by the memory cell MC1 is different from the fixed logic value of the fixed error mode of the memory device 300, the page buffer circuit 320 can write the read bit provided by the memory cell MC1 into the data maintainer 321.

[0066] At the beginning of time interval T5, the PLOAD signal is pulled low again, and the loading action of the next memory cell MC2 is started.

[0067] When the corresponding signal PLOAD is pulled low again, transistor MP1 is turned on, and the sensing signal SEN remains at logic value 1. Then, after the signal PLOAD returns to logic value 1, the control signal Rcell is pulled high to logic value 1, and switch MS2 is turned on accordingly. The read bit of memory cell MC2 can be transmitted to the page buffer circuit 320 via switch MS2. In this embodiment, memory cell MC2 is an error memory cell, and its generated read bit is fixed at logic value 0. Therefore, in the subsequent time interval T5, the sensing signal SEN is correspondingly pulled low to logic value 0.

[0068] During time interval T5, based on the sensing signal SEN being a logic value of 0, transistor MN5 is turned off, and the discharge path formed by pull-down circuit 323 is cut off. Therefore, the voltage at the inverting data output terminal Q of data sustainer 321 does not change. Conversely, the data output terminal QB of data sustainer 321 maintains the read data Dout.

[0069] In other words, in this embodiment, when the read bit provided by the storage unit MC2 is the same as the fixed logic value of the fixed error mode of the memory device 300, the page buffer circuit 320 can ignore the read bit provided by the storage unit MC2.

[0070] In addition, during time interval T5, signals STB and PDL are pulled high to logic value 1, and page buffer circuit 320 can generate read data Dout with logic value 1.

[0071] Incidentally, in this embodiment, the data sustainer 321 includes inverters INV1 and INV2, wherein the input terminal of inverter INV1 is the inverted data output terminal Q of the data sustainer 321, and the input terminal of inverter INV2 is the data output terminal QB of the data sustainer 321. The output terminal of inverter INV1 is coupled to the input terminal of inverter INV2, and the input terminal of inverter INV1 is coupled to the output terminal of inverter INV2.

[0072] Please refer to the table below, which is the truth table for the data reading action in this embodiment:

[0073]

[0074] Regardless of whether the written data is a logic value 1 or 0, if an error occurs in the storage unit MC2, the page buffer circuit 320 of this embodiment can obtain read data Dout equal to the expected read data.

[0075] Please refer to the following: Figure 5 , Figure 5A circuit diagram illustrating another embodiment of the memory device disclosed herein is shown. The memory device 500 includes a memory cell array 510 and a page buffer circuit 520. In this embodiment, the memory cell array 510 may have the same circuit architecture as the memory cell array 310, and related details will not be described in detail.

[0076] The page buffer circuit 520 of this embodiment is provided in a memory device 500 corresponding to a fixed error mode with a fixed logic value of 0. In this embodiment, the page buffer circuit 520 includes buffers 521 and 522 and a logic circuit 523. Buffers 521 and 522 are coupled to bit lines BLA and BLA+1, respectively. Bit lines BLA and BLA+1 correspond to memory cells MC1 and MC2, respectively. Buffers 521 and 522 are used to receive and temporarily store read bits generated by memory cells MC1 and MC2. Furthermore, the logic circuit 523 can perform an OR logic operation on the read bits temporarily stored in buffers 521 and 522, thereby generating read data Dout. The truth table of the logic operation of the page buffer circuit 520 is as follows:

[0077]

[0078] In this embodiment, the logic circuit 523 can be an OR logic gate, or a combination of multiple logic gates, to perform OR logic operations on the read bits temporarily stored in the buffers 521 and 522. For example, the logic circuit 523 can be constructed by connecting NOR gates and inverters in series, or by using other combinations of logic gates, without fixed limitations.

[0079] Incidentally, the memory device 500 of this disclosure embodiment may have multiple page buffer circuits 520, each coupled to a corresponding two-bit line. Figure 5 The single page buffer circuit 520 illustrated herein is merely an illustrative example and should not be construed as limiting the scope of this disclosure. Designers can determine the number of page buffer circuits 520 required based on the actual number of bit lines in the memory device 500.

[0080] Please refer to Figure 6 , Figure 6 A circuit diagram of a memory device according to another embodiment of the present disclosure is shown. The memory device 600 includes a memory cell array 610 and a page buffer circuit 620. In this embodiment, the memory cell array 610 has a similar circuit architecture to the memory cell array 310, which will not be described in detail here.

[0081] On the other hand, the page buffer circuit 620 is coupled to bit lines BL2 and BL3 respectively via switches MS1 and MS2. Switches MS1 and MS2 can both be transistor switches. The page buffer circuit 620 is used to read the read bits transmitted from the memory cells on bit lines BL2 and BL3, and generate read data Dout accordingly.

[0082] In terms of circuit details, the page buffer circuit 620 of this embodiment is provided for a memory device 600 with a fixed error mode corresponding to a fixed logic value of logic 1. The page buffer circuit 620 includes a data hold circuit 621, a pull-up switch 623, and a pull-down circuit 622. The pull-up switch 623 can be constructed by transistor MP2. The control terminal of transistor MP2 is coupled to the power supply voltage VCC through transistor MP3; the first terminal of transistor MP2 is coupled to the power supply voltage VCC through transistor MP1. Transistors MP1 and MP3 are controlled by signals PBLCH and PLOAD, respectively.

[0083] The second terminal of transistor MP2 is coupled to the inverted data output terminal Q of data sustain 612. A pull-down circuit 622 is coupled between the inverted data output terminal Q of data sustain 612 and the reference ground voltage GND. The pull-down circuit 622 is composed of transistor MN. Transistor MN is controlled by the reset signal PBRST. In addition, the page buffer circuit 620 includes transistor MN1. Transistor MN1 is coupled between the control terminal of transistor MP2 and the output terminal QB of data sustain 612. The control terminal of transistor MN1 receives a voltage of 0V and is in the off state.

[0084] For details regarding the operation of memory device 600, please refer to [link / reference]. Figure 6 as well as Figure 7 ,in Figure 7 Illustration published Figure 6 A waveform diagram illustrating the operation of the memory device 600 according to an embodiment. Figure 7 During time interval T1, the reset signal PBRST is pulled up to logic 1 and enters the reset period. Correspondingly, transistor MN2 is turned on, and the inverted data output Q of data sustainer 612 is set to logic 0. Correspondingly, the output QB of data sustainer 612 is set to logic 1.

[0085] Next, after the reset signal PBRST is pulled low to logic 0, the signal PLOAD is pulled low to logic 0, and transistor MP3 is turned on. At this time, the turned-on transistor MP3 provides the power supply voltage VCC to the control terminal of transistor MP2, causing the signal SO to be pulled high to logic 1, and transistor MP2 to be turned off.

[0086] During time interval T2, signal SO remains at logic value 1. During time interval T3, control signal Lcell is pulled high to turn on switch MS1. Correspondingly, memory cell MC1 provides a read bit, for example, logic value 0, to the control terminal of transistor MP2, and pulls signal SO low.

[0087] As signal SO goes low, transistor MP2 becomes active. During time interval T3, transistor MP1 is off because signal PBLCH remains at logic 1. Therefore, the voltages at the inverted data output Q and output QB of data sustainer 612 remain unchanged.

[0088] During time interval T4, signal PBLCH is pulled low to logic 0, transistor MP1 is turned on, and the first terminal of transistor MP2 is pulled up to the power supply voltage VCC. Since transistor MP2 is currently on, the voltage at the inverted data output terminal Q of data sustain 612 can be pulled up to logic 1, and conversely, the voltage at the output terminal QB of data sustain 612 can be pulled down to logic 0.

[0089] During the first part of time interval T5, signal PLOAD is pulled low again to turn on transistor MP3, which in turn pulls signal SO high again. Then, control signal Rcell is pulled high to logic 1 to turn on switch MS2. Correspondingly, memory cell MC2 can provide a read bit, which is transmitted to the control terminal of transistor MP2 via switch MS2. Since the read bit provided by memory cell MC2 is a fixed logic value of 1, signal SO can remain unchanged at logic value 1.

[0090] During time interval T6, the signal PBLCH is pulled low to turn on transistor MP1. Since transistor MP2 is controlled by the signal SO, which is logic 1, the conduction of transistor MP1 does not affect the voltage at the inverted data output terminal Q of data hold circuit 612. Here, page buffer circuit 620 can generate read data Dout equal to logic 0.

[0091] Please refer to the table below, which is the truth table for the data reading action in this embodiment:

[0092]

[0093] Regardless of whether the written data is a logic value 1 or 0, under the condition that the storage unit MC2 is faulty, the page buffer circuit 620 of this embodiment can obtain read data Dout equal to the expected read data.

[0094] Please refer to the following: Figure 8 , Figure 8A circuit diagram illustrating another embodiment of the memory device disclosed herein is shown. The memory device 800 includes a memory cell array 810 and a page buffer circuit 820. In this embodiment, the memory cell array 810 may have the same circuit architecture as the memory cell array 610, and related details will not be described in detail.

[0095] The page buffer circuit 820 of this embodiment is provided in a memory device 800 corresponding to a fixed error mode with a fixed logic value of 1. In this embodiment, the page buffer circuit 820 includes buffers 821 and 822 and a logic circuit 823. Buffers 821 and 822 are coupled to bit lines BLA and BLA+1, respectively. Bit lines BLA and BLA+1 correspond to memory cells MC1 and MC2, respectively. Buffers 821 and 822 are used to receive and temporarily store read bits generated by memory cells MC1 and MC2. Furthermore, the logic circuit 823 can perform AND logic operations on the read bits temporarily stored in buffers 821 and 822, thereby generating read data Dout. The truth table of the logic operations of the page buffer circuit 820 is as follows:

[0096]

[0097] In this embodiment, the logic circuit 823 can be an OR logic gate, or a combination of multiple logic gates, to perform OR logic operations on the read bits temporarily stored in the buffers 821 and 822. For example, the logic circuit 823 can be constructed by connecting NAND gates and inverters in series, or by using other combinations of logic gates, without fixed limitations.

[0098] In summary, the memory device disclosed herein stores a single write data using two memory cells. Furthermore, a page buffer circuit is configured to address the fixed error mode of the memory device. Through the page buffer circuit, error correction of the read bits can be quickly performed based on the fixed logic value of the fixed error mode and the two read bits from the memory cell, thus obtaining the correct read data.

Claims

1. A method for error correction of a memory device, comprising: Based on a write data, a first write bit and a second write bit are generated, and the first write bit and the second write bit are respectively written to a corresponding first storage unit and a second storage unit. In a read mode, a page buffer circuit is provided to read a first read bit of the first memory cell and a second read bit of the second memory cell; and The page buffer circuit generates correct read data based on a fixed error mode of the memory device, the first read bit, and the second read bit.

2. The error correction method according to claim 1, wherein the fixed error mode includes the read bit corresponding to the error storage cell of the memory device being fixed at logic value 1 or fixed at logic value 0.

3. The error correction method of claim 1, wherein the step of causing the page buffer pad to generate correct read data based on the fixed error mode of the memory device, the first read bit, and the second read bit includes: When a fixed logic value of the fixed error mode is the same as one of the first read bit and the second read bit, the read data is generated based on the other of the first read bit and the second read bit.

4. The error correction method according to claim 3 further includes: When the first read bit is not the same as the fixed logic value, the read data is made equal to the first read bit; as well as When the second read bit is the same as the fixed logic value, the second read bit is ignored.

5. The error correction method according to claim 3 further includes: When the fixed logic value is 1, the first read bit and the second read bit are subjected to an AND logic operation to generate the read data.

6. The error correction method according to claim 3 further includes: When the fixed logic value is 0, the first read bit and the second read bit are ORed to generate the read data.

7. The error correction method according to claim 1, wherein the first memory cell and the second memory cell are coupled to the same word line and respectively disposed on adjacent bit lines, and the first write bit and the second write bit have the same logic value.

8. A memory device, comprising: A storage cell array includes multiple storage cells, wherein a first storage cell and a second storage cell correspond to the same word line, wherein the first storage cell and the second storage cell are respectively used to store a first write bit and a second write bit corresponding to a written data; as well as A page buffer circuit is coupled to a first bit line and a second bit line of the corresponding first memory cell and second memory cell, respectively. The page buffer circuit reads a first read bit of the first memory cell and a second read bit of the second memory cell in a read mode, and generates correct read data according to a fixed error mode of the memory device, the first read bit and the second read bit.

9. The memory device of claim 8, wherein the fixed error mode includes the read bit corresponding to the error storage cell of the memory device being fixed at logic value 1 or fixed at a logic value.

10. The memory device of claim 8, wherein the page buffer circuit generates the read data based on the other of the first read bit and the second read bit when a fixed logic value of the fixed error mode is the same as one of the first read bit and the second read bit.

11. The memory device of claim 8, wherein when a fixed logic value of an error storage cell in the memory device is logic 0, the page buffer circuit comprises: A sensing signal generator is coupled to the first memory cell and the second memory cell via multiple switches, and sets the logic value of a sensing signal according to the first read bit and the second read bit. A data hold device has a data output terminal and an inverted data output terminal, wherein the data output terminal of the data hold device is used to output the read data; A pull-down circuit is coupled between the inverting data output terminal and a reference ground voltage to pull down the voltage on the inverting data output terminal according to the sensing signal. as well as A pull-up switch is coupled between the inverting data output terminal and a reference voltage, and pulls up the voltage on the inverting data output terminal during a reset period.

12. The memory device of claim 11, wherein the data maintainer comprises: A first inverter has an input terminal coupled to the data output terminal, and the output terminal of the first inverter is coupled to the inverted data output terminal; as well as A second inverter has an input terminal coupled to the inverted data output terminal, and the output terminal of the second inverter is coupled to the data output terminal.

13. The memory device of claim 8, wherein when a fixed logic value of an error storage cell in the memory device is logic 0, the page buffer circuit comprises: A first buffer, coupled to the first bit line, is used to temporarily store the first read bit; A second buffer, coupled to the second bit line, is used to temporarily store the second read bit; as well as A logic circuit, coupled to the first buffer and the second buffer, performs an OR logic operation on the first read bit and the second read bit to generate the read data.

14. The memory device of claim 8, wherein when a fixed logic value of an error storage cell in the memory device is logic 1, the page buffer circuit comprises: A data hold device has a data output terminal and an inverted data output terminal, wherein the data output terminal of the data hold device is used to output the read data; A pull-down circuit is coupled between the inverting data output terminal and a reference ground voltage to pull down the voltage on the inverting data output terminal during a reset period. as well as A pull-up switch is coupled between the inverting data output terminal and a reference voltage to pull up the voltage on the inverting data output terminal according to the first read bit or the second read bit.

15. The memory device of claim 14, wherein the data maintainer comprises: A first inverter has an input terminal coupled to the data output terminal, and the output terminal of the first inverter is coupled to the inverted data output terminal; as well as A second inverter has an input terminal coupled to the inverted data output terminal, and the output terminal of the second inverter is coupled to the data output terminal.

16. The memory device of claim 8, wherein when a fixed logic value of an error storage cell in the memory device is logic 1, the page buffer circuit comprises: A first buffer, coupled to the first bit line, is used to temporarily store the first read bit; A second buffer, coupled to the second bit line, is used to temporarily store the second read bit; as well as A logic circuit, coupled to the first buffer and the second buffer, performs AND and logic operations on the first read bit and the second read bit to generate the read data.

17. The memory device of claim 8, wherein the first write bit and the second write bit have the same logic value, and the first memory cell and the second memory cell are respectively disposed on adjacent bit lines.

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