Semiconductor stack wafer

Abstract

The invention provides a semiconductor stack wafer. The semiconductor stack wafer comprises a plurality of wafers, a standby wafer and a repair information block, each wafer includes a plurality of dies, and the plurality of wafers includes a logic wafer having a plurality of logic dies. And the standby wafer repairs the target wafer in the plurality of wafers according to the repair enabling signal and the repair information signal. The repair information block is located in the standby wafer or the logic wafer. The repair information block is used for inputting an input signal and outputting a repair enabling signal and a repair information signal according to the input signal.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor stacked wafer with a repair mechanism, which can improve the yield of the semiconductor stacked wafer. BACKGROUND

[0002] The stacked wafers of semiconductor wafers have been developed and used to make memory devices with high bandwidth and large storage capacity. The stacked wafers are stacked by several semiconductor wafers. However, as the number of wafers increases, the yield of the stacked wafers decreases sharply, so the present application proposes a novel technology to improve the yield of the stacked wafers. SUMMARY

[0003] According to an embodiment of the present application, a semiconductor stacked wafer includes a plurality of wafers, a spare wafer, and a repair information block. The plurality of wafers each includes a plurality of dies, and the plurality of wafers includes a logic wafer and a target wafer. The spare wafer is used to repair the target wafer in the plurality of wafers according to a repair enable signal and a repair information signal. The repair information block is located in the spare wafer or the logic wafer, and the repair information block is used to input an input signal and output the repair enable signal and the repair information signal according to the input signal.

[0004] According to an embodiment of the present application, a semiconductor stacked wafer includes a plurality of wafers, a spare wafer, and a repair information block. The plurality of wafers each includes a plurality of dies, and the plurality of wafers includes a logic wafer and a target wafer. The spare wafer is used to repair the target wafer in the plurality of wafers according to a repair enable signal and a repair information signal. The repair information block is located in the spare wafer or the logic wafer, and the repair information block is used to input an input signal and output the repair enable signal and the repair information signal according to the input signal.

[0005] According to an embodiment of the present application, a spare wafer is added to a semiconductor stacked wafer, thereby improving the yield of the wafer stack. Since the target wafer in the plurality of wafers of the semiconductor stacked wafer can be repaired in units of dies, in units of dummy channels, in units of memory banks, or in units of memory behaviors, the repair mechanism of the embodiment of the present application can be effectively and flexibly applied to a wide range of products. In addition, the I / O segments (or IO units) of the target wafer of the semiconductor stacked wafer can be repaired using the proposed repair mechanism. Therefore, the flexibility of the repair mechanism can be further improved. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1is a schematic diagram of a semiconductor stack wafer according to an embodiment of the present invention;

[0007] Figure 2 is a schematic diagram of a memory device formed by stacking memory dies of a semiconductor stack wafer according to an embodiment of the present invention;

[0008] Figure 3A is a schematic diagram of a repair information block for repairing a target die of a target wafer according to an embodiment of the present invention;

[0009] Figure 3B and Figure 3C is a waveform diagram of signals in a semiconductor stack wafer for repairing a target die according to an embodiment of the present invention;

[0010] Figure 4A is a schematic diagram of a repair information block for repairing a target virtual channel, a target memory bank, or a target row of a target wafer according to an embodiment of the present invention;

[0011] Figure 4B and Figure 4C is a waveform diagram of signals in a semiconductor stack wafer for repairing a target virtual channel, a target bank, or a target row according to an embodiment of the present invention;

[0012] Figure 5A is a schematic diagram of a repair information block for repairing a target column in a target wafer according to an embodiment of the present invention;

[0013] Figure 5B and Figure 5C is a waveform diagram of signals in a semiconductor stack wafer for repairing a target column according to an embodiment of the present invention;

[0014] Figure 5D is a schematic diagram of an I / O section in a memory bank of a semiconductor stack wafer according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] Reference will now be made to specific embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0016] Figure 1is a schematic diagram of a semiconductor stack wafer 100 according to embodiments of the present application. The semiconductor stack wafer 100 can include a plurality of wafers W0, W1, W2, W3, W4, W5, W6, W7 stacked on each other. The wafers W0 to W7 of the semiconductor stack wafer 100 can be stacked on each other using a wafer-to-wafer stacking technique. Each of the wafers W0 to W7 can include a plurality of semiconductor dies D (also referred to as dies D) that can be stacked on each other to form a memory device, such as a high bandwidth memory (HBM). It should be understood that the number of wafers W0 to W7 in the semiconductor stack wafer 100 and the number of dies D per wafer are not limited to any particular number. The memory device formed by the stacking of the dies D of the semiconductor stack wafer 100 can be a volatile or non-volatile memory. For example, the memory device can be a dynamic random-access memory (DRAM), but the present application is not limited thereto.

[0017] The wafers W0 to W7 of the semiconductor stack wafer 100 can include a logic wafer, a spare wafer, and a plurality of memory wafers. For brevity, the wafer W0 of the semiconductor stack wafer 100 is referred to as a logic wafer or a system on chip (SoC) wafer, the wafer W1 is referred to as a spare wafer, and the wafers W2 to W7 are referred to as memory wafers. In some embodiments, the memory wafer W7 is also referred to as a target wafer or a failed wafer for repair operations. It should be noted that the present application does not limit the number of logic wafers, the number of spare wafers, and the number of memory wafers in the semiconductor stack wafer 100. Furthermore, the positions and arrangements of the logic wafers, the spare wafer, and the memory wafers in the semiconductor stack wafer 100 can be changed according to design needs.

[0018] Figure 2This is a schematic diagram of a memory device 200 formed by multiple memory dies D0, D1, D2, D3, D4, D5, D6, and D7 of stacked semiconductor wafers according to an embodiment of the present invention. The memory device 200 may be DRAM, but the present invention is not limited thereto. Dies D0 to D7 are dies of wafers W0 to W7, respectively. Die D0 in logic wafer W0 may be referred to as logic die D0, spare die D1 in spare wafer W1 may be referred to as spare die D1, and dies D2 to D7 in memory wafers W2 to W7 may be referred to as memory dies D2 to D7. The memory device 200 may include memory ranks R0 and R1, each corresponding to multiple wafers. For example, the first memory rank R0 may correspond to wafers W0 to W3, and the second memory rank R1 may correspond to wafers W4 to W7. Memory ranks R0 and R1 may be selected by the logical states of rank selection signals SID[0] and SID[1]. For example, when the rank selection signal SID[0] is in a high logic state, the first rank R0 is selected; when the rank selection signal SID[1] is in a high logic state, the second rank R1 is selected.

[0019] Each die D0 to D7 may include multiple virtual channels PC0, PC1, PC2, and PC3, and each virtual channel PC0 to PC3 may include multiple memory banks BK0 to BK15. Each memory bank BK0 to BK15 may include multiple memory rows (not shown) and multiple memory columns (not shown). Each die D0 to D7 may also include multiple input / output (I / O) segments.

[0020] To improve the yield of stacked dies, a spare wafer (i.e., spare wafer W1) is added to the semiconductor stacked wafer 100 to repair the target wafer (i.e., target wafer W7) when a failed wafer (i.e., target die W7) is determined to be present in the semiconductor stacked wafer 100. In this way, the yield of the semiconductor stacked wafer 100 can be improved.

[0021] In some embodiments, target wafer W7 can be repaired on a die-by-die basis. In other words, the target die in target wafer W7 can be replaced by a spare die in spare wafer W1. Target wafer W7 can be repaired on a virtual channel-by-virtual channel-by-memory bank-by-memory behavior-by-memory behavior basis. Furthermore, the target I / O segment of the target die in target wafer W7 can also be repaired using spare wafer W1.

[0022] Figure 3AThis is a schematic diagram of a repair information block 310 for repairing a target die in a target wafer W7, as shown in an embodiment of the present invention. In other words, by using the repair information block 310, the target die in the target wafer W7 can be replaced by a corresponding spare die in a spare wafer W1. The repair information block 310 can be located in the logic wafer W0 or the spare wafer W1 of the semiconductor stack wafer 100. The repair information block 310 can be implemented by hardware circuitry, software, or firmware.

[0023] Repair information block 310 can receive input signal IN_S and generate repair enable signal TSV_REDUN_MISS and repair information signal RE_S1. Input signal IN_S may include rank selection signal SID[0:1], library selection signal BA[0:15], and row selection signal RA_LAT[0:13]. Rank selection signal SID[0:1] is used to select the memory rank for repair operation, library selection signal BA[0:15] is used to select the target memory library for repair operation, and row selection signal RA_LAT[0:13] is used to select the memory row for repair operation.

[0024] The repair enable signal TSV_REDUN_MISS indicates whether a repair operation should be performed on semiconductor stack wafer 100. For example, when the repair enable signal TSV_REDUN_MISS is in a high logic state, no repair operation is performed on semiconductor stack wafer 100. When the repair enable signal TSV_REDUN_MISS is in a low logic state, a repair operation is performed to repair the target wafer (i.e., target wafer W7) of semiconductor stack wafer 100.

[0025] The repair information signal RE_S1 may include wafer selection signal WS[0:7], spare wafer selection signal WS_RED, library selection signal BA[0:15], and row selection signal RA_LAT[0:13]. The wafer selection signal WS[0:7] is used to select the target wafer for the repair operation, and the spare wafer selection signal WS_RED is used to select the spare wafer for the repair operation. The library selection signal BA[0:15] and row selection signal RA_LAT[0:13] may remain the same as the library selection signal BA[0:15] and row selection signal RA_LAT[0:13] input to the repair information block 310.

[0026] Repair information block 310 transmits the wafer select signal WS[0:7] to each die of wafers W0 to W7. The spare wafer select signal WS_RED is transmitted to each die of spare wafer W1, and the library select signal BA[0:15] and row select signal RA_LAT[0:130] are transmitted to all dies of wafers W0 to W7.

[0027] Figure 3B andFigure 3C This is a waveform diagram of a signal in a semiconductor stack wafer used for repairing a target die, as shown in an embodiment of the present invention. Figure 3B and Figure 3C The signals displayed include the repair enable signal TSV_REDUN_MISS, the rank selection signals SID[0] and SID[1], the wafer selection signals WS[0:3] and WS[4:7], the spare wafer selection signal WS_RED, the library selection signals BA[0] and BA[1:15], the row selection signal RA_LAT[0:13], and the read / write signal RD / WR.

[0028] The rank selection signals SID[0] and SID[1] indicate the memory rank selected in memory ranks R0 and R1. Wafer selection signals WS[0:3] are transmitted to the dies of wafers W0 to W3, and wafer selection signals WS[4:7] are transmitted to the dies of wafers W4 to W7. The logical state of the wafer selection signals WS[0:7] indicates which wafer among W0 to W7 is selected for the repair operation. The spare wafer selection signal WS_RED is transmitted to the spare die of spare wafer W1 to indicate whether spare wafer W1 is selected for the repair operation. The library selection signal BA[0:15] is transmitted to memory libraries BK0 to BK15 to indicate which memory library is selected, and the row selection signal RA_LAT[0:13] indicates which memory row is selected. The read / write signals RD / WR indicate the memory operation to be performed (i.e., a read operation or a write operation).

[0029] Reference Figure 3B Assume that memory bank BK0 of second rank R1 is selected and no repair operation is performed. Since no repair operation is performed, the repair enable signal TSV_REDUN_MISS is in a high logic state and the spare wafer select signal WS_RED is in a low logic state. In addition, since memory rank R1 is selected, the first rank select signal SID[0] is in a low logic state and the second rank select signal SID[1] is in a high logic state. Figure 3B Further, it is shown that the wafer selection signals WS[0:3] are in a low logic state, and the wafer selection signals WS[4:7] are in a high logic state. This indicates that wafers W0 to W3 are not selected, and wafers W4 to W7 are selected. The library selection signal BA[0] is in a high logic state, while the library selection signal BA[1:15] is in a low logic state, indicating that memory library BK0 is selected. The row selection signal RA_LAT[0:13] for transferring memory rows to the selected memory library BK0 may be in a low or high logic state, depending on the memory row selected for the memory operation (i.e., a read operation or a write operation). The read / write signal RD / WR may be in a low or high logic state, depending on whether a read operation or a write operation is performed on the selected memory row.

[0030] Reference Figure 3C Assume that memory library BK0 of the second memory rank R1 is selected and a repair operation is performed to repair the target wafer W7. Due to the repair operation, the repair enable signal TSV_REDUN_MISS is in a low logic state, and the spare wafer selection signal WS_RED is in a high logic state. Since the second memory rank R1 is selected and the target wafer W7 of the second memory rank R1 is selected for the repair operation, the first rank selection signal SID[0] is in a low logic state, the second rank selection signal SID[1] is in a high logic state, the wafer selection signals WS[0:3, 7] transmitted to the dies of wafers W0 to W3 and the target wafer W7 are in a low logic state, and the wafer selection signals WS[4:6] transmitted to the dies of wafers W4 to W6 are in a high logic state. Figure 3C The logical states of the library selection signal BA[0:15], row selection signal RA_LAT[0:13], and read / write signal RD / WR are related to... Figure 3B The signals are the same as those shown in the image, so detailed descriptions of these signals are omitted.

[0031] The target die of target wafer W7 receives the wafer selection signal W7 in a low logic state, while the non-target die of target wafer W7 receives the wafer selection signal W7 in a high logic state. Simultaneously, the spare wafer selection signal WS_RED can select the corresponding spare die in spare wafer W1. Therefore, the target die in target wafer W7 can be replaced by the corresponding spare die in spare wafer W1. In this way, target wafer W7 can perform repair in the die unit using the spare wafer and the repair information signal RE_S1 output by repair information block 310.

[0032] In some embodiments, information about the target die of the target wafer W7 may be stored in the repair information block 310. During normal operation, when accessing the target die of the target wafer W7, access to the failed die can be replaced by accessing the corresponding spare die in the spare wafer W1.

[0033] Figure 4A This is a schematic diagram of a repair information block 410 for repairing a target virtual channel, target memory library, or target row of a target wafer, as shown in an embodiment of the present invention. Assume the target virtual channel is virtual channel PC2, the target memory library is memory library BK0, and the target wafer is wafer W7.

[0034] Repair information block 410 can receive input signal IN_S and generate repair enable signal TSV_REDUN_MISS and repair information signal RE_S2. Figure 4A The input signal IN_S and the repair enable signal TSV_REDUN_MISS of the repair information block 410 are related to... Figure 3AThe input signal IN_S and the repair enable signal TSV_REDUN_MISS of the repair information block 310 are the same, therefore omitted. Figure 4A Detailed description of the input signal IN_S and the repair enable signal TSV_REDUN_MISS.

[0035] When the target wafer W7 is repaired in the virtual channel cell, the repair information signal RE_S2 may include the wafer selection signal WS[0:7], the spare wafer selection signal WS_RED, the virtual channel selection signal PS[0:7], and the spare virtual channel selection signal PS_RED[0:7]. When the target wafer W7 is repaired in the virtual channel cell, the target virtual channel PC2 in the target wafer W7 can be replaced by the corresponding spare virtual channel in the spare wafer W1.

[0036] When the target wafer W7 is repaired in the memory library unit, the repair information signal RE_S2 may further include the library selection signal BA[0:15], in addition to the wafer selection signal WS[0:7], the spare wafer selection signal WS_RED, the virtual channel selection signal PS[0:7], and the spare virtual channel selection signal PS_RED[0:7]. When the target wafer W7 is repaired in the memory library unit, the target memory library BK0 in the target wafer W7 can be replaced by the corresponding spare memory library in the spare wafer W1.

[0037] When the target wafer W7 is repaired in a memory row cell, the repair information signal RE_S2 may further include the row selection signal RA_LAT[0:13], in addition to the wafer selection signal WS[0:7], the spare wafer selection signal WS_RED, the virtual channel selection signal PS[0:7], the spare virtual channel selection signal PS_RED[0:7], and the library selection signal BA[0:15]. When the target wafer W7 is repaired in a memory row cell, the target memory row in the target wafer W7 can be replaced by the corresponding spare memory row in the spare wafer W1.

[0038] The wafer selection signal WS[0:7] is used to select the target wafer (i.e., wafer W7) for repair operation, and the spare wafer selection signal WS_RED is used to select the spare wafer (i.e., wafer W1) for repair operation. The virtual channel selection signal PS[0:7] is used to select the target virtual channel (i.e., virtual channel PC2) for repair operation, and the spare virtual channel selection signal PS_RED[0:7] is used to select the corresponding spare virtual channel in spare wafer W1 for repair operation. The library selection signal BA[0:15] is used to select the target memory library (i.e., memory library BK0) for repair information. The row selection signal RA_LAT[0:13] is used to select the target memory row for repair operation. The library selection signal BA[0:15] and the row selection signal RA_LAT[0:13] can be kept the same as the library selection signal BA[0:15] and the row selection signal RA_LAT[0:13] input to the repair information block 410.

[0039] Repair information block 410 transmits wafer select signals WS[0:7] and virtual channel select signals PS[0:7] to each die of wafers W0 to W7. Backup wafer select signal WS_RED and backup virtual channel select signal PS_RED[0:7] are transmitted to each die of backup wafer W1. Library select signal BA[0:15] and row select signal RA_LAT[0:130] are transmitted to all dies of wafers W0 to W7.

[0040] Figure 4B and Figure 4C This is a waveform diagram of a semiconductor stack wafer used for repairing a target virtual channel, target library, or target row, as shown in an embodiment of the present invention. Figure 4B and Figure 4C The signals shown include Figure 3B and Figure 3C All signals displayed. In addition, Figure 4B and Figure 4C The waveforms of the virtual channel selection signal PS[0:7] and the spare virtual channel selection channel PS_RED[0:7] are further displayed.

[0041] Reference Figure 4B The following signals were fixed: enable signal TSV_REDUN_MISS, rank selection signals SID[0] and SID[1], wafer selection signals WS[0:3] and WS[4:7], spare wafer selection signal WS_RED, library selection signal BA[0:15], row selection signal RA_LAT[0:13], and read / write signal RD / WR. Figure 4B The waveforms in Figure 3B The same as in [the previous text], therefore a detailed description is omitted. Figure 4BThe waveforms of the virtual channel selection signals PS[2] and PS[0:1, 3:7], and the spare virtual channel selection signals PS_RED[2] and PS_RED[0:1, 3:7] are further displayed. Figure 4B In the process, the virtual channel selection signals PS[2] and PS[0:1, 3:7] are in a high logic state, while the backup virtual channel selection signals PS_RED[2] and PS_RED[0:1, 3:7] are in a low logic state. Therefore, neither the virtual channel of the target wafer W7 nor the backup virtual channel of the backup wafer W1 is selected, and the repair operation is not performed.

[0042] Reference Figure 4C The following signals were fixed: enable signal TSV_REDUN_MISS, rank selection signals SID[0] and SID[1], wafer selection signals WS[0:3] and WS[4:7], spare wafer selection signal WS_RED, library selection signal BA[0:15], row selection signal RA_LAT[0:13], and read / write signal RD / WR. Figure 4C The waveforms in Figure 3C The same as in [the previous text], therefore a detailed description is omitted.

[0043] Figure 4C The waveforms of the virtual channel selection signals PS[2] and PS[0:1,3:7], and the spare virtual channel selection signals PS_RED[2] and PS_RED[0:1,3:7] are further displayed. Figure 4C In this process, the virtual channel selection signal PS[2] of the target virtual channel PC2 transmitted to the target wafer W7 is in a low logic state, and the virtual channel selection signals [0:1,3:7] of the non-target virtual channels PC0 to PC1 and PC3 to PC7 transmitted to the target wafer W7 are in a high logic state. The backup virtual channel selection channel PS_RED[2] of the backup virtual channel transmitted to the corresponding target virtual channel PC2 is in a high logic state, and the backup virtual channel selection channel PS_RED[0:1,3:7] of the backup virtual channels PC0 to PC1 and PC3 to PC7 transmitted to the corresponding target wafer W7 is in a low logic state. In this way, the target virtual channel PC2 can be replaced by the corresponding backup virtual channel in the backup wafer W1 during the repair operation. Therefore, the target wafer W7 is repaired in units of virtual channels.

[0044] When the target wafer W7 is repaired using memory libraries as units, the repair information signal RE_S2 further includes library selection signals BA[0] and BA[1:15]. For example... Figure 4CAs shown, the library selection signal BA[0] can be in a high logic state, and the library selection signal BA[1:15] can be in a low logic state. In this way, the target memory library BK0 of the target virtual channel PC2 of the target wafer W7 can be replaced by the corresponding spare memory library in the spare wafer W1 during the repair operation.

[0045] When the target wafer W7 is repaired using memory row units, the repair information signal RE_S2 further includes the row selection signal RA_LAT[0:13]. For example... Figure 4C As shown, the row selection signals RA_LAT[0:13] can be selectively in a low or high logic state, depending on which row in the target memory library is being repaired. Row selection signals transmitted to the target row are in a high logic state, while those transmitted to non-target rows are in a low logic state. Therefore, the target memory row of the target memory library in the target virtual channel of the target wafer can be repaired. In this way, the failed wafer W7 can be repaired using memory line units.

[0046] Figure 5A This is a schematic diagram of a repair information block 510 for repairing a target wafer W7 in units of I / O segments, according to an embodiment of the present invention. The repair information block 510 may include an I / O repair information block 512 and a decoder 514. The I / O repair information block 512 is located in logic die W0 or spare die W1, and the decoder 514 is located in all dies of wafers W0 to W7.

[0047] exist Figure 5A In the I / O repair information block 512, the input signals include column address signals CA_LAT[0:4], and the output signals include column address signals CA_LAT[0:4], I / O segment selection signals CA_SEG[0:31], and spare I / O segment selection signals CA_SEG_RED[0:31]. The output signals of the I / O repair information block 512 are provided to the decoder 514. The decoder 514 of the spare die in the spare wafer W1 can be controlled by the spare I / O segment selection signal CA_SEG_RED[0:31], and the decoders 514 of the dies in wafers W0 and W1 to W7 can be controlled by the I / O segment selection signal CA_SEG[0:31]. Each decoder 514 is used to decode the column address signal CA_LAT[0:4] to generate the column selection signal CSL[0:31] for the repair operation.

[0048] In some embodiments, the column address signal CA_LAT[0:4] output by the I / O repair information block 512 is the same as the column address signal CA_LAT[0:4] input to the I / O repair information block 512. The I / O segment selection signal CA_SEG[0:31] can be used by the target die of the target wafer W7 to control the I / O segments of the target wafer W7. The spare I / O segment selection signal CA_SEG_RED[0:31] can be used by the spare die of the spare wafer W1 to control the spare I / O segments of the spare wafer W1. The I / O segment selection signal CA_SEG[0:31] may be the inverted signal of the spare I / O segment selection signal CA_SEG_RED[0:31].

[0049] Figure 5B and Figure 5C This is a signal waveform diagram of the I / O section SEG0 for repairing the target wafer W7, as shown in an embodiment of the present invention. Figure 5B and Figure 5C The signals displayed include column address signals CA_LAT[0:4], I / O segment selection signals CA_SEG[0] and CA_SEG[1:31], spare I / O segment selection signals CA_SEG_RED[0] and CA_SEG_RED[1:31], column selection signals CSL0[0]@target_die and CSL1[0]-CSL31[0]@target_die, and column selection signals CSL0[0]@reserve_die and CSL1[0]-CSL31[0]@reserve_die. I / O segment selection signals CA_SEG[0] and CA_SEG[1:31] can select I / O segments in target wafer W7 for repair operations. Spare I / O segment selection signals CA_SEG_RED[0] and CA_SEG_RED[1:31] can select spare I / O segments in spare wafer W1 for repair operations. The column selection signals CSL0[0]@target_die and CSL1[0]-CSL31[0]@target_die can select columns in the target die (i.e., target die W7) for repair operations. The column selection signals CSL0[0]@reserve_die and CSL1[0]-CSL31[0]@target_die can select columns in the spare die for repair operations.

[0050] Figure 5B This shows the signal waveform when column repair operation is not enabled. For example... Figure 5BAs shown, all I / O segment selection signals CA_SEG[0] and CA_SEG[1:31] are in a high logic state. Simultaneously, all I / O spare segment selection signals CA_SEG_RED[0] and CA_SEG_RED[1:31] are in a low logic state. Furthermore, column selection signals CSL0[0]@target_die and CSL1[0]-CSL31[0]@target_die are in a high logic state, while column selection signals CSL0[0]@reserve_die and CSL1[0]-CSL31[0]@reserve_die are in a low logic state. Therefore, no repair operation will be performed to repair the target I / O segment in target wafer W7.

[0051] Figure 5C The diagram shows the signal waveforms when the repair operation is enabled to repair the I / O segment SEG0 of wafer W7. (Example:) Figure 5C As shown, the I / O segment selection signal CA_SEG[0] transmitted to the target I / O segment SEG0 in the target wafer W7 is in a low logic state, while the I / O segment selection signal CA_SEG[1:31] transmitted to the non-target segment is in a high logic state. Simultaneously, the spare I / O segment selection signal CA_SEG_RED[0] transmitted to the spare I / O segment corresponding to the target I / O segment SEG0 is in a high logic state, while the I / O segment selection signal CA_SEG_RED[1:31] transmitted to the spare I / O segment corresponding to the non-target I / O segment is in a low logic state. Therefore, the target I / O segment SEG0 in the target wafer W7 and the spare I / O segment SEG0 in the spare wafer W1 are selected for repair operations.

[0052] Figure 5C Further, it is shown that the column selection signal CSL0[0]@target_die transmitted to the target I / O segment is in a low logic state, while the column selection signals CSL1[0]-CSL31[0]@target_die transmitted to the non-target I / O segment are in a high logic state. At the same time, the spare column selection signal CSL0[0]@reserve_die is in a high logic state, while the spare column selection signals CSL1[0]-CSL31[0]@reserve_die are in a low logic state. Therefore, the target I / O segment in the target die and the spare I / O segment in the spare die are selected for repair operation. The target I / O segment in the target die of the target wafer (i.e., wafer W7) can be replaced by the spare I / O segment column in the spare die of the spare wafer (i.e., wafer W1). In this way, the target wafer W7 can be repaired on a unit basis of I / O segments.

[0053] Figure 5DThis illustrates the repair operation of replacing the target I / O section SEG0 of the target wafer W7 with the corresponding spare I / O section SEG0 of the spare wafer W1. For example... Figure 5D As shown, wafers W1 and W7 each include multiple I / O segments SEG0 to SEG31. Each of the I / O segments SEG0 to SEG31 can receive an input column selection signal CLxx[0:31], where xx represents the I / O segment in I / O segments SEG0 to SEG31. For example, xx = 00 represents I / O segment SEG0, and xx = 31 represents I / O segment SEG31. Each of the I / O segments SEG0 to SEG31 can output data MDQxx[0:7]. The data MDQxx[0:7] output from I / O segments SEG0 to SEG31 can be combined to form the data DQ_TSV[0:255] output from I / O segments SEG0 to SEG31.

[0054] like Figure 5D As shown, when the target I / O segment SEG0 of the target wafer W7 is replaced by the corresponding I / O segment SEG0 of the spare wafer W1, the data output by the target wafer W7's I / O segment SEG0 will be replaced by the data MDQ00[0:7] output by the spare wafer W1's I / O segment SEG0. In this way, the target wafer W7 can be repaired on a unit basis, either an I / O segment or an I / O unit.

[0055] In summary, in the embodiments of the present invention, the semiconductor stack wafer includes a spare wafer for repairing the target wafer (or failed wafer) in the semiconductor stack wafer. The repair operation can be performed using repair information blocks located on the logic wafer or the spare wafer in the semiconductor stack wafer. In this way, the yield of the semiconductor stack wafer can be improved. Furthermore, the repair operation can be performed at the die level, virtual channel level, memory bank level, or memory behavior level to enhance the flexibility of the repair mechanism. The I / O segments of the target wafer can also be repaired, further enhancing the flexibility of the repair mechanism.

[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor stacked wafer, comprising: Multiple wafers, each comprising multiple dies, the multiple wafers including logic wafers and target wafers; A spare wafer is used to repair the target wafer among the plurality of wafers according to a repair enable signal and a repair information signal; The repair information block is located in the spare wafer or the logic wafer and is used to input input signals and output the repair enable signal and the repair information signal according to the input signals.

2. The semiconductor stacked wafer according to claim 1, wherein When the repair enable signal is in the first logic state, a repair operation is performed to repair the disabled target wafer; When the repair enable signal is in the second logic state, the repair operation is performed to repair the enabled target wafer.

3. The semiconductor stacked wafer according to claim 2, wherein The target wafer is repaired on a grain-by-grain basis, and In the repair operation, the target die in the target wafer is replaced by a spare die in the spare wafer.

4. The semiconductor stacked wafer according to claim 3, wherein The input signals include a rank selection signal, a library selection signal, and a row selection signal, and The repair information signal includes a target wafer selection signal, a spare wafer selection signal, a library selection signal, and a row selection signal, wherein the target wafer selection signal is used to select the target wafer for the repair operation, and the spare wafer selection signal is used to select the spare wafer for the repair operation.

5. The semiconductor stacked wafer according to claim 4, wherein The repair information block transmits the target wafer selection signal to the die of the wafer, and the repair information block transmits the spare wafer selection signal to the spare die of the spare wafer. The repair information block transmits the library selection signal and the row selection signal to the die of the wafer and the spare die of the spare wafer.

6. The semiconductor stacked wafer according to claim 4, wherein In the repair operation of repairing the target wafer, the spare wafer selection signal is in the first logic state, the target wafer selection signal transmitted to the target die of the target wafer is in the second logic state, and the target wafer selection signal transmitted to the non-target die of the target wafer is in the first logic state.

7. The semiconductor stacked wafer according to claim 4, wherein When the repair operation for repairing the target wafer is disabled, the spare wafer selection signal is in the second logic state, and the target wafer selection signal transmitted to all dies of the target wafer is in the first logic state.

8. The stacked wafer according to claim 2, wherein Each of the grains includes multiple virtual channels. The target wafer is repaired using virtual channels as units, and In the repair operation, the target virtual channel of the target wafer is replaced by the backup virtual channel in the backup wafer.

9. The semiconductor stacked wafer according to claim 2, wherein Each of the grains includes multiple virtual channels. Each of the virtual channels includes multiple memory libraries. The target wafer is repaired using memory libraries as units, and The target memory library of the target virtual channel of the target wafer is replaced by the backup memory library in the backup wafer during the repair operation.

10. The semiconductor stacked wafer according to claim 2, wherein Each of the grains includes multiple virtual channels. Each of the virtual channels includes multiple memory libraries. Each of the memory libraries comprises multiple memory rows. The target wafer is repaired using memory behavior units, and The target memory row of the target memory library of the target virtual channel of the target wafer is replaced by the spare memory row of the spare wafer during the repair operation.

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