Etching method of wafer

Abstract

The application relates to a wafer etching method, which comprises the following steps: providing a wafer, wherein the wafer comprises a substrate, an epitaxial layer, a first oxide layer, a first hard mask layer and a shallow trench isolation structure which penetrates the first oxide layer and the first hard mask layer and extends to the epitaxial layer, and the epitaxial layer, the first oxide layer, the first hard mask layer and the shallow trench isolation structure are sequentially stacked on one side of the substrate; forming a porous medium layer on the side of the substrate away from the epitaxial layer; performing a first wet etching treatment on the wafer to remove the first hard mask layer; and performing a second wet etching treatment on the wafer to remove the porous medium layer. The wafer etching method utilizes the capturing ability of the porous medium layer to silicon ions, so that the free silicon ions in the etchant are crystallized and precipitated on the surface of the porous medium layer, thereby improving the cleanliness of the surface of the side of the wafer provided with the shallow trench isolation structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a wafer etching method. BACKGROUND

[0002] Shallow Trench Isolation (STI) technology is a commonly used isolation technology in advanced semiconductor processes. STI technology usually fills the trench between active regions in a semiconductor device with insulating silicon oxide to form an isolation structure between semiconductor devices. For example, the process of manufacturing a shallow trench isolation structure includes forming a silicon oxide layer and a silicon nitride film on an epitaxial substrate using a furnace tube process, patterning the film, then forming a trench in the epitaxial substrate by a dry etching process, and filling the trench with deposited oxide for isolating silicon material, and finally removing the silicon nitride mask by a wet etching process.

[0003] During the wet etching process of the silicon nitride layer, a high etching selectivity ratio of silicon nitride / silicon oxide is required to reduce or avoid etching damage to the silicon oxide layer while removing the silicon nitride layer. However, the wet etching process of the silicon nitride layer usually uses high-temperature phosphoric acid as an etchant. Generally, the etching selectivity ratio of silicon nitride and silicon oxide can be increased by introducing expensive additives, but this method is costly and polluting. While the cost burden may not be significant in the circulating liquid tank of a tank-type device, the cost burden increases linearly when using a single-piece device for advanced wet processes. SUMMARY

[0004] Therefore, it is necessary to provide a wafer etching method to improve the surface cleanliness of the side of the wafer on which the shallow trench isolation structure is provided while removing the first hard mask layer on the surface of the wafer.

[0005] The present application provides a wafer etching method, comprising:

[0006] providing a wafer, the wafer comprising a substrate, an epitaxial layer, a first oxide layer, a first hard mask layer, and a shallow trench isolation structure extending through the first oxide layer and the first hard mask layer and into the epitaxial layer, which are sequentially stacked on one side of the substrate;

[0007] forming a porous medium layer on the side of the substrate away from the epitaxial layer;

[0008] performing a first wet etching process on the wafer to remove the first hard mask layer;

[0009] performing a second wet etching process on the wafer to remove the porous medium layer.

[0010] In one of the embodiments, the first wet etching process of the wafer includes:

[0011] The wafer is arranged in the etching tank, and the etching agent in the etching tank is fully immersed in all the wafers to remove the first hard mask layer in all the wafers.

[0012] In one of the embodiments, the surfaces of all the wafers are parallel to each other, and the surfaces of the shallow trench isolation structures formed in all the wafers are oriented in the same direction.

[0013] In one of the embodiments, the etching agent used in the first wet etching process includes phosphoric acid, and the etching agent used in the second wet etching process includes hydrofluoric acid.

[0014] In one of the embodiments, after the porous medium layer is formed, before the first wet etching process is performed, the etching method of the wafer further includes:

[0015] The surface of the porous medium layer is modified to have strong polar groups on the surface away from the substrate; wherein the strong polar groups include at least one of hydroxyl and amine groups.

[0016] In one of the embodiments, the material of the porous medium layer includes porous silicon oxide, and the porosity of the porous medium layer ranges from 20% to 60%.

[0017] In one of the embodiments, the formation of the shallow trench isolation structure includes:

[0018] The substrate is provided, and the epitaxial layer is formed on one side of the substrate;

[0019] The first oxide layer is formed on the side of the epitaxial layer away from the substrate;

[0020] The first hard mask layer is formed on the side of the first oxide layer away from the epitaxial layer;

[0021] The patterned photoresist layer is formed on the side of the first hard mask layer away from the first oxide layer;

[0022] The first hard mask layer, the first oxide layer, and the epitaxial layer are etched with the photoresist layer as a mask to form an isolation trench extending through the first hard mask layer and the first oxide layer and into the epitaxial layer;

[0023] The isolation material is filled in the isolation trench to form the shallow trench isolation structure including the isolation trench and the isolation material.

[0024] In one of the embodiments, the first oxide layer is formed by a first furnace tube process, and the process of forming the first oxide layer further comprises:

[0025] forming a second oxide layer on a side of the substrate away from the epitaxial layer;

[0026] forming the first hard mask layer by a second furnace tube process, and the process of forming the first hard mask layer further comprises:

[0027] forming a second hard mask layer on a side of the second oxide layer away from the substrate.

[0028] In one of the embodiments, after forming the shallow trench isolation structure, before forming the porous medium layer on a side of the substrate away from the epitaxial layer, the etching method of the wafer further comprises:

[0029] removing the second oxide layer and the second hard mask layer.

[0030] In one of the embodiments, the second oxide layer and the second hard mask layer are removed by a wet etching process, the etchant of the wet etching process comprises hydrofluoric acid, and the concentration of the hydrofluoric acid ranges from 1% to 49%.

[0031] The unexpected effect of the present application is that, by forming the porous medium layer on a side of the substrate away from the epitaxial layer, the porous medium layer can attract free silicon ions in the etchant during the first wet etching process to remove the first hard mask layer, so that the silicon ions crystallize and precipitate on the surface of the porous medium layer, which is beneficial to improve the cleanliness of the surface of the wafer on which the shallow trench isolation structure is arranged. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0033] Figure 1 The flow chart of the etching method of the wafer provided in one of the embodiments of the present application.

[0034] Figure 2 The structure schematic diagram corresponding to the step of providing the wafer in the etching method of the wafer provided in one of the embodiments of the present application.

[0035] Figure 3A structure diagram corresponding to a step of removing the second oxide layer and the second hard mask layer in the wafer etching method provided by one of the embodiments of the present application.

[0036] Figure 4 A structure diagram corresponding to a step of forming a porous medium layer on a side of the substrate away from the epitaxial layer in the wafer etching method provided by one of the embodiments of the present application.

[0037] Figure 5 A structure diagram corresponding to a step of modifying the surface of the porous medium layer in the wafer etching method provided by one of the embodiments of the present application.

[0038] Figure 6 A structure diagram corresponding to a step of removing the first hard mask layer by performing a first wet etching treatment on the wafer in the wafer etching method provided by one of the embodiments of the present application.

[0039] Figure 7 A structure diagram corresponding to a step of immersing a batch of wafers in an etchant in an etching tank in the wafer etching method provided by one of the embodiments of the present application.

[0040] Figure 8 A structure diagram corresponding to a step of removing the porous medium layer by performing a second wet etching treatment on the wafer in the wafer etching method provided by one of the embodiments of the present application.

[0041] In the drawings, reference numerals include: 100 - substrate; 101 - epitaxial layer; 110 - first oxide layer; 111 - second oxide layer; 120 - first hard mask layer; 121 - second hard mask layer; 130 - shallow trench isolation structure; 131 - isolation trench; 140 - porous medium layer; A - etching tank; W - wafer. DETAILED DESCRIPTION

[0042] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terminology used in the specification of the present application is only for the purpose of describing specific embodiments and is not intended to limit the present application.

[0044] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, e.g., a first doped type can be P-type and a second doped type can be N-type, or a first doped type can be N-type and a second doped type can be P-type.

[0045] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other directions (for example, rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0046] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, as used herein, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0047] Figure 1 A flow chart of the wafer etching method is provided for one of the embodiments of the present application. The wafer etching method provided by one of the embodiments of the present application comprises the following steps S01 to S04.

[0048] Step S01: providing a wafer, the wafer comprising a substrate, an epitaxial layer, a first oxide layer, a first hard mask layer, and a shallow trench isolation structure penetrating through the first oxide layer and the first hard mask layer and extending into the epitaxial layer, which are sequentially stacked on one side of the substrate.

[0049] Step S02: forming a porous medium layer on the side of the substrate away from the epitaxial layer.

[0050] Step S03: performing a first wet etching treatment on the wafer to remove the first hard mask layer.

[0051] It should be noted that during the first wet etching treatment of the wafer, the wafer needs to be completely immersed in the etchant so that all surfaces of the wafer are in contact with the etchant, so as to ensure that in the process of removing the first hard mask layer, the porous medium layer can attract free silicon ions, and the silicon ions can crystallize and precipitate on the surface of the porous medium layer, thereby reducing or avoiding the precipitation of silicon ions on the side surface of the wafer where the porous medium layer is not provided.

[0052] Step S04: performing a second wet etching treatment on the wafer to remove the porous medium layer.

[0053] As described above, the wafer etching method forms a porous medium layer on the side of the substrate away from the epitaxial layer, and performs two wet etching treatments on the wafer. In the process of removing the first hard mask layer and the porous medium layer, the porous medium layer can attract free silicon ions in the etchant, and the silicon ions can crystallize and precipitate on the surface of the porous medium layer, thereby facilitating the improvement of the cleanliness of the side surface of the wafer where the shallow trench isolation structure is provided.

[0054] Reference is made to Figure 2In one embodiment, the forming of the shallow trench isolation structure 130 includes: providing the substrate 100, forming the epitaxial layer 101 on one side of the substrate 100; forming the first oxide layer 110 on a side of the epitaxial layer 101 away from the substrate 100; forming the first hard mask layer 120 on a side of the first oxide layer 110 away from the epitaxial layer 101; forming a patterned photoresist layer (not shown in the figure) on a side of the first hard mask layer 120 away from the first oxide layer 110; etching the first hard mask layer 120, the first oxide layer 110 and the epitaxial layer 101 with the photoresist layer as a mask to form the isolation trench 131 extending through the first hard mask layer 120 and the first oxide layer 110 and into the epitaxial layer 101; and filling the isolation trench 131 with an isolation material to form the shallow trench isolation structure 130 including the isolation trench 131 and the isolation material.

[0055] It should be noted that in other embodiments of the present application, the specific forming method of the shallow trench isolation structure can be adjusted according to actual needs, and appropriate process steps and process methods are selected, and the present application does not limit this.

[0056] In one embodiment, the photoresist layer is removed after the forming of the isolation trench and before the filling of the isolation material in the isolation trench. Optionally, the photoresist layer is removed by using a gray ash process and a wet cleaning process.

[0057] In one embodiment, an epitaxial growth process is used to form the epitaxial layer on one side of the substrate. In other embodiments of the present application, other common process methods can also be used to form the epitaxial layer, and the present application does not limit this.

[0058] Continuing to refer to Figure 2 In one embodiment, the first furnace tube process is used to form the first oxide layer 110, and the second furnace tube process is used to form the first hard mask layer 120. Further, in the process of forming the first oxide layer 110 by using the first furnace tube process, a second oxide layer 111 is also formed on a side of the substrate 100 away from the epitaxial layer 101; and in the process of forming the first hard mask layer 120 by using the second furnace tube process, a second hard mask layer 121 is also formed on a side of the second oxide layer 111 away from the substrate 100. Optionally, the materials of the first oxide layer 110 and the second oxide layer 111 both include silicon oxide, and the materials of the first hard mask layer 120 and the second hard mask layer 121 both include silicon nitride.

[0059] Referring to Figure 3 In one embodiment, after the forming of the shallow trench isolation structure 130, before the forming of the porous medium layer on a side of the substrate 100 away from the epitaxial layer 101, the etching method of the wafer further includes: removing the second oxide layer 111 and the second hard mask layer 121.

[0060] In one of the embodiments, the second oxide layer and the second hard mask layer are removed by using a wet etching process, wherein the etchant of the wet etching process comprises hydrofluoric acid (HF), and the concentration of the hydrofluoric acid ranges from 1% to 49%.

[0061] Referring to Figure 4 In one of the embodiments, when the porous medium layer 140 is formed on the side of the substrate 100 away from the epitaxial layer 101, the porous medium layer 140 can be formed by using a chemical vapor deposition (CVD) process, or can be formed by using other common deposition methods. Optionally, the material of the porous medium layer 140 comprises porous silicon oxide.

[0062] In one of the embodiments, the porosity of the porous medium layer ranges from 20% to 60%. It should be noted that in other embodiments of the present application, the material of the porous medium layer can be selected from other common materials with a porosity meeting the requirements according to actual process requirements, and the present application does not limit this.

[0063] Referring to Figure 5 In one of the embodiments, after the porous medium layer 140 is formed, the etching method of the wafer further comprises: performing a modification treatment on the surface of the porous medium layer 140, so that the surface of the porous medium layer 140 away from the substrate 100 has strong polar groups. Optionally, the strong polar groups comprise at least one of hydroxyl and amine groups.

[0064] It should be noted that the modification treatment on the surface of the porous medium layer can improve the capture ability of the porous medium layer to silicon ions, so as to absorb the free silicon ions in the etchant in the next wet etching process.

[0065] Referring to Figure 5 and Figure 6 In one of the embodiments, the wafer is subjected to a first wet etching treatment to remove the first hard mask layer 120. Optionally, the etchant of the first wet etching treatment comprises phosphoric acid (H3PO4).

[0066] Referring to Figure 6 and Figure 7 In one of the embodiments, the first wet etching treatment can be performed by using a tank cleaning device. Specifically, the process of performing the first wet etching treatment on the wafer W by using the tank cleaning device comprises: arranging a batch of wafers W in the etching tank A at intervals, so that the etchant in the etching tank A completely immerses all the wafers W, to remove the first hard mask layer 120 in all the wafers W.

[0067] In one embodiment, the surfaces of all the wafers are parallel to each other, and the surfaces of all the wafers on which the shallow trench isolation structures are formed are oriented in the same direction. For example, the surface of a wafer on which the shallow trench isolation structures are formed is defined as the front surface of the wafer, and the surface of the wafer on which the porous medium layer is formed is defined as the back surface of the wafer. In a batch of parallel wafers, the front surfaces of all the wafers are arranged in the same direction, such that the front surface of a current wafer is opposite to the back surface of a previous wafer. Thus, the free silicon ions accumulated on the front surface of the current wafer can be attracted by the porous medium layer formed on the back surface of the previous wafer, and the excess silicon ions can be crystallized and precipitated on the porous medium layer on the back surface of the previous wafer, thereby ensuring that the front surface of the current wafer remains clean. The free silicon ions accumulated on the front surface of the current wafer are the silicon ions generated in the process of removing the first hard mask layer by phosphoric acid etchant.

[0068] In one embodiment, when all the wafers are arranged in the etching tank with their surfaces parallel to each other, all the wafers are arranged in a straight line. Thus, the front surface of the wafer at the first position in the queue (hereinafter referred to as the first wafer) is not opposite to the back surface of any other wafer. Since the front surface of the first wafer is not arranged with any other wafer, more free silicon ions are accumulated on the front surface of the first wafer. Therefore, a baffle formed with a porous medium layer can be arranged on the front surface of the first wafer to ensure that the free silicon ions accumulated on the front surface of the first wafer can be precipitated on the surface of the porous medium layer on the baffle, thereby improving the cleanliness of the front surface (i.e., the surface on which the shallow trench isolation structures are formed) of each wafer in the etching tank.

[0069] Referring to Figure 8 In one embodiment, the wafer is subjected to a second wet etching process to remove the porous medium layer 140. Optionally, the etchant used in the second wet etching process includes hydrofluoric acid (HF).

[0070] In one embodiment, the wafer can be subjected to the second wet etching process by using a single-wafer cleaning device. Since the single-wafer cleaning device can use different etchants to treat the front and back surfaces of the wafer respectively, during the process of subjecting the wafer to the second wet etching process by using the single-wafer cleaning device, hydrofluoric acid can be used to treat the surface of the wafer on which the porous medium layer is formed to remove the porous medium layer, and water or other cleaning agents can be used to clean the surface of the wafer on which the shallow trench isolation structures are formed to further improve the cleanliness of the surface of the wafer on which the shallow trench isolation structures are formed, thereby facilitating the smooth progress of subsequent process procedures.

[0071] The unexpected effect of the present application is that: by forming a porous medium layer on the side of the substrate away from the epitaxial layer, in the process of removing the first hard mask layer by the first wet etching treatment, the porous medium layer can attract free silicon ions in the etchant, and the silicon ions can crystallize and precipitate on the surface of the porous medium layer, which is beneficial to improve the cleanliness of the surface of the side of the wafer provided with the shallow trench isolation structure.

[0072] In the description of the present specification, the description of the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in combination with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0073] The technical features of the above-mentioned embodiments can be combined arbitrarily, and in order to make the description simple, all possible combinations of the technical features of the above-mentioned embodiments are not described, however, as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application.

[0074] The above-mentioned embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method of etching a wafer, the method comprising: The method comprises the following steps: providing a wafer, the wafer comprising a substrate, an epitaxial layer, a first oxide layer, a first hard mask layer, and a shallow trench isolation structure formed in the epitaxial layer through the first oxide layer and the first hard mask layer, sequentially stacked on one side of the substrate; forming a porous medium layer on the side of the substrate away from the epitaxial layer, the material of the porous medium layer comprising porous silicon oxide, and the porosity of the porous medium layer ranging from 20% to 60%; performing a first wet etching process on the wafer to remove the first hard mask layer; performing a second wet etching process on the wafer to remove the porous medium layer; the first wet etching process comprises the following steps: arranging a batch of the wafers in the etching tank at intervals, so that the etchant in the etching tank completely immerses all the wafers to remove the first hard mask layer in all the wafers; wherein the surfaces of all the wafers are parallel to each other, and the surfaces of the shallow trench isolation structures formed in all the wafers are oriented in the same direction.

2. The method of claim 1, wherein The etchant used in the first wet etching process comprises phosphoric acid, and the etchant used in the second wet etching process comprises hydrofluoric acid.

3. The method of claim 1, wherein the etching is performed by a dry etching method. After forming the porous medium layer and before performing the first wet etching process, the etching method of the wafer further comprises the following steps: performing a modification process on the surface of the porous medium layer, so that the surface of the porous medium layer away from the substrate has strong polar groups; wherein the strong polar groups comprise at least one of hydroxyl and amine groups.

4. The method of claim 1, wherein The formation process of the shallow trench isolation structure comprises the following steps: providing the substrate, and forming the epitaxial layer on one side of the substrate; forming the first oxide layer on the side of the epitaxial layer away from the substrate; forming the first hard mask layer on the side of the first oxide layer away from the epitaxial layer; forming a patterned photoresist layer on the side of the first hard mask layer away from the first oxide layer; etching the first hard mask layer, the first oxide layer, and the epitaxial layer with the photoresist layer as a mask to form an isolation trench through the first hard mask layer and the first oxide layer and extending into the epitaxial layer; filling the isolation trench with an isolation material to form the shallow trench isolation structure comprising the isolation trench and the isolation material.

5. The method of claim 4, wherein the etching is performed by a dry etching method. The first oxide layer is formed by a first furnace tube process, and the process of forming the first oxide layer further comprises the following steps: forming a second oxide layer on the side of the substrate away from the epitaxial layer; The first hard mask layer is formed by a second furnace tube process, and the process of forming the first hard mask layer further comprises the following steps: forming a second hard mask layer on the side of the second oxide layer away from the substrate.

6. The method of claim 5, wherein the etching is performed by a dry etching method. After forming the shallow trench isolation structure and before forming the porous medium layer on the side of the substrate away from the epitaxial layer, the etching method of the wafer further comprises the following steps: removing the second oxide layer and the second hard mask layer.

7. The method of claim 6, wherein the etching is performed by a dry etching method. The second oxide layer and the second hard mask layer are removed by a wet etching process, the etchant of the wet etching process comprising hydrofluoric acid, and the concentration of the hydrofluoric acid ranging from 1% to 49%.

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