Chip fusion welding packaging structure with uniform pressure distribution and heat energy release functions

Abstract

The invention discloses a chip fusion welding packaging structure with uniform pressure distribution and heat energy release functions, and relates to the technical field of chip fusion welding packaging, the chip fusion welding packaging structure specifically comprises a substrate and a chip, a plurality of groups of gold wires are arranged on a substrate bonding pad, and the other ends of the gold wires are fixed with the position of a chip bonding pad through a wire feeding mechanism on a bonding machine; according to the invention, the honeycomb groove layer is arranged on the back of the chip, and the prefabricated silver layer which is in mirror image matching with the honeycomb groove layer is arranged on the pre-plated gold tin solder layer on the top of the substrate to form a three-dimensional interlocking structure, so that the structure can disperse the welding pressure to the side wall of the groove, avoid local stress concentration and remarkably improve the uniformity of interface pressure distribution; moreover, through the honeycomb heat conduction network and the three-dimensional heat conduction network, the heat energy release efficiency is optimized, directional release of heat energy is achieved, meanwhile, the surface of the groove is subjected to multi-layer functionalization treatment, a triple interface treatment process is adopted, and the interface performance and the heat conduction efficiency are remarkably improved.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of chip melting welding packaging, in particular to a chip melting welding packaging structure with pressure uniform distribution and heat energy release functions. BACKGROUND

[0002] Chip melting welding packaging is a key interconnection technology in semiconductor packaging, and is mainly used for electrically and mechanically connecting input pads / output pads on a chip with corresponding pads on a packaging substrate or a lead frame, a core principle of which is to use a metal or an alloy with a lower melting point than the chip and the substrate to melt, wet and connect the metalized surfaces on the two sides through heating, and to form reliable metallurgical bonding after cooling, and it is emphasized that the melting welding is specially used for a process in which solder is completely liquefied.

[0003] For main packaging forms of the chip, there are flip chip and wire bonding, the flip chip is a pinless structure and generally contains a circuit unit and is designed to be electrically and mechanically connected to a circuit through a proper number of tin balls on a surface, and the wire bonding is another common technology for connecting electrodes of a semiconductor device chip surface and external leads of a substrate or a lead frame through heat, pressure and ultrasonic energy, so as to realize electrical interconnection between the chip and the substrate and information intercommunication between the chips.

[0004] Usually, the chip is fixed on the substrate by using an adhesive, and a chip bonding area of the substrate is usually a metal pad, and special treatment is usually performed on the metal pad to improve bonding strength and reliability, such as silver plating, gold plating or coating a layer of special bondable material, and the chip back surface and the substrate are mechanically fixed and thermally conductive, which is particularly important for subsequent packaging, and the chip back surface and the substrate are connected, and uneven distribution of welding pressure and a planar contact mode easily lead to local stress concentration, thereby affecting welding quality and reliability.

[0005] Secondly, heat energy release efficiency is low, and a heat conduction path is limited, so it is difficult to quickly guide heat of a chip hot spot to the substrate, resulting in poor heat dissipation effect and insufficient interface bonding strength, and a solder filling method is difficult to realize precise filling and uniform distribution of solder, so that defects such as holes and cracks exist in a welding interface, and thereby mechanical strength and thermal stability of a welding joint are affected.

[0006] Therefore, the application provides a chip melting welding packaging structure with pressure uniform distribution and heat energy release functions. SUMMARY

[0007] The application aims to provide a chip melting welding packaging structure with pressure uniform distribution and heat energy release functions, and solve the problems mentioned in the background.

[0008] In order to achieve the above object, the present application provides the following technical scheme: a chip melting welding packaging structure with pressure uniform distribution and heat energy release function, comprising a substrate and a chip, a plurality of gold wires are arranged on the substrate pad, and the other end of the gold wire is fixed with the chip pad position through the wire feeding mechanism on the bonder;

[0009] The gap between the substrate and the chip is pre-plated with a gold-tin solder layer on the top of the substrate, the top of the gold-tin solder layer is provided with a prefabricated silver layer through template printing, and the gap between the chip and the substrate is provided with a honeycomb groove layer on the back of the chip.

[0010] Further, the preparation method of the honeycomb groove layer in the chip melting welding packaging structure with pressure uniform distribution and heat energy release function is:

[0011] S1: chip back surface pretreatment

[0012] Diamond grinding wheel is used for wafer grinding, the thickness of the ground wafer is controlled to be 195-205 mu m, then the ground wafer is put into a vacuum chamber and argon is introduced, plasma is generated by applying radio frequency power of 300 W for wafer cleaning, and the processing time is controlled to be 115-125 s;

[0013] S2: honeycomb groove laser etching

[0014] PECVD is used to deposit SiN x The filling ratio of silane to ammonia in the deposition parameters is controlled to be 3:1, the temperature is controlled to be 200 DEG C, then laser direct writing exposure is carried out, a regular hexagonal matrix is formed on the back side of the chip, and the regular hexagonal matrix groove formed on the back side of the chip is subjected to depth reactive ion etching;

[0015] S3: groove surface functionalization treatment

[0016] Titanium nitride coating is formed on the bottom of the regular hexagonal matrix groove on the back side of the chip by magnetron sputtering, the thickness is controlled to be 50 nm, then silicon dioxide gradient transition layer is deposited in the regular hexagonal matrix groove on the back side of the chip by PECVD, finally OTS monolayer is constructed on the top layer of the regular hexagonal matrix groove on the back side of the chip by liquid phase self-assembly, after ending, copper composite micropillar is formed at the top of the regular hexagonal matrix groove on the back side of the chip by electrochemical deposition, the diameter is 5 mu m, and the height is 10 mu m;

[0017] S4: precise solder filling

[0018] SAC305 and 0.2wt% Cu nanoparticles are used to prepare solder paste, and the solder paste is coated by steel mesh and doctor blade, and then multi-stage reflow welding is carried out;

[0019] S5: interface strengthening treatment

[0020] The back of the chip is ultrasonically vibrated in a vacuum environment, then the back of the chip is scanned by a YAG laser, and the back of the chip is chemically mechanically polished by using silica colloid as a polishing liquid.

[0021] Further, the side of the chip is formed into a regular hexagonal matrix with a side length of 20-50 mu m and a pitch of 5-10 mu m.

[0022] Further, the depth of the regular hexagonal matrix groove formed on the back of the chip is etched by reactive ion etching, which includes main etching and passivation alternation, sulfur hexafluoride is introduced into the vacuum chamber as etching gas, plasma is formed by high-frequency power excitation, chemical reaction occurs between the plasma and the silicon material on the surface of the regular hexagonal matrix groove, the reaction time is 8s, then carbon octafluoride gas is introduced, the reaction time is 5s, and the cycle number is controlled to be 30 times.

[0023] Further, the top of the substrate is pre-plated with a gold-tin solder layer, the bonding temperature is controlled to be 220 DEG C, the bonding time is 120s, and a pre-prepared silver layer is further arranged on the gold-tin solder layer on the top of the substrate.

[0024] Further, the preparation method of the pre-prepared silver layer on the gold-tin solder layer on the top of the substrate is:

[0025] Template printing, a stainless steel 300-mesh screen is used to cooperate with silver paste to form a honeycomb array mirror image pattern on the top of the gold-tin solder layer, which matches the chip groove;

[0026] Pre-sintering, the sintering temperature is controlled to be 180-220 DEG C, the temperature rise is 2 DEG C / s, the holding time is 120s, and the filling ratio of sintering protective gas nitrogen and hydrogen is controlled to be 95:5.

[0027] Further, the regular hexagonal matrix groove on the back of the chip is divided into a high-density area and a low-density area, wherein the regular hexagonal matrix groove in the high-density area is 1200-2000 / mm2, and the regular hexagonal matrix groove in the low-density area is 300-800 / mm2.

[0028] Compared with the prior art, the beneficial effects of the present application are:

[0029] 1. In the present application, the regular hexagonal honeycomb groove is etched on the back of the chip, the surface of the substrate is pre-prepared with a honeycomb-shaped silver layer matched with the mirror image by template printing, the interface performance is enhanced by multi-layer functional treatment in the groove, the honeycomb structure disperses the welding pressure to the groove sidewall, avoids local stress concentration, significantly improves the uniformity of interface pressure distribution, and after the molten solder fills the groove, a mortise and tenon type three-dimensional interlocking structure is formed, which combines the anchoring effect of the copper micro column, and greatly enhances the bonding strength and shear resistance of the chip and the substrate.

[0030] 2. In this invention, a honeycomb thermal conductive network is set up to optimize the heat release efficiency. The grooves are filled with high thermal conductivity nano-silver paste, and a honeycomb silver layer is superimposed on the pre-plated gold-tin solder layer of the substrate to form a continuous thermal conductive path. The thermal expansion coefficient matching is optimized through gradient material design to reduce thermal stress. The honeycomb structure can accommodate more high thermal conductivity materials and build a three-dimensional thermal conductive network to quickly guide the heat from the chip hotspots to the substrate. The triple interface treatment of ultrasonic micro-vibration, YAG laser scanning and chemical mechanical polishing is used to eliminate micro-voids and defects and improve the interface heat conduction efficiency. The high and low density groove partition design is specifically adapted to the chip heat source distribution to achieve directional heat release and improve the heat dissipation effect. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the overall structure of the chip fusion welding and packaging structure with pressure uniform distribution and heat release functions of the present invention.

[0032] Figure 2 This is a flowchart illustrating the fabrication process of the honeycomb groove layer in the chip fusion welding packaging structure with pressure uniformity and heat release functions of the present invention.

[0033] Figure 3 This is a schematic diagram of the distribution of the honeycomb groove layer on the back side of the chip of the present invention;

[0034] Figure 4 This is a schematic cross-sectional view of the functionalization treatment of the inner surface of the honeycomb groove layer on the back side of the chip of the present invention.

[0035] In the diagram: 100, substrate; 200, chip; 300, honeycomb groove layer; 400, gold wire; 500, pre-formed silver layer; 600, gold-tin solder layer. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] Please see Figures 1-4 The present invention provides a technical solution:

[0038] like Figure 1As shown, the chip 200 fusion welding packaging structure with pressure distribution and heat release functions of the present invention adopts a three-dimensional interlocking structure. A honeycomb groove is etched on the back of the chip 200 and combined with the nano-silver layer on the substrate 100 to form a "three-dimensional interlocking" structure, which breaks through the traditional planar contact mode. The sidewalls of the honeycomb groove greatly increase the actual contact area between the chip 200 and the nano-silver TIM, far exceeding the planar contact. At the same time, after the molten or sintered nano-silver fills the groove, it solidifies to form a "mortise and tenon" structure, providing additional mechanical fixing and enhancing interface stability.

[0039] The high-performance nano-silver sintering is combined with the microstructure on the back of the chip 200 to maximize the use of the high thermal conductivity of nano-silver. The groove structure helps to accommodate more nano-silver material and guides its filling and formation of a better thermal conduction path. This solution realizes both mechanical fixation and thermal management functions in the same interface structure.

[0040] The specific steps for fabricating the honeycomb groove layer 300 on the back side of the chip 200 are as follows: Figure 2 As shown, firstly, a wafer with a standard thickness is selected as the material for chip 200. A diamond grinding wheel is used to grind the wafer, and the wafer thickness is precisely controlled within the range of 195-205μm to ensure the flatness of the back side of chip 200 and the accuracy of subsequent processing, while not affecting the subsequent circuit etching of the front silicon wafer.

[0041] After grinding, the wafer is quickly transferred to a vacuum chamber, high-purity argon gas is introduced, and 300W of radio frequency power is applied to generate plasma to clean the wafer surface. The processing time is strictly controlled within 120 seconds to remove surface impurities and oxides, improve the cleanliness and activity of the back side of chip 200. By precisely controlling the grinding thickness and plasma cleaning parameters, the flatness and cleanliness of the back side of chip 200 can be significantly improved, providing a good foundation for the subsequent fabrication of the honeycomb groove layer 300.

[0042] After the back side of chip 200 is pre-processed, a layer of SiN is deposited using PECVD technology. x During the deposition process, the filling ratio of silane to ammonia is strictly controlled at 3:1, and the temperature is controlled at 200℃ to ensure the uniformity and density of the mask layer. Subsequently, a precise regular hexagonal matrix pattern is formed on the back side of the chip 200 using laser direct writing exposure technology.

[0043] Next, deep reactive ion etching is performed on the regular hexagonal matrix region. During the etching process, sulfur hexafluoride and carbon octafluoride gases are alternately introduced for main etching and passivation treatment, respectively. The number of cycles is controlled at 30, with each reaction time being 8s and 5s, respectively, to form a honeycomb groove structure with moderate depth and smooth edges. By precisely controlling the etching parameters and gas ratio, a uniform and smooth honeycomb groove structure can be formed. This structure can effectively increase the surface area of ​​the back of the chip 200 and improve the uniformity of pressure distribution and heat release efficiency during the welding process.

[0044] After the honeycomb groove etching is completed, a 50nm thick titanium nitride coating is deposited at the bottom of the groove using magnetron sputtering technology to enhance the wear resistance and corrosion resistance of the bottom of the groove. Subsequently, a silicon dioxide gradient transition layer is deposited in the middle layer of the groove using PECVD technology to improve the stress distribution inside the groove. Finally, an OTS monolayer is constructed on the top layer of the groove using liquid phase self-assembly technology.

[0045] like Figure 4 As shown, copper composite micropillars with a diameter of 5μm and a height of 10μm are formed at the apex of the groove using electrochemical deposition technology to further enhance the functionality and welding reliability of the groove surface. Through multi-layer functionalization, the wear resistance, corrosion resistance and welding reliability of the groove surface can be significantly improved. The titanium nitride coating can effectively resist the high temperature and wear during the welding process, the silica gradient transition layer can improve the stress distribution inside the groove and reduce cracks caused by stress concentration, and the OTS monolayer and copper composite micropillars can provide good wettability and conductivity, promoting uniform distribution and firm adhesion of the solder.

[0046] In the process of chip 200 fusion soldering packaging, the quality of solder filling and the strength of the solder interface have a decisive influence on the performance of the solder joint. However, traditional solder filling methods often fail to achieve precise filling and uniform distribution of solder, resulting in defects such as voids and cracks at the solder interface. Therefore, this embodiment aims to provide a method for precise solder filling and interface strengthening treatment to improve the mechanical strength and thermal stability of the solder joint.

[0047] The solder paste prepared by mixing SAC305 with 0.2wt% Cu nanoparticles was selected as the welding material. The solder paste was evenly applied to the groove using a high-precision steel mesh and a scraper. Subsequently, a multi-stage reflow soldering process was performed to form a stable and reliable weld joint. The multi-stage reflow soldering pretreatment included a preheating stage, a heat preservation stage, and a cooling stage. By precisely controlling the temperature and time of each stage, the solder was ensured to melt fully and be evenly distributed.

[0048] The back side of the chip 200 is subjected to ultrasonic micro-vibration treatment in a vacuum environment to eliminate the minute defects and stress concentrations generated during the welding process. The ultrasonic micro-vibration treatment can generate high-frequency vibrations, which relax and eliminate the minute defects and stress concentrations on the welding interface. Subsequently, the back side groove area of ​​the chip 200 is scanned using a YAG laser.

[0049] By precisely controlling the laser parameters to strengthen the welding interface, YAG laser scanning can generate local high temperature, causing the metal atoms on the welding interface to rearrange and diffuse, forming a tighter metallurgical bond. At the same time, it also exposes the grooves after strengthening the interface. Finally, silica gel is used as a polishing slurry to perform chemical mechanical polishing on the back of the chip 200 to further improve the flatness and smoothness of the welding interface.

[0050] A pre-made silver layer 500 is also prepared on the top of the substrate 100 in advance. Since the substrate 100 and the chip 200 are separated and a gold solder layer 600 is pre-plated on the top of the substrate 100, the pre-made silver layer 500 is located on top of the gold solder layer 600 and forms a honeycomb array mirror pattern that matches the groove of the chip 200 through a stainless steel 300 mesh screen.

[0051] After pre-sintering and stabilization, the sintering temperature was controlled at 200℃, the temperature rise was 2℃ / s, and the holding time was 120s. At the same time, the filling ratio of nitrogen and hydrogen in the sintering protective gas was controlled at 95:5. Finally, the pre-fabricated substrate 100 and pre-fabricated chip 200 were bonded together, and gold wire 400 was welded and fixed on the top of the substrate 100. Then, the top of the chip 200 was sealed with grease by setting a mold.

[0052] Applying a honeycomb microstructure to the 200-TIM interface of a chip, by increasing the contact area through three-dimensional interlocking and integrating fixing functions, can significantly reduce interface thermal resistance, improve heat dissipation capacity, and enhance mechanical bonding strength, such as... Figure 3 As shown, the high and low density groove partition design is specifically adapted to the heat source distribution of the chip 200 to achieve directional heat release.

[0053] These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A chip fusion bonding packaging structure with pressure uniform distribution and heat release functions, comprising a substrate (100) and a chip (200), characterized in that, The substrate (100) has multiple sets of gold wires (400) on its pads, and the other end of the gold wires (400) is fixed to the position of the chip (200) pads by the wire feeding mechanism on the bonding machine; A gold-tin solder layer (600) is pre-plated between the substrate (100) and the chip (200) and located on the top of the substrate (100). A pre-made silver layer (500) is printed on the top of the gold-tin solder layer (600) by a template. A honeycomb groove layer (300) is provided between the chip (200) and the substrate (100) and located on the back of the chip (200).

2. The chip fusion bonding packaging structure with pressure uniform distribution and heat release functions according to claim 1, characterized in that, The method for preparing the honeycomb groove layer in the chip fusion bonding packaging structure with pressure uniform distribution and heat release functions is as follows: S1: Chip backside preprocessing The wafer is ground using a diamond grinding wheel, and the thickness of the ground wafer is controlled at 195-205μm. The ground wafer is then placed in a vacuum chamber and argon gas is introduced. The wafer is cleaned by plasma generated by 300W radio frequency power, and the processing time is controlled at 115-125s. S2: Laser etching of honeycomb grooves SiN deposition using PECVD x In the mask layer, the filling ratio of silane to ammonia in the deposition parameters is controlled at 3:1, the temperature is controlled at 200℃, and then a regular hexagonal matrix is ​​formed on the back side of the chip (200) by laser direct writing exposure. The regular hexagonal matrix groove formed on the back side of the chip (200) is then subjected to deep reactive ion etching. S3: Functional treatment of groove surface Titanium nitride coating was formed at the bottom of the hexagonal matrix groove on the back side of the chip (200) by magnetron sputtering with a thickness of 50 nm. Then, a silicon dioxide gradient transition layer was deposited in the middle layer of the hexagonal matrix groove on the back side of the chip (200) by PECVD. Finally, an OTS monolayer was constructed on the top layer of the hexagonal matrix groove on the back side of the chip (200) by liquid phase self-assembly. After completion, copper composite micropillars with a diameter of 5 μm and a height of 10 μm were formed at the apex of the hexagonal matrix groove on the back side of the chip (200) by electrochemical deposition. S4: Precision Solder Filling Solder paste was prepared using SAC305 and 0.2wt% Cu nanoparticles, and then applied using a stencil and scraper, followed by multi-stage reflow soldering. S5: Interface Enhancement Processing The back of the chip (200) is subjected to ultrasonic micro-vibration treatment in a vacuum environment. Then, the back groove area of ​​the chip (200) is scanned by YAG laser, and the back of the chip (200) is chemically and mechanically polished using silica gel as polishing slurry.

3. The chip fusion bonding packaging structure with pressure uniform distribution and heat release functions according to claim 2, characterized in that, The side length of the regular hexagonal matrix on the back side of the chip (200) is controlled at 20-50μm, and the spacing is controlled at 5-10μm.

4. The chip fusion bonding packaging structure with pressure uniform distribution and heat release functions according to claim 3, characterized in that, The deep reactive ion etching of the back side of the chip (200) forms a regular hexagonal matrix groove, which includes alternating main etching and passivation. The etching gas sulfur hexafluoride is introduced into the vacuum chamber and plasma is generated by high frequency power supply. The plasma reacts chemically with the silicon material on the surface of the regular hexagonal matrix groove for 8 seconds. Then carbon octafluoride gas is introduced for 5 seconds. The number of cycles is controlled at 30.

5. The chip fusion bonding packaging structure with pressure uniform distribution and heat release functions according to claim 4, characterized in that, The substrate (100) is pre-plated with a gold-tin solder layer (600) on top, the bonding temperature is controlled at 220°C and the bonding time is 120s. A pre-formed silver layer (500) is also set on the gold-tin solder layer (600) on top of the substrate (100).

6. The chip fusion bonding packaging structure with pressure uniform distribution and heat release functions according to claim 1, characterized in that, The method for preparing the pre-formed silver layer (500) on the gold-tin solder layer (600) on the top of the substrate (100) is as follows: Template printing: using a stainless steel 300-mesh screen and silver paste to form a honeycomb array mirror pattern on the top of the gold solder layer (600) that matches the groove of the chip (200); Pre-sintering, with sintering temperature controlled at 180-220℃, temperature rise of 2℃ / s, and holding for 120s. At the same time, the filling ratio of nitrogen and hydrogen in the sintering protective gas is controlled at 95:

5.

7. The chip fusion bonding packaging structure with pressure uniform distribution and heat release functions according to claim 1, characterized in that, The back of the chip (200) has a regular hexagonal matrix groove divided into a high-density area and a low-density area. The number of regular hexagonal matrix grooves in the high-density area is 1200-2000 per mm², and the number of regular hexagonal matrix grooves in the low-density area is 300-800 per mm².

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