Discrete device packaging structure with multi-chip parallel layout

Abstract

The invention discloses a discrete device packaging structure with a multi-chip parallel layout, belongs to the technical field of semiconductor device packaging, and solves the problems that the parallel parasitic parameter of an existing discrete device is large and the cost of a power module is high. The discrete device packaging structure with the multi-chip parallel layout comprises a drain metal substrate, a power semiconductor chip, a supporting positioning stud, a grid leading-out terminal, a source leading-out terminal, a bonding wire, a PCB and a supporting shell. The drain electrode metal substrate is connected with the drain electrode of the power semiconductor chip, the grid electrode and the source electrode of the power semiconductor chip are connected with the copper bonding pad on the PCB through bonding wires, and the grid electrode leading-out terminal and the source electrode leading-out terminal are connected with the copper bonding pad on the PCB through bonding wires. The power density of the device is improved, the parasitic parameter of the whole device is reduced, the production cost is reduced, and the reliability is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power semiconductor packaging, and particularly relates to a discrete device packaging structure with a multi-chip parallel layout. BACKGROUND

[0002] Power devices, as electronic devices for realizing electric energy control or conversion, play a crucial role in power electronic systems. Discrete devices are widely used in the industrial field due to their low cost, good flexibility, high reliability, and convenient maintenance and replacement. With the modularization of power electronic device development and design, it has become a development trend to package multiple identical power electronic devices or multiple different power electronic devices used in cooperation in a module to form a power module. The power module can reduce the size of the device, reduce the cost, and improve the reliability. More importantly, the power module can greatly reduce the line inductance, especially for circuits with high operating frequency, the power module can simplify the protection and buffer circuit by reducing the line inductance.

[0003] However, the power module has high integration, so the packaging cost and design complexity are high, which is not conducive to large-scale industrial applications that are sensitive to cost. In the packaging materials of the power module, the highest cost proportion is the copper clad ceramic substrate (Direct Bond Copper, DBC). The production process of the DBC ceramic substrate leads to a high cost, so the packaging structure without the DBC ceramic substrate can significantly reduce the cost of device packaging.

[0004] In addition, in order to meet the high-power application in the industry, power chips are often used in parallel to improve the current-carrying capacity of the device as a whole. However, due to the inconsistency of parameters between the chips and the asymmetric layout, the current flowing between the parallel chips is not balanced. The chip with the largest current flowing through it has more serious heat loss, so it will bear higher electrical stress and thermal stress, which is not conducive to the safety and stability of the system as a whole. Therefore, making the current between the parallel chips more balanced through symmetric layout design or path compensation is also a guarantee for the stable and safe operation of the power electronic system. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a discrete device packaging structure with a multi-chip parallel layout to solve the technical problems of large parasitic parameters of traditional discrete devices in parallel and high cost of power modules.

[0006] The application adopts the following technical solutions: A kind of discrete device package structure of multi-chip parallel layout, including drain metal substrate, drain metal substrate is arranged in support shell, PCB board is arranged above drain metal substrate, drain metal substrate is integrated and leads drain terminal and is fixed by the recess of support shell;Gate lead-out terminal and source lead-out terminal are also arranged at the recess of support shell;Gate lead-out terminal and source lead-out terminal are connected with PCB board by bonding wire respectively;A plurality of power semiconductor chips are arranged on drain metal substrate, the drain of power semiconductor chip is connected with drain metal substrate, and source and gate are connected with the copper layer pad exposed on PCB board by bonding wire respectively.

[0007] Preferably, four positioning holes and a central axis through hole are symmetrically arranged in the drain metal substrate.

[0008] Preferably, the power semiconductor chips are symmetrically distributed on both sides of the central axis of the drain metal substrate, forming a loop.

[0009] Preferably, the power semiconductor chips are silicon MOSFET, IGBT or silicon carbide MOSFET, and the number is greater than or equal to 2.

[0010] Preferably, a support positioning stud is embedded in the positioning hole of the drain metal substrate, and the PCB board is placed on the support positioning stud.

[0011] Preferably, the height of the support positioning stud is 0.5-1.5mm, to ensure that the distance between the PCB board and the substrate is greater than or equal to 0.3mm.

[0012] Preferably, the bonding wire connects the chip gate / source to the PCB board with equal length path, and the wiring of the gate lead-out terminal and the power semiconductor chip is symmetrical.

[0013] Preferably, a through hole is arranged at the central axis of the back of the support shell, which is coaxial with the through hole of the drain metal substrate.

[0014] Preferably, the back of the support shell is hollow and internally provided with a silica gel filling layer.

[0015] Preferably, the dielectric strength of the gel filling layer is greater than or equal to 15kV / mm, and the thermal conductivity is greater than or equal to 0.8W / (m·K).

[0016] Compared with the prior art, the present application has at least the following beneficial effects: The application discloses a discrete device package structure of a multi-chip parallel layout, which realizes power density improvement through multi-chip parallel connection, realizes package integration at the discrete device level, significantly reduces the parasitic inductance of a circuit compared with parallel connection of multiple discrete devices, and fully plays the integration advantage of the package structure; the package integration of the discrete device is realized through low-cost materials such as a metal substrate, lead terminals, a PCB board and bonding wires, so that the overall switching performance of the device is optimized, and the production cost is significantly reduced. Meanwhile, the package structure and the manufacturing process are simple, and are suitable for large-scale industrial promotion and use, and are beneficial to further reducing the production cost; through adjustment of the layout and wiring of a plurality of parallel chips, dynamic and static current sharing between the parallel chips is realized, the long-term safe and reliable operation of the device is ensured, and the adjustment includes chip layout adjustment, PCB wiring optimization and lead terminal adjustment; the PCB and the substrate are kept at a certain distance through positioning support studs, the distance of the lead terminals is adjusted to provide sufficient insulation distance, and silica gel filling is used as an insulating medium in the package, and covers the power semiconductor chip, so that the insulation strength of the package structure is improved, and the reliability of the module is improved; the metal substrate (copper / aluminum) is used to replace the traditional DBC ceramic substrate, the package cost is directly reduced by more than 42%, the drain terminals are integrally formed with the metal substrate, and an additional welding process is saved; the support shell groove integrates the terminal fixing function, reduces the positioning clamp, and improves the assembly efficiency; the chip drain is directly connected to the metal substrate, the current path is shortened by 70%, and the total parasitic inductance of the loop is only 4.7nH; the PCB board centrally manages the gate / source wiring, the gate loop inductance is reduced to 1.2nH, and the switching loss is reduced by 18%; the multiple chips are connected in parallel through the metal substrate, combined with PCB wiring optimization, the static current imbalance is less than or equal to 5%, and the dynamic switching current deviation is less than 8%; the thermal conductivity coefficient of the metal substrate (>380W / (m·K)) is significantly higher than that of the DBC ceramic (24-28W / (m·K)), and the chip junction temperature is reduced by 15 DEG C; the support shell groove locks the terminal, and the vibration resistance is improved by 3 times; the silica gel filling covers the exposed conductor, and the humidity corrosion resistance reaches MSL 1 level; the standard PCB board is used to replace the complex DBC photolithography process, the production yield is improved, various chips such as silicon / SiC / GaN can be mixed and loaded, the application is suitable for photovoltaic inverter (10-50kW) and electric vehicle OBC (3-22kW) scenes, and through the three-in-one design of the metal substrate direct connection, PCB centralized wiring and shell integration, the cost, performance and reliability are realized in three dimensions, and a revolutionary solution is provided for industrial high-power applications in terms of discrete price and module performance.

[0017] Further, the central axis through hole promotes double-sided heat dissipation, the chip temperature rise is reduced by 15 DEG C, the four positioning holes are matched with the studs to control the chip position deviation to be less than or equal to ±0.1mm, current imbalance caused by deviation is avoided, and the cooperation of heat dissipation and mechanical positioning is solved.

[0018] Further, the central axis is symmetrically distributed on both sides to offset the asymmetric inductance of the layout, the dynamic current imbalance is less than 8%, the symmetric heat dissipation path reduces local hot spots, the temperature difference between the chips is less than 5 DEG C, dynamic / static current equalization is realized, and the reliability is improved.

[0019] Further, the SiC MOSFET supports a working frequency of 200 kHz, the switching loss is 22% lower than that of a silicon device, the current-carrying capacity is linearly improved (4 chips are 3.6 times that of a single chip), and the application scenarios are expanded.

[0020] Further, the stud physically isolates the PCB and the substrate, the withstand voltage is greater than 2500V (the distance is greater than or equal to 0.3mm), the stud absorbs assembly tolerance and vibration, the bonding wire breakage rate is reduced by 90%, the insulation distance of the PCB is ensured, and vibration buffering is provided.

[0021] Further, the height of 0.5-1.5mm ensures that the creepage distance is greater than 3.2mm, the 1.0mm spacing forms an air convection channel, the forced air cooling efficiency is improved by 18, and the insulation strength and heat dissipation efficiency are effectively balanced.

[0022] Further, the equal-length wiring controls the gate signal delay to be less than 0.5ns, suppresses inter-chip vibration, the symmetric path makes the source inductance of each chip consistent, the static current deviation is less than or equal to 3%, and the gate delay difference of the parallel chips is eliminated.

[0023] Further, the coaxial through hole is aligned with the heat sink fin, the thermal resistance is reduced by 40%, the through hole is guided and positioned, the automatic assembly precision is improved to ±0.05mm, and a high-efficiency heat dissipation channel is constructed.

[0024] Further, the glue covers all exposed conductors, the partial discharge amount is less than 5pC, the gel CTE matches the chip, the delamination rate is less than 1% after temperature cycling (-55-150 DEG C), and insulation, heat dissipation and mechanical protection are integrated.

[0025] Further, the dielectric strength of greater than or equal to 15kV / mm resists 10kV / us surge voltage, the thermal conductivity of greater than or equal to 0.8W / (m*K) ensures that the chip junction temperature is less than 150 DEG C, and the critical value of the insulation and heat dissipation capacity is quantified.

[0026] In summary, the application reasonably selects the materials of various components, adjusts the layout inside the package, ensures the balance of current between the chips on the basis of power level improvement of chip parallel connection, and significantly reduces the parasitic inductance inside the package, the model structure is simple, and the application is suitable for large-area market promotion.

[0027] The technical solutions of the application will be further described in detail below with reference to the drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the relative embodiment description are briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0029] Figure 1 A front isometric view of the low-cost multi-chip parallel layout discrete device packaging structure in the embodiment of the present application; Figure 2 A top view of the low-cost multi-chip parallel layout discrete device packaging structure in the embodiment of the present application; Figure 3 An exploded view (hidden bonding wires) of the low-cost multi-chip parallel layout discrete device packaging structure in the embodiment of the present application.

[0030] Wherein: 1. drain metal substrate; 2. power semiconductor chip; 3. support positioning stud; 4. gate lead terminal; 5. source lead terminal; 6. bonding wire; 7. PCB board; 8. support housing. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort under the premise of the present application are within the protection scope of the present application.

[0032] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "one side", "one end", "one edge" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. In addition, in the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0033] In the description of the application, it should be noted that unless otherwise expressly specified and limited, the terms "mounting", "connection", "connecting" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, or it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0034] It should be understood that when used in the specification and the appended claims, the terms "comprise" and "include" indicate the presence of described features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0035] It should also be understood that the terms used in the present application specification are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the present application specification and the appended claims, unless otherwise clearly indicated by the context, the singular forms "a", "an" and "the" are intended to include the plural forms.

[0036] It should be further understood that the term "and / or" used in the present application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0037] In the drawings, various structural schematic diagrams according to the disclosed embodiments of the present application are shown. These drawings are not drawn to scale, in which certain details are exaggerated for the purpose of clear expression, and certain details can be omitted. The shapes of various regions, layers shown in the drawings and their relative size, positional relationship may deviate in actuality due to manufacturing tolerance or technical limitation, and the skilled in the art can additionally design regions / layers with different shapes, sizes, relative positions according to actual needs.

[0038] In the prior art, power devices play a crucial role in power electronic systems as electronic devices for realizing electric energy control or conversion. Discrete devices are widely used in the industrial field due to their low cost, good flexibility, high reliability, and convenient maintenance and replacement. However, the traditional power module uses a copper-clad ceramic substrate as a heat dissipation and electrical connection carrier, and its production process is complex and the cost is high. In addition, when multiple chips are arranged in parallel, due to the difference in chip parameters and asymmetric layout, it is easy to cause uneven current distribution, affecting the stability of the system.

[0039] In order to solve the above problems, firstly, it is necessary to find a low-cost heat dissipation and electrical connection scheme to replace the copper-clad ceramic substrate, and to optimize the chip layout to improve the current balance. Through analysis, it is found that the metal substrate has good heat conduction and electrical conductivity, which can replace the ceramic substrate to reduce the packaging cost. Further considering the multi-chip parallel connection scene, if the chips are symmetrically arranged and equal-length signal paths are used, the difference in parasitic parameters can be reduced, thereby alleviating the current imbalance problem. Based on this, a metal substrate combined with a support shell is proposed, which realizes a low-cost and high-reliability packaging structure through layered layout and symmetric wiring.

[0040] The application provides a discrete device packaging structure with multi-chip parallel layout, a drain metal substrate is connected with the drain of a power semiconductor chip, and the gate and source of the power semiconductor chip are connected with copper pads on a PCB board, gate output terminals and source output terminals on the PCB board through bonding wires. The application solves the problem of large parasitic parameters of existing discrete devices in parallel connection and high cost of power modules, improves the power density of the device, reduces the overall parasitic parameters of the device, reduces the production cost, and improves the reliability.

[0041] Please refer to Figure 1 The application provides a discrete device packaging structure with multi-chip parallel layout, which comprises a plurality of power semiconductor chips 2, four support positioning studs 3, a drain metal substrate 1, a gate output terminal 4, a drain output terminal 5, a PCB board 7, a support shell 8, and a plurality of bonding wires 6. The drain metal substrate 1 is arranged in the support shell 8, the PCB board 7 is arranged above the drain metal substrate 1, the drain metal substrate 1 integrally outputs the drain output terminal and is fixed through the groove of the support shell 8; the gate output terminal 4 and the source output terminal 5 are also arranged in the groove of the support shell 8; the gate output terminal 4 and the source output terminal 5 are connected with the PCB board 7 through the bonding wires 6; a plurality of power semiconductor chips 2 are arranged on the drain metal substrate 1, the drains of the power semiconductor chips 2 are connected with the drain metal substrate 1, and the sources and gates are connected with the exposed copper layer pads on the PCB board 7 through the bonding wires 6.

[0042] The drain metal substrate 1 refers to a substrate made of high-thermal-conductivity metal material, which can be realized by copper, aluminum, molybdenum alloy, etc.

[0043] The bonding wire 6 refers to a metal wire, which can be realized by aluminum wire or copper wire, and is used to connect the chip and the PCB board through equal-length paths to reduce the difference in parasitic inductance.

[0044] The PCB board 7 refers to a printed circuit board with exposed copper layer pads, which can be realized by FR4 substrate, and is used to concentrate the connection of gate and source signals.

[0045] The support shell 8 refers to an insulating shell with a groove, which can be implemented by injection molding of engineering plastics, and the groove is used to fix the drain terminal and constrain its position.

[0046] Specifically, the drain metal substrate 1 directly serves as a heat dissipation channel and a drain current carrier, replacing the traditional copper-clad ceramic substrate, thereby reducing the packaging cost. The power semiconductor chip 2 is welded on the drain metal substrate 1, the drain is conducted through the drain metal substrate 1, the source and the gate are connected to the copper layer pad of the PCB board 7 through the bonding wire 6, and signal centralized control is realized. The groove of the support shell 8 fixes the drain terminal, ensuring mechanical stability. The gate and source lead terminals are symmetrically connected to the PCB board 7 through the bonding wire 6, and the symmetric layout of the power semiconductor chip 2 makes the parallel loop path lengths consistent, thereby reducing the current distribution difference. The back through hole of the support shell 8 is coaxially designed with the substrate through hole, optimizing the heat dissipation path.

[0047] The power semiconductor chip 2 is a silicon MOSFET, IGBT, or silicon carbide MOSFET.

[0048] Compared with the prior art, the traditional scheme relies on a copper-clad ceramic substrate to realize heat dissipation and electrical connection, while the present scheme adopts a metal substrate combined with a support shell structure, which reduces the cost while maintaining the heat dissipation efficiency. In the prior art, the multi-chip parallel layout is prone to uneven current distribution due to path asymmetry, while the present scheme significantly improves current uniformity through symmetric layout and equal-length bonding wire design. In addition, the layered layout of the PCB board and the metal substrate simplifies the signal wiring complexity and improves the packaging reliability.

[0049] Through the above technical scheme, the present application solves the problem of insufficient heat dissipation and electrical performance caused by the omission of a copper-clad ceramic substrate in discrete device packaging, and effectively improves the current distribution uniformity in multi-chip parallel connection through symmetric layout and equal-length wiring design. The metal substrate integrated structure reduces the packaging cost, and the layered layout of the support shell and the PCB board optimizes the signal control path, thereby realizing low-cost and high-reliability power device packaging in industrial applications.

[0050] The present application further proposes that the drain metal substrate is symmetrically provided with four positioning holes and a central axis through hole.

[0051] Among them, the positioning hole refers to a hole structure distributed at the symmetric position of the drain metal substrate for fixing installation, which can be implemented by a circular or rectangular through hole, and its function is to limit the displacement of the substrate in the horizontal direction by cooperating with the internal protrusion or positioning pin of the support shell. The central axis through hole refers to a hole structure penetrating along the central axis of the substrate, which can be implemented by a cylindrical through hole, and its function is to constrain the offset of the substrate in the vertical direction by cooperating with the coaxial back through hole of the support shell.

[0052] Specifically, four positioning holes are symmetrically distributed on both sides of the substrate central axis, forming a four-point positioning structure. During installation, the positioning pins inside the support shell are inserted into the positioning holes, so that the substrate is mechanically constrained in both the transverse and longitudinal directions. At the same time, the central axis through hole and the through hole on the back of the support shell are connected by a coaxial bolt or positioning column, further limiting the possibility of the substrate rotating around the axis. In this way, the substrate is multi-dimensionally positioned in the support shell, eliminating the problem of asymmetric chip layout caused by installation deviation.

[0053] Compared with the prior art, the existing packaging structure usually adopts single-sided positioning holes or asymmetric positioning design, which is easy to cause the substrate to deviate due to assembly stress or vibration, thereby causing uneven current distribution of parallel chips. The scheme cooperates the symmetrically distributed four positioning holes with the central axis through hole to disperse mechanical stress while ensuring positioning accuracy and avoiding local deformation.

[0054] Through the above technical scheme, the application solves the problem of asymmetric chip layout caused by inaccurate positioning of the drain metal substrate, ensures that the power semiconductor chips are symmetrically distributed on both sides of the substrate, improves the current balance of the parallel loop, and at the same time enhances the stability of the cooperation between the substrate and the support shell, avoiding structural failure caused by mechanical vibration or thermal expansion.

[0055] The application further provides a technical scheme in which the power semiconductor chips are symmetrically distributed on both sides of the central axis of the drain metal substrate to form a parallel loop.

[0056] Among them, symmetric distribution means that the chips are mirror arranged in the substrate plane with the geometric center line as the reference, which can be realized by double-row staggered arrangement or ring array arrangement, thereby reducing the discrete nature of parasitic parameters by eliminating spatial position difference. The central axis on both sides refers to the virtual symmetry axis perpendicular to the current main path in the substrate plane, which can be realized by marking the substrate opening or notch as a positioning reference to ensure that the distance of the chip group from the symmetry axis is equal. Parallel loop refers to a multi-branch conductive structure in which the drains of multiple chips are connected to the substrate, and the sources and gates are connected to the PCB through independent bonding paths, which can be realized by designing equal-length bonding wires or equal-area pads to make the impedance characteristics of each branch consistent.

[0057] Specifically, the axis in the substrate is set as the symmetry reference of the current distribution, and all the chips are divided into two groups and arranged on both sides of the axis. The drain of each chip is connected to the same potential through the substrate metal layer, and the source and gate are connected to the corresponding symmetric pad areas on the PCB board through bonding wires. Since the distance from the chip group to the center line of the substrate is equal, the difference in the conductive path length of each chip to the drain terminal is eliminated, and the wiring length of the source and gate bonding wires is also automatically matched due to the symmetric layout. This spatial symmetry translates into consistency in the equivalent resistance and inductance parameters of each branch, making the impedance characteristics of each branch in the parallel circuit tend to be the same, thereby achieving natural balanced distribution of the current of each chip in the on state.

[0058] Compared with the prior art, the conventional multi-chip parallel scheme usually adopts linear arrangement or random distribution, resulting in significant differences in the conductive path length between chips, and the discrete degree of parasitic inductance and resistance parameters exceeds 10%. The present scheme controls the difference in parasitic parameters of each branch within 5% by using a forced symmetric layout constraint, and eliminates the thermal coupling difference caused by the position offset of the chips, so that the uniformity of the chip junction temperature distribution is improved by more than 30%.

[0059] Through the above technical scheme, the present application effectively solves the current distribution imbalance problem caused by the asymmetric layout of the parallel chips, so that the static current deviation of each chip in the on state is controlled within ±5%, the dynamic current sharing response time is shortened to the microsecond level, the local overheating risk is significantly reduced, and the service life of the device is prolonged.

[0060] The present application further proposes that the power semiconductor chips are silicon MOSFETs, IGBTs or silicon carbide MOSFETs, and the number is ≥2.

[0061] Among them, the silicon MOSFET refers to a metal-oxide semiconductor field effect transistor made of silicon-based material, which can be implemented by using a planar gate or a trench gate structure, and is suitable for high-frequency low-loss application scenarios.

[0062] Among them, the IGBT refers to an insulated gate bipolar transistor, which can be implemented by using an NPT type or an FS type structure, and is suitable for electric energy conversion under high-voltage and large-current conditions.

[0063] Among them, the silicon carbide MOSFET refers to a metal-oxide semiconductor field effect transistor made of silicon carbide material, which can be implemented by using a vertical conduction structure, and is suitable for high-frequency high-temperature working environment.

[0064] Among them, the number ≥2 means that the number of parallel power semiconductor chips is two or more, which can be implemented by using an even symmetric distribution, and the overall current carrying capacity is improved by increasing the number of parallel branches.

[0065] Specifically, the selection of silicon MOSFET, IGBT or silicon carbide MOSFET is determined according to the electrical parameter requirements of the application scenario. For example, in the scenario requiring high-frequency switching and sensitive to loss, silicon MOSFET is preferred; in the high-voltage and high-current industrial frequency converter, IGBT is used to improve the withstand voltage capability; in high temperature or high frequency working condition, silicon carbide MOSFET is used to reduce the on-state loss. By setting two or more chips in parallel, combined with symmetric layout, the on-state path length and parasitic inductance of each chip tend to be consistent, thereby reducing the current distribution deviation caused by parameter difference. At the same time, the heat distribution of multiple chips is dispersed through the parallel structure, avoiding local overheat caused by overload of a single chip.

[0066] Compared with the prior art, the parallel chips in the prior art usually use a single type of semiconductor device and the layout is asymmetric, resulting in uneven current distribution and thermal stress concentration. The present scheme minimizes the parasitic parameter difference of different chips by limiting the chip type and number, combined with symmetric layout design, and disperses the current and thermal load by using the multi-chip parallel structure, thereby improving the current carrying capacity while improving the current sharing characteristics.

[0067] Through the above technical scheme, the present application can flexibly select the type of semiconductor chip according to the application requirements, improve the overall current carrying capacity through the multi-chip parallel structure, and reduce the parasitic parameter difference by combining the symmetric layout, effectively inhibit the current imbalance phenomenon of parallel chips, reduce the risk of local overheating, and thereby improve the working stability and reliability of the device.

[0068] The present application further proposes to embed a support positioning stud in the positioning hole of the drain metal substrate, and the PCB board is placed on the support positioning stud.

[0069] The support positioning stud refers to a columnar structure with mechanical support function, which can be made of metal or ceramic material, embedded in the positioning hole through thread or interference fit, used to bear the weight of the PCB board and maintain the distance between the PCB board and the substrate.

[0070] The positioning hole refers to a hole-shaped structure arranged at the edge of the drain metal substrate, which can be in the form of a circular or square through hole, used to form a physical fit with the support positioning stud to achieve horizontal positioning of the PCB board.

[0071] The PCB board placement refers to a flat support structure formed by the top surface of the support positioning stud, which can be polished or added with an insulating gasket to keep the contact surface between the PCB board and the stud flat, avoiding structural deformation caused by poor contact.

[0072] Specifically, after the support positioning stud is embedded into the positioning hole of the drain metal substrate preform, the top of the support positioning stud forms a stable support plane. The PCB board is directly placed on the plane formed by the plurality of support positioning studs, and the vertical distance between the substrate and the PCB board is controlled by the height of the stud. The maintenance of the distance relies on the rigid support characteristics of the stud, which replaces the insulating support function of the traditional DBC substrate. The cooperation of the positioning hole and the stud enables accurate positioning of the PCB board in the horizontal direction, preventing electrical connection abnormalities caused by installation deviation.

[0073] Compared with the prior art, the traditional packaging structure uses a DBC ceramic substrate as a support medium for the PCB board, and the substrate needs to be combined with the metal bottom plate through a high-temperature welding process, which significantly increases the material cost and process complexity. The mechanical cooperation of the support positioning stud and the positioning hole in the present application realizes the positioning and support of the PCB board by utilizing the structural characteristics of the metal substrate itself without the DBC substrate, which not only retains the necessary insulating distance but also reduces the additional cost of the ceramic substrate.

[0074] Through the above technical solution, the present application effectively solves the problem of insufficient support strength of the packaging structure after omitting the DBC substrate, and realizes the accurate installation of the support positioning stud by utilizing the existing positioning hole of the metal substrate, which not only reduces the material cost but also ensures the stability of the distance between the PCB board and the substrate, avoiding electrical short circuit or abnormal heat dissipation caused by failure of the support structure.

[0075] The present application further proposes that the height of the support positioning stud is 0.5-1.5 mm, ensuring that the distance between the PCB board and the substrate is above 0.3 mm.

[0076] The support positioning stud refers to a columnar support component embedded into the positioning hole of the drain metal substrate, which can be made of metal or high-strength engineering plastic and fixed through threaded connection or interference fit. The component forms a rigid support structure in the vertical direction, which is used to accurately control the spatial distance between the PCB board and the metal substrate.

[0077] The distance between the PCB board and the substrate refers to the vertical distance between the lower surface of the printed circuit board and the upper surface of the metal substrate, which can be controlled by adjusting the height parameter of the support positioning stud. The setting of the distance needs to meet the minimum space requirement for air convection heat dissipation and the electrical insulation safety standard at the same time.

[0078] Specifically, the support positioning stud is embedded in the substrate positioning hole to form a stable three-dimensional support system, and the height parameter is optimized to meet the mechanical support strength and spatial layout requirements. When the PCB is placed on the top of the support positioning stud, the vertical size of the support structure directly determines the gap size between the circuit board and the metal substrate. The gap serves as both a heat dissipation airflow channel to promote heat dissipation and an electrical insulation layer to prevent high-voltage breakdown. By precisely controlling the machining accuracy of the support positioning stud, the stability of the gap between the circuit board and the substrate in different batches of products can be ensured.

[0079] Compared with the prior art, the traditional packaging structure uses fixed-height support pads or adhesive materials to control the spacing of the circuit board, which has the defects of large assembly tolerance and unstable heat dissipation channel. The present application realizes precise control of the spacing parameter through adjustable height support positioning studs, which optimizes the balance between heat dissipation and insulation performance while ensuring structural rigidity.

[0080] Through the above technical solutions, the present application effectively solves the problems of low heat dissipation efficiency and insulation failure caused by insufficient spacing between the circuit board and the metal substrate. Through the optimization design of the mechanical support structure, the heat dissipation performance and electrical safety are simultaneously improved, and the assembly stability and production consistency of the packaging structure are ensured.

[0081] The present application further proposes that the bonding wires connect the chip gate or source to the PCB board in equal length paths, and the gate lead terminals are symmetrically arranged with the power semiconductor chip.

[0082] Among them, the equal length path connection means that the physical length of the bonding wire is consistent with the medium material through which the wire path passes. Specifically, it can be realized by using a serpentine wire on the PCB board or a pre-defined bonding track, which ensures the equalization of the driving signal transmission impedance of each parallel chip by eliminating the difference in transmission path.

[0083] Among them, the symmetric wiring means that the electrical connection between the gate lead terminals and the power semiconductor chip presents a mirror symmetry relationship in spatial layout. Specifically, it can be realized by using a double-axis symmetric arrangement of bonding points or balancing the wire length, which reduces the difference in loop parasitic parameters and suppresses the influence of electromagnetic interference on the driving signal.

[0084] Specifically, in the gate drive loop of the parallel chip, the equal length path connection makes the driving signal transmission path of each chip have the same resistance and inductance characteristics, thereby eliminating the inconsistent phenomenon of signal transmission delay caused by path difference. At the same time, the symmetric wiring design makes the gate drive loop of each chip form a complementary structure in the spatial electromagnetic field distribution, effectively offsetting the difference in parasitic capacitance and inductance caused by layout asymmetry. The synergistic effect of the two can realize the synchronous triggering and turning off of the driving signal of the parallel chip, avoiding the transient current distribution imbalance caused by timing deviation.

[0085] Compared with the prior art, the length difference of the bonding wire in the traditional packaging structure causes the transmission delay of the driving signal to be out of synchronization, and the difference in parasitic parameters caused by asymmetric wiring exacerbates the dynamic current imbalance of the parallel chips. The combination design of equal-length path connection and symmetric wiring in the scheme realizes the parameter symmetry of the driving loop from two dimensions of signal transmission path and electromagnetic compatibility, breaking through the limitations of single optimization means.

[0086] Through the above technical scheme, the application can effectively suppress the transient current distribution imbalance of the parallel chips caused by the out-of-synchronization of the driving signal in the switching process, reduce the risk of local overheating and electrical stress overload caused by current concentration, and thus improve the operation stability and reliability of the multi-chip parallel system.

[0087] The application further proposes that a through hole is formed at the central axis of the back of the support shell and coaxially cooperates with the through hole of the drain metal substrate.

[0088] The through hole formed at the central axis of the back of the support shell refers to a through hole structure formed along the center line of the back of the shell, which can be realized by mechanical processing or mold forming. The through hole is used to provide an axial positioning reference for the support shell and the external heat sink or mounting component.

[0089] The coaxial cooperation of the through hole of the drain metal substrate refers to the complete coincidence of the through hole of the substrate and the through hole of the support shell in the axial direction. The cooperation can be realized by precise assembly process. The cooperation relationship is used to ensure the consistency of the three-dimensional space positioning between the shell and the substrate, and avoid the deviation of the heat conduction path caused by assembly error.

[0090] Specifically, the support shell and the drain metal substrate form a continuous axial channel through the coaxial through hole, which can be used as a mounting interface for the external heat sink or fastener. During assembly, the through hole of the support shell and the through hole of the substrate are precisely aligned through the coaxial constraint relationship, so that the contact surface pressure distribution of the shell and the substrate is uniform, and the local thermal resistance increase caused by misalignment is reduced. At the same time, the straight-line heat dissipation path formed by the coaxial through hole can directly transfer the heat generated by the substrate to the external heat dissipation structure, avoiding the accumulation of heat inside the shell.

[0091] Compared with the prior art, the traditional packaging structure usually adopts an asymmetric positioning method, such as edge buckle or non-central positioning hole to fix the shell and the substrate. Such method is prone to assembly deviation due to machining tolerance, which affects the heat dissipation efficiency and generates mechanical stress. The coaxial cooperation of the central axis through hole in the scheme eliminates the superposition risk of multi-directional positioning error, and balances the stress distribution between the shell and the substrate by using the axial symmetric structure.

[0092] By the technical scheme, the application solves the problems of low heat dissipation efficiency and poor structural stability caused by insufficient installation and positioning accuracy of the support shell and the drain metal substrate, improves the assembly accuracy through the axial positioning reference formed by the coaxial through hole, optimizes the linearity of the heat conduction path, and reduces the risk of local stress concentration.

[0093] The application further proposes that the back of the support shell is hollowed out and internally provided with a silica gel filling layer.

[0094] The back of the support shell being hollowed out means that the back area of the support shell is designed as an open or recessed structure, which can be realized by machining or injection molding process. The cavity structure is formed by removing part of the shell material, which can provide space for the filling material and reduce the overall weight of the package.

[0095] The silica gel filling layer is a semi-solid filler composed of a silicon-based polymer material, which can be realized by injecting liquid silicone and then curing. The silica gel forms an elastic insulating layer after curing, which can wrap the internal components and achieve electrical isolation and heat transfer.

[0096] Specifically, the cavity structure formed by the hollowed back of the support shell allows the silica gel filling layer to fully cover the internal power semiconductor chips and bonding wires. The high dielectric strength of the silica gel can block the current leakage path between the drain metal substrate and the external environment, and its thermal conductivity can conduct the heat generated by the chips to the external heat sink through the support shell. The silica gel filling layer replaces the traditional copper-clad ceramic substrate, which realizes heat conduction by directly contacting the chip surface, avoiding the high-cost processing link of the ceramic substrate. The hollow structure simplifies the shell manufacturing process, and the silica gel filling can be completed by automatic dispensing equipment, which is suitable for large-scale production needs.

[0097] Compared with the prior art, the traditional packaging scheme relies on a copper-clad ceramic substrate to achieve insulation and heat dissipation, but the ceramic substrate is costly and complex to process. The present scheme uses a silica gel filling layer combined with a hollow support shell, which maintains equivalent insulation and heat dissipation capacity, eliminates the use of a ceramic substrate, and the fluidity of the silica gel allows it to adaptively fill irregular spaces, improving the protection effect of the internal components of the packaging structure.

[0098] Through the above technical scheme, the application improves the heat dissipation uniformity of the power semiconductor chip, enhances the electrical insulation reliability of the internal components of the packaging structure, reduces the material and manufacturing costs, and the silica gel filling process can be adapted to an automated production line, improving the packaging efficiency.

[0099] The application further proposes that the dielectric strength of the silica gel filling layer is ≥15kV / mm, and the thermal conductivity is ≥0.8W / (m·K).

[0100] The dielectric strength ≥ 15 kV / mm refers to the breakdown voltage threshold that the filling material can withstand under a unit thickness, and can be realized by using a silica gel containing aluminum oxide or boron nitride filler. This feature prevents insulation failure in a high voltage environment by improving the material's ability to withstand an electric field. The thermal conductivity ≥ 0.8 W / (m·K) refers to the efficiency of the filling material in transferring heat, and can be realized by using a modified silica gel with added silicon nitride or silicon carbide particles. This feature enhances the internal heat conduction path of the material to quickly transfer the heat generated by the chip to the outside of the package.

[0101] Specifically, the back hollow area of the support shell is filled with a silica gel layer with high dielectric strength and high thermal conductivity, replacing the insulation and heat dissipation functions of the traditional copper clad ceramic substrate. The silica gel layer covers the power semiconductor chip and the bonding wire area, and its dielectric strength ensures electrical isolation between the chips and the terminals, preventing leakage current or partial discharge caused by the omission of the ceramic substrate. At the same time, the thermal conductivity meets the chip heat dissipation requirements, and the heat is transferred to the external heat dissipation structure through the contact surface of the filling layer and the support shell, maintaining the chip operating temperature within a safe range.

[0102] Compared with the prior art, the traditional package relies on a copper clad ceramic substrate to achieve insulation and heat dissipation, but the substrate is costly and the process is complex. This scheme optimizes the performance of the gel material and directly realizes insulation and heat conduction functions by using a filling layer without a ceramic substrate, reducing material costs and simplifying package structure design.

[0103] Through the above technical scheme, the application solves the problems of insufficient insulation performance and reduced heat dissipation efficiency after omitting the copper clad ceramic substrate, while reducing the packaging cost, ensuring the electrical safety and long-term thermal stability of the power semiconductor chip under high voltage working conditions.

[0104] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the scope of protection of the present application.

[0105] Embodiment 1 See Figure 1 , Figure 2 , Figure 3The application provides a multi-chip parallel layout discrete device package structure, which comprises a drain metal substrate 1, power semiconductor chips 2, support positioning studs 3, gate lead terminals 4, source lead terminals 5, bonding wires 6, a PCB plate 7 and a support shell 8.

[0106] The drain metal substrate 1 is provided with four symmetrical positioning holes for placing the support positioning studs 3, and the support positioning studs 3 play a supporting and positioning role for the PCB plate 7; the drain lead terminals are directly led out from the substrate; the drains of the four power semiconductor chips 2 are connected with the substrate through solder; and the gates and sources on the upper surfaces of the power semiconductor chips 2 are connected with copper pads of the PCB plate 7 through the bonding wires. The bonding wires 6 adopt equal-length serpentine wires (the length difference is less than 0.1 mm), and the gate paths are mirror-symmetrical, so that the parallel chip delay difference is less than 0.3 ns.

[0107] The PCB plate 7 is placed on the support positioning studs 3 and keeps a certain insulating distance from the substrate; the gate lead terminals 4 and the source lead terminals 5 are connected with the copper pads on the PCB plate 7 through the bonding wires 6; the support shell 8 is provided with three grooves on one side for positioning and fixing the gate lead terminals 4, the drain lead terminals and the source lead terminals 5; and the inside of the support shell 8 is filled with silica gel or injection molding process as an insulating medium.

[0108] Step 1: substrate preparation The drain metal substrate 1 adopts a copper-molybdenum composite plate (CuMo15, thermal conductivity 180 W / (m·K): Four positioning holes (Φ1.5±0.02mm) are laser punched The central axis through hole (Φ5.0±0.1mm) is EDM processed Step 2: chip mounting The power semiconductor chips 2 (4×SiC MOSFET, single-core specification 1200V / 80A) are welded on the substrate by using nano-silver solder paste (80Ag): Positioning accuracy: symmetrically distributed at a distance of ±0.1mm from the central axis Welding condition: peak temperature 245℃±5℃, H2 / N2 protective atmosphere Step 3: PCB interconnection The PCB plate 7 is made of high-frequency FR-4 base material (ε r =4.3, thickness 0.8mm): The copper pad surface is chemically plated with Ni / Au (thickness 3μm) The bonding wires 6 adopt ultrasonic wedge bonding (power 120mW, time 20ms) Step 4: shell assembly The support shell 8 is made of PPS engineering plastic (CTE 28ppm / ℃): Groove depth 2.0mm, terminal interference amount 0.05mm Back hole coaxiality error with substrate ≤±0.05mm.

[0109] Simulation experiment data 1、Cost comparison

[0110] 2、Electrical performance Parasitic inductance: 4.7nH (traditional discrete parallel > 15nH), switch loss reduction 18% (1200V / 100A double pulse test).

[0111] Current sharing effect: 4 chips in parallel under rated current, static current deviation ≤5%, dynamic switch current deviation ≤8%.

[0112] 3、Thermal performance (ANSYS simulation) Working condition: 4xSiC MOSFET (150A continuous current) No heat dissipation hole: maximum temperature 148℃; with coaxial hole: maximum temperature 133℃ (decrease 10%).

[0113] In summary, the discrete device packaging structure of the multi-chip parallel layout of the application, four semiconductor power chips are connected in parallel and integrated in a module unit, so that the power density is improved while the parasitic inductance of the whole device is reduced. At the same time, the power semiconductor chip is directly welded on the metal substrate, and low-cost materials such as lead terminals, PCB boards and bonding wires are used to realize the packaging integration of discrete devices "modularization", so that the packaging structure optimizes the switching performance of the device while significantly reducing the production cost; the application improves the current sharing characteristics between parallel chips through chip layout adjustment, PCB wiring optimization and lead terminal adjustment.

[0114] The above content only illustrates the technical idea of the application, and cannot limit the protection scope of the application. Any modification made according to the technical idea of the application on the basis of the technical scheme falls within the protection scope of the claims of the application.

Claims

1. A discrete device packaging structure with a multi-chip parallel layout, characterized in that, The device includes a drain metal substrate (1), which is disposed inside a support housing (8). A PCB board (7) is disposed above the drain metal substrate (1). The drain metal substrate (1) has an integrated drain terminal and is fixed by a groove in the support housing (8). A gate terminal (4) and a source terminal (5) are also disposed in the groove of the support housing (8). The gate terminal (4) and the source terminal (5) are respectively connected to the PCB board (7) by bonding wires (6). Multiple power semiconductor chips (2) are disposed on the drain metal substrate (1). The drain of the power semiconductor chip (2) is connected to the drain metal substrate (1), and the source and gate are respectively connected to the exposed copper pads on the PCB board (7) by bonding wires (6).

2. The discrete device packaging structure with multi-chip parallel layout according to claim 1, characterized in that, The drain metal substrate (1) has four positioning holes and a through hole along the central axis symmetrically formed.

3. The discrete device packaging structure with multi-chip parallel layout according to claim 1, characterized in that, The power semiconductor chip (2) is symmetrically distributed on both sides of the central axis of the drain metal substrate (1) to form a parallel circuit.

4. The discrete device packaging structure with multi-chip parallel layout according to claim 3, characterized in that, The power semiconductor chip (2) is a silicon MOSFET, IGBT or silicon carbide MOSFET, and the number is ≥2.

5. The discrete device packaging structure with multi-chip parallel layout according to claim 1, characterized in that, A support positioning stud (3) is embedded in the positioning hole of the drain metal substrate (1), and the PCB board (7) is placed on the support positioning stud (3).

6. The discrete device packaging structure with multi-chip parallel layout according to claim 5, characterized in that, The height of the support positioning stud (3) is 0.5~1.5mm to ensure that the distance between the PCB board (7) and the substrate is ≥0.3mm.

7. The discrete device packaging structure with multi-chip parallel layout according to claim 1, characterized in that, The bonding wires (6) are connected to the chip gate / source to the PCB board (7) with equal length paths, and the wiring of the gate lead-out terminal (4) is symmetrical with that of the power semiconductor chip (2).

8. The discrete device packaging structure with multi-chip parallel layout according to claim 1, characterized in that, A through hole is opened at the back center axis of the support housing (8) and is coaxially fitted with the through hole of the drain metal substrate (1).

9. The discrete device packaging structure with multi-chip parallel layout according to claim 1, characterized in that, The back of the supporting shell (8) is hollowed out and the interior is filled with a silicone gel layer.

10. The discrete device packaging structure with multi-chip parallel layout according to claim 1, characterized in that, The dielectric strength of the gel filler layer is ≥15kV / mm, and the thermal conductivity is ≥0.8W / (m·K).

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