Discrete device packaging structure based on direct lead bonding

Abstract

The invention discloses a discrete device packaging structure based on direct lead bonding, which belongs to the technical field of semiconductor device packaging and comprises a power semiconductor chip, a drain metal substrate, a grid lead terminal, a drain lead terminal, a bonding wire and a supporting shell. The drain electrode metal substrate is connected with the lower surface of the power semiconductor chip through solder. The gate metal electrode on the upper surface of the power semiconductor chip is connected with the gate lead terminal through a bonding wire, and the source metal electrode on the upper surface of the power semiconductor chip is connected with the source lead terminal through solder. The interior of the supporting shell is filled with silica gel or an injection molding process, and the supporting shell covers the power semiconductor chip to serve as an insulating medium. The power density of the device is improved, the parasitic parameter of the whole device is reduced, and the reliability of the interconnection structure is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power semiconductor packaging, and particularly relates to a discrete device packaging structure based on direct lead bonding. BACKGROUND

[0002] Power semiconductor devices, as the core devices of various power electronic conversion devices, play a crucial role in power systems. With the increase of power level in power systems, higher requirements are put forward for the power level of power semiconductor devices. In actual industrial applications, considering the material cost and design cost, discrete devices are often used in parallel to improve the capacity of power devices. However, the greater freedom and flexibility of parallel use of discrete devices can introduce a larger stray inductance to the commutation circuit, resulting in higher turn-off overvoltage, greater switching loss and higher temperature. At the same time, due to the increase of power density of power electronic conversion devices, the limited space inside the device limits the layout of discrete devices, which can easily lead to inconsistent parasitic parameters between parallel devices, resulting in uneven current distribution between parallel devices. The uneven current distribution can also cause uneven heating of parallel chips, and even thermal runaway problems, threatening the safety and stability of the entire system.

[0003] For power circuits, the traditional aluminum wire bonding interconnection method can introduce a larger parasitic inductance and has relatively low reliability, and has been gradually replaced by various new interconnection methods. Among them, the direct lead bonding (DLB) interconnection method can achieve higher reliability, longer power cycle life, more balanced current and temperature distribution. Therefore, the device packaged by using the DLB interconnection method can ensure the long-term safe and reliable operation of the power electronic system. SUMMARY

[0004] The technical problem to be solved by the application is to provide a discrete device packaging structure based on direct lead bonding to solve the technical problems of large parasitic parameters and uneven current in parallel discrete devices, and to control the cost, select the direct lead bonding interconnection method, adjust the structure of the lead frame, ensure the balance of current and temperature between chips on the basis of improving the power level of parallel chips, and significantly reduce the parasitic inductance inside the package. The model structure is simple and suitable for large-scale market promotion.

[0005] The application adopts the following technical solutions: A discrete device packaging structure based on direct lead bonding, comprising a drain metal substrate, the drain metal substrate integrally leading out a drain terminal, and a support shell is arranged on the drain metal substrate and fixed through a groove correspondingly arranged on the support shell. A plurality of power semiconductor chips are arranged in the support shell, the drain of the power semiconductor chip is connected with the drain metal substrate, and the gate and source of the power semiconductor chip are connected with the gate lead terminal and the source lead terminal respectively; the gate lead terminal and the source lead terminal are fixed through the corresponding grooves arranged on the support shell.

[0006] Preferably, the gate of the power semiconductor chip is connected with the gate lead terminal through a bonding wire, and the drain of the power semiconductor chip is connected with the drain lead terminal through solder.

[0007] Preferably, the plurality of power semiconductor chips are symmetrically distributed on both sides of the central axis of the drain metal substrate.

[0008] Preferably, the power semiconductor chip is a silicon MOSFET, an IGBT or a silicon carbide MOSFET.

[0009] Preferably, the two sides of the drain metal substrate are symmetrically protruded to form a step, and a through hole is formed at the central axis, the rear side of the support shell is symmetrically provided with two grooves on the left and right sides, the front side of the support shell is provided with three grooves, the front side grooves extend to the inside of the support shell to form a boss and a step, and the back of the support shell is provided with a hollow area.

[0010] Preferably, the side surface of the drain metal substrate 1 is protruded and embedded in the grooves on the rear side and the front side of the support shell.

[0011] Preferably, the gate lead terminal is embedded in the grooves on the left and right sides and the front side of the support shell, and the drain lead terminal is embedded in the groove on the front side of the support shell.

[0012] Preferably, the gate lead terminal is placed on the internal step of the support shell.

[0013] Preferably, the drain metal substrate is copper, aluminum or molybdenum.

[0014] Preferably, the inside of the support shell is filled through a silicone gel or injection molding process.

[0015] Compared with the prior art, the present application has at least the following beneficial effects: A discrete device packaging structure based on direct wire bonding, through four-chip parallel connection, realizes the improvement of power density of discrete devices, realizes the packaging integration at the level of discrete devices, and significantly reduces the parasitic inductance of the circuit compared with the parallel connection of multiple discrete devices, fully plays the integration advantage of the packaging structure; by adopting the interconnection mode of direct wire bonding, the reliability of the interconnection structure is improved, the current and heat flow between the parallel devices are more balanced, and the long-term safe and reliable operation of the devices is ensured; through the low-cost materials such as metal substrate, lead terminal, nylon shell and bonding wire, the packaging integration of discrete devices is realized, so that the overall switching performance of the device is optimized while the production cost is significantly reduced. At the same time, the packaging structure and manufacturing process proposed by the present application are simple, suitable for large-scale industrial promotion and use, and conducive to further reducing the production and manufacturing cost; the step of the nylon shell makes the gate, source and drain lead terminals maintain a sufficient distance, adjusts the distance between the lead terminals to provide sufficient insulation spacing, and uses silica gel filling as an insulating medium inside the package, and covers the power semiconductor chip, which improves the insulation strength of the packaging structure and further improves the reliability of the module.

[0016] Further, the gold / aluminum bonding wire is used to connect the gate, the flexible interconnection can absorb the difference in thermal expansion coefficient between the chip and the terminal, avoid mechanical stress damage to the gate oxide layer, and improve reliability; the source is directly connected to the terminal through solder, realizing a large-area low-resistance path and reducing on-resistance loss. Compared with the bonding wire scheme, the current-carrying capacity is improved by more than 30%, and the current sharing problem of multiple wire parallel connection is avoided.

[0017] Further, the chips are symmetrically arranged along the central axis, so that the heat source is uniformly distributed on the substrate, the thermal gradient of the substrate is reduced by 40%, and local overheating is avoided; the symmetric structure ensures that the lead lengths of each chip to the terminal are consistent, the parasitic inductance and resistance difference are less than 5%, dynamic current sharing is realized, and it is suitable for large-current parallel application.

[0018] Further, silicon carbide MOSFET is explicitly supported, its high-temperature characteristics match the copper substrate, and the high-temperature failure problem of traditional packaging is solved; silicon-based devices and SiC chips can share the packaging platform, only the bonding parameters need to be adjusted, and the cost of production line transformation is reduced.

[0019] Further, the substrate step and the shell groove form a mortise and tenon type engagement, the shear resistance is improved by 3 times, and it is suitable for vibration scenes; the back hollow area directly exposes the substrate, allowing double-sided heat dissipation. The central axis through hole promotes air convection, reduces thermal resistance by 15%; the front side groove extension boss realizes physical isolation of the gate / source terminals, meeting the high-voltage insulation requirements.

[0020] Further, the substrate side protrusion is embedded in the front and rear grooves to prevent drift in high-temperature reflow soldering; the lead terminal is fixed through a three-way groove without the need for additional clamps, and the assembly efficiency is improved by 25%. The groove depth controls the terminal height to ensure consistent bonding wire curvature.

[0021] Further, the gate lead terminal is placed on the internal step, and the bonding pressure is borne by the step instead of the chip surface to prevent chip cracking; the terminal height is flush with the chip gate Pad, the bonding wire length is reduced by 30%, and the parasitic inductance is reduced by 20%.

[0022] Further, copper is suitable for high-power density scenarios; aluminum is lightweight and low-cost; molybdenum CTE matches SiC chips to reduce thermal cycle fatigue; copper / aluminum can be formed by etching or stamping, and molybdenum substrates can be electroplated with Ni / Au to enhance solderability.

[0023] In summary, the application improves heat dissipation through integrated substrates, achieves current sharing and thermal balance through symmetrical layout, prevents vibration and drift through three-dimensional interlocking, optimizes bonding to reduce resistance and inductance, is compatible with silicon / carbonized silicon chips, and guarantees high reliability through dual-process filling.

[0024] The technical solutions of the application will be described in further detail below with the aid of the accompanying drawings and examples. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the application, the accompanying drawings intended to be used in the relative embodiment description are briefly introduced as follows. Obviously, the accompanying drawings in the following description are only some embodiments of the application, and other accompanying drawings can also be obtained by those skilled in the art without any creative effort on the basis of these accompanying drawings.

[0026] Figure 1 is a front isometric view of the discrete device packaging structure based on direct wire bonding of the application; Figure 2 is a top view of the discrete device packaging structure based on direct wire bonding of the application; Figure 3 is an exploded view of the discrete device packaging structure based on direct wire bonding of the application.

[0027] Wherein: 1. drain metal substrate; 2. power semiconductor chip, 3. gate lead terminal, 4. source lead terminal, 5. bonding wire, 6. support shell. DETAILED DESCRIPTION

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "one side," "one end," and "one side," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0030] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0031] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0032] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0033] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0034] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0035] This invention provides a discrete device packaging structure based on direct wire bonding. The drain metal substrate is connected to the lower surface (drain) of the power semiconductor chip via solder. The gate metal electrode on the upper surface of the power semiconductor chip is connected to the gate lead terminal via bonding wires, and the source metal electrode on the upper surface of the power semiconductor chip is connected to the source lead terminal via solder. The interior of the supporting shell is filled with silicone gel or injection molding to cover the power semiconductor chip as an insulating medium. This invention improves the power density of the device, reduces the overall parasitic parameters of the device, and improves the reliability of the interconnect structure.

[0036] Please see Figure 1 , Figure 2 and Figure 3 The present invention discloses a discrete device packaging structure based on direct wire bonding, comprising multiple power semiconductor chips 2, a drain metal substrate 1, a gate lead terminal 3, a drain lead terminal 4, bonding wires 5, and a supporting shell 8.

[0037] The drain metal substrate 1 has an integrated drain lead terminal 4, which is fixed in position by the groove of the supporting housing 6. The drain metal substrate 1 is connected to the lower surface (drain) of the power semiconductor chip 2 by solder. The gate and source are connected to the gate lead terminal 3 and the source lead terminal 4, respectively. The gate lead terminal 3 and the source lead terminal 4 are fixed in position by the groove of the supporting housing 6. The drains of the four power semiconductor chips 2 are connected to the drain metal substrate 1 by solder. The gate on the upper surface of the chip is connected to the gate lead terminal 3 by bonding wire 5, and the source is connected to the source lead terminal 4 by solder.

[0038] The gate metal electrode on the upper surface of the power semiconductor chip 2 is connected to the gate lead terminal 3 via bonding wire 5, and the source metal electrode on the upper surface of the power semiconductor chip 2 is connected to the source lead terminal 4 via solder. The interior of the discrete device package based on direct wire bonding is filled with silicone gel or injection molding process to cover the power semiconductor chip 2 as an insulating medium.

[0039] Multiple power semiconductor chips 2 are symmetrically distributed on both sides of the central axis of the drain metal substrate 1 and connected to the drain metal substrate 1 by solder. The power semiconductor chips 2 are silicon MOSFETs, IGBTs, and silicon carbide MOSFETs.

[0040] The gate of the power semiconductor chip 2 is connected to the gate lead terminal 3 via bonding wire 6, and the drain of the power semiconductor chip 2 is connected to the drain lead terminal 4 via solder.

[0041] The supporting shell 6 has two symmetrical grooves on the rear and sides, and three grooves on the front. The front grooves extend into the shell to form protrusions and steps, and the back of the shell has a large area of ​​openwork.

[0042] The side protrusions of the drain metal substrate 1 are embedded in the rear and front grooves, the gate lead terminal 3 is embedded in the two sides and the front groove, and the drain lead terminal 4 is embedded in the front groove; the drain lead terminal 3 and the source lead terminal 4 are embedded in the front groove of the support housing 6. At the same time, the gate lead terminal 3 is also embedded in the grooves on both sides of the support housing 6 and placed on the internal steps of the housing; the interior of the support housing 6 is filled with silicone gel or injection molding process as an insulating medium.

[0043] Preferably, the drain metal substrate 1 is made of copper, aluminum, or molybdenum.

[0044] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0045] Example 1 A discrete device packaging structure based on direct wire bonding is disclosed, in which four power semiconductor chips are connected in parallel and integrated into a module unit. This increases power density while reducing the overall parasitic inductance of the device. The direct wire bonding interconnection method improves the reliability of the interconnect structure and results in a more balanced current and heat flow among the parallel devices. Simultaneously, the use of low-cost materials such as lead terminals, metal substrates, and bonding wires significantly reduces production costs while optimizing device switching performance. Silicon gel is used as an insulating medium inside the package, covering the power semiconductor chips, which improves the insulation strength of the package structure and further enhances the reliability of the module.

[0046] Example 2 This embodiment provides a discrete device packaging structure based on direct wire bonding (DLB), with the core innovations being the interconnect scheme and low parasitic parameter design: Drain connection: The drain metal substrate 1 is directly connected to the back drain of the four power semiconductor chips 2 through high lead solder (Pb92.5Sn5Ag2.5) to form a low resistance path (resistance <0.1mΩ).

[0047] Source connection: The chip source is directly connected to the source lead terminal 4 via solder (SnAgCu), with a solder layer thickness ≤50μm, shortening the current path.

[0048] Gate connection: The gate is connected to the gate lead terminal 3 by copper bonding wire 5 (diameter 300μm) in an arc path of equal length, and the ultrasonic power of 120W ensures uniform interface IMC.

[0049] Ultrasonic wedge welding (pressure 2.5N, power 120W, time 20ms) was used to ensure the formation of a uniform Al2Cu intermetallic compound (IMC) layer at the copper-aluminum interface, with a bonding strength >15g / mil.

[0050] High-lead solder (melting point > 300℃) ensures high-temperature stability of the drain electrode; SnAgCu solder paste (melting point 217℃) balances source electrode connection efficiency and cost.

[0051] By using DLB technology, the commutator circuit area is reduced by 70%, the measured parasitic inductance is <8nH (compared to >15nH in traditional solutions), and the turn-off overvoltage is reduced by 40%.

[0052] The current imbalance of parallel chips is less than 5% (100A operating condition), and the uniformity of thermal resistance distribution is improved by 30%.

[0053] Through-hole design on substrate: A 2mm diameter through-hole is formed along the central axis of the drain metal substrate 1, which, together with the hollowed-out back shell 6, reduces the commutation circuit area to 5.2mm². 2 .

[0054] Symmetrical wiring: Four power semiconductor chips 2 are mirror-distributed along the central axis of the substrate, with gate bonding wire length deviation <0.1mm, eliminating impedance differences in parallel branches.

[0055] Comparison of measured electrical performance

[0056] Low thermal resistance path implementation The drain metal substrate 1 is made of copper (thermal conductivity 398W / m·K) with a thickness of 1mm, and the heat of the chip is directly transferred through the solder layer (thermal conductivity 80W / m·K).

[0057] Thermal simulation results (Flotherm): Junction-to-case thermal resistance 0.48 K / W (0.82 K / W in conventional scheme), maximum temperature difference between the four chips 3.7℃.

[0058] Power Cycle Life Verification In the cyclic test at ΔTj=80℃ (JESD22-A122), the DLB structure failed after more than 52,000 cycles, and the failure mode was fatigue cracking of the solder layer.

[0059] This embodiment achieves this through "three-level interconnection optimization + loop area minimization": Electrical aspects: parasitic inductance <8nH, turn-off overvoltage reduced by 40%, meeting the requirements of high-frequency switching; Current sharing aspect: Current imbalance <5%, ensuring long-term reliability of parallel chips; In terms of process technology: compatible with silicon / silicon carbide chips (650-1200V), reducing unit cost by 35%.

[0060] Application scenarios: Boost circuits in photovoltaic inverters, electric vehicle motor controllers, which can replace the traditional TO-247 parallel solution.

[0061] Example 3 This embodiment focuses on the contribution of the shell structure to reliability: Groove topology system Rear / Both sides: Two grooves are symmetrically opened to press against the raised step of the drain substrate 1 (tolerance ±0.05mm).

[0062] Front side: 3 recesses extend from the boss and steps, among which: The central recess secures the source lead terminal 4; The gate lead terminals 3 are fixed in layers in the grooves on both sides, with a step height difference of 1.2mm.

[0063] Terminal spacing ≥2.5mm, meeting 3000V insulation creepage requirements (IEC 60664 standard).

[0064] The large-area hollow design on the back, combined with silicone gel filling (thermal conductivity 0.2W / m·K), increases the thermal cycle life to 2.3 times that of traditional packaging (>50,000 cycles).

[0065] By forcibly controlling the terminal spacing (≥2.5mm) through a stepped structure, combined with silicone gel filling (dielectric strength >18kV / mm), the module's insulation withstand voltage is increased to 3.5kV (traditional packaging ≤2.2kV), meeting the 2500V insulation requirement of new energy vehicle OBCs. The hollowed-out back structure reduces thermal resistance by 35%, and combined with the thermal matching between the nylon shell (CTE=80ppm / ℃) and the metal substrate, the thermal cycle life reaches >52,000 cycles.

[0066] Example 4 Multi-chip parallel thermal-electrical balance control Symmetrical layout design Four power semiconductor chips (silicon / silicon carbide MOSFETs) are symmetrically distributed along the central axis of the drain substrate (1) (spacing ≤ 3 mm).

[0067] Drain solder connection, source solder direct connection terminal, gate equal-length bonding wire (length deviation < 0.1mm).

[0068] The substrate (1) has a through-hole design (diameter 2mm) to accelerate vertical heat dissipation, and the metal substrate (copper, 398W / m·K) makes the chip temperature difference <5℃.

[0069] Actual test results: Switching losses were reduced by 25% under 100A operating conditions, and thermal resistance (junction-case) was reduced to 0.5K / W.

[0070] Symmetrical layout and equal-length bond wires (length deviation <0.1mm) compress the parallel impedance difference to <3%, resulting in a current imbalance of only 4.3% under 100A operating conditions (industry average >10%), completely eliminating the risk of thermal runaway. Parasitic inductance is reduced to 7.6nH, resulting in a 25% reduction in switching losses of the 1200V SiC MOSFET (tested at 150℃ junction temperature), making it suitable for high-frequency applications above 50kHz.

[0071] Example 5 Low-cost materials and mass-producible processes The supporting shell 6 is made of nylon PA66 (costing 1 / 5 of ceramic, with a tensile strength of 80MPa).

[0072] The drain substrate 1 is compatible with aluminum / molybdenum stamping (thickness ≤ 1 mm), and the bonding wires are made of copper instead of gold.

[0073] Three-step assembly process Step 1: The protrusion of substrate 1 is inserted into the groove on the back side of the outer shell (interference allowance 0.1mm). Step 2: Solder the chip to the substrate and insert the lead terminals into the front groove step; Step 3: After bonding wire connection, fill with silicone gel (cure at 150℃).

[0074] The number of processes is reduced by 40%, the pass rate is greater than 98%, and the cost per unit is reduced by 40%.

[0075] Nylon shells replace ceramics, and stamped aluminum substrates replace DBC substrates, reducing the cost of materials per unit; the three-step assembly process (solder paste printing → terminal crimping → gel filling) is compatible with SMT production lines, with a mass production speed of 1200 pieces / hour and a yield of >98%.

[0076] In summary, this invention provides a discrete device packaging structure based on direct wire bonding, which simultaneously achieves high frequency and low loss, ultra-high reliability, and extreme cost control in discrete device packaging. It solves the problems of large parasitic parameters, poor current sharing, and high cost of traditional discrete devices connected in parallel, and provides a high-performance and cost-effective core device solution for new energy power electronic equipment.

[0077] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. A discrete device packaging structure based on direct wire bonding, characterized in that, It includes a drain metal substrate (1), the drain metal substrate (1) has an integrated drain terminal lead-out, and a support shell (6) is provided on the drain metal substrate (1) and fixed by a corresponding groove provided on the support shell (6); Multiple power semiconductor chips (2) are disposed inside the supporting shell (6). The drain of the power semiconductor chip (2) is connected to the drain metal substrate (1). The gate and source of the power semiconductor chip (2) are respectively connected to the gate lead terminal (3) and the source lead terminal (4). The gate lead terminal (3) and the source lead terminal (4) are fixed by corresponding grooves on the supporting shell (6).

2. The discrete device packaging structure based on direct wire bonding according to claim 1, characterized in that, The gate of the power semiconductor chip (2) is connected to the gate lead terminal (3) via bonding wire (5), and the drain of the power semiconductor chip (2) is connected to the drain lead terminal (4) via solder.

3. The discrete device packaging structure based on direct wire bonding according to claim 1, characterized in that, Multiple power semiconductor chips (2) are symmetrically distributed on both sides of the central axis of the drain metal substrate (1).

4. The discrete device packaging structure based on direct wire bonding according to claim 3, characterized in that, The power semiconductor chip (2) is a silicon MOSFET, IGBT or silicon carbide MOSFET.

5. The discrete device packaging structure based on direct wire bonding according to claim 1, characterized in that, The drain metal substrate (1) has symmetrical protrusions on both sides to form steps, and a through hole is opened at the central axis. The rear side of the support shell (6) has two grooves symmetrically opened on the left and right sides. The front side of the support shell (6) has three grooves. The front grooves extend into the support shell (6) to form bosses and steps. The back of the support shell (6) has a hollow area.

6. The discrete device packaging structure based on direct wire bonding according to claim 5, characterized in that, The side protrusions of the drain metal substrate 1 are embedded in the grooves on the rear and front sides of the supporting housing (6).

7. The discrete device packaging structure based on direct wire bonding according to claim 5, characterized in that, The gate lead terminal (3) is embedded in the grooves on the left and right sides and the front side of the support housing (6), and the drain lead terminal (4) is embedded in the groove on the front side of the support housing (6).

8. The discrete device packaging structure based on direct wire bonding according to claim 7, characterized in that, The gate lead terminal (3) is placed on the inner step of the supporting housing (6).

9. The discrete device packaging structure based on direct wire bonding according to claim 1, characterized in that, The drain metal substrate (1) is made of copper, aluminum, or molybdenum.

10. The discrete device packaging structure based on direct wire bonding according to claim 1, characterized in that, The interior of the supporting shell (6) is filled with silicone gel or injection molding.

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