Semiconductor device package and manufacturing method thereof

Abstract

The embodiment of the invention relates to a semiconductor device package and a manufacturing method thereof. A package substrate includes a first dielectric layer, a first patterned conductive layer, and a first set of alignment marks. The first patterned conductive layer is disposed on the first dielectric layer. The first set of alignment marks is disposed on the first dielectric layer and adjacent a first edge of the first dielectric layer. The first set of alignment marks includes a plurality of alignment marks. Distances between the alignment marks in the first set of alignment marks and the first edge are different from each other.

Description

[0001] Related Application

[0002] This application is a divisional application of the application with the application number “201910988197.7” and the title “Semiconductor Device Package and Method of Manufacturing the Same” filed on October 17, 2019.

[0003] Cross Reference to Related Applications

[0004] This application claims the benefit of and priority to U.S. Provisional Application No. 62 / 748,172, filed October 19, 2018, the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0005] The present disclosure relates to a semiconductor device package and a method of manufacturing the same, and to a semiconductor device package including a multilayer substrate and a method of manufacturing the same. BACKGROUND

[0006] Multilayer substrates are widely used in many semiconductor device packages. A multilayer substrate can include a plurality of layers (e.g., dielectric layers). Each of the layers has a patterned conductive layer. The alignment between any two layers of the substrate can be important for obtaining better. SUMMARY

[0007] According to some embodiments of the present disclosure, a package substrate includes a first dielectric layer, a first patterned conductive layer, and a first set of alignment marks. The first patterned conductive layer is disposed on the first dielectric layer. The first set of alignment marks is disposed on the first dielectric layer and adjacent to a first edge of the first dielectric layer. The first set of alignment marks includes a plurality of alignment marks. Distances between the alignment marks of the first set of alignment marks and the first edge are different from each other.

[0008] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device package includes: (a) providing a substrate; (b) disposing an electronic component on the substrate; and (c) forming a package on the substrate to cover the electronic component. The substrate includes a first dielectric layer, a first patterned conductive layer, and a first set of alignment marks. The first patterned conductive layer is disposed on the first dielectric layer. The first set of alignment marks is disposed on the first dielectric layer and adjacent to a first edge of the first dielectric layer. The first set of alignment marks includes a plurality of alignment marks. Lengths of the alignment marks of the first set of alignment marks are different from each other.

[0009] According to some embodiments of the disclosure, a method for manufacturing a semiconductor device package includes (a) providing a substrate; (b) disposing an electronic component on the substrate; and (c) forming a package on the substrate to cover the electronic component. The substrate has a first dielectric layer, a first patterned conductive layer, and a first set of alignment marks. The first patterned conductive layer is disposed on the first dielectric layer. The first set of alignment marks is disposed on the first dielectric layer and adjacent to a first edge of the first dielectric layer. The first set of alignment marks includes a plurality of alignment marks. Distances between the alignment marks in the first set of alignment marks and the first edge are different from each other. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1A Illustration of a perspective view of a substrate according to certain comparative techniques.

[0011] Figure 1B Illustration of a perspective view of a substrate according to certain comparative techniques.

[0012] Figure 1C Image showing a cross-sectional view of a substrate according to certain comparative techniques.

[0013] Figure 2 Illustration of a top view of one layer of a substrate according to some embodiments of the disclosure.

[0014] Figure 3A Illustration of a perspective view of a substrate according to some embodiments of the disclosure.

[0015] Figure 3B Illustration of a perspective view of a substrate according to some embodiments of the disclosure.

[0016] Figure 4A Illustration of a perspective view of a substrate according to some embodiments of the disclosure.

[0017] Figure 4B Illustration of a perspective view of a substrate according to some embodiments of the disclosure.

[0018] Figure 5 Illustration of a perspective view of a substrate according to some embodiments of the disclosure.

[0019] Figure 6A Illustration of a top view of one layer of a substrate according to some embodiments of the disclosure.

[0020] Figure 6B Illustration of a perspective view of a substrate according to some embodiments of the disclosure.

[0021] Figure 7A 、 Figure 7B 、 Figure 7C and Figure 7DA method of fabricating a semiconductor device package according to some embodiments of the disclosure is described.

[0022] Figure 8 A cross-sectional view of a semiconductor device package according to some embodiments of the disclosure is described.

[0023] Common reference numerals are used throughout the drawings and implementations to indicate the same or similar components. The disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings, in which: DETAILED DESCRIPTION

[0024] Figure 1A A cross-sectional view of a substrate package according to certain comparative techniques is described. The substrate package includes a substrate 10 and a patterned conductive layer (e.g., a redistribution layer (RDL) or an antenna radiation pattern) disposed within the substrate 10. The substrate 10 can be a multilayer substrate including a core structure 10a, dielectric layers 10b, 10c, and protective layers 10d, 10e (e.g., layers including solder resist or resist). The core structure 10a may, for example, be selected from, but not limited to, a silicon substrate, a plastic substrate, or a ceramic substrate. The dielectric layers 10b and 10c are disposed on the top and bottom surfaces of the core structure 10a, respectively. Each of the dielectric layers 10b and 10c can include a material such as polypropylene (PP), bismaleimide triazine (BT) resin, epoxy resin, polyimide (PI), or other dielectric material. The dielectric layers 10b and 10c can include the same material as each other or can include different materials. In other embodiments, the substrate 10 can be a coreless multilayer substrate that omits the core structure and includes a plurality of dielectric layers (or sub-layers).

[0025] One or more layers of the substrate 10 include a patterned conductive layer. For example, as shown in Figure 1A The patterned conductive layer can be disposed on the core structure 10a and the dielectric layers 10b and 10c, for example. For example, the patterned conductive layer can be disposed on both surfaces of the core structure 10a. For example, the patterned conductive layer can be disposed on the top surface of the dielectric layer 10b and covered by the protective layer 10d. For example, the patterned conductive layer can be disposed on the bottom surface of the dielectric layer 10c and covered by the protective layer 10e.

[0026] The substrate 10 includes one or more sets of alignment marks (e.g., a first set of alignment marks 10ml, a second set of alignment marks 10m2, a third set of alignment marks 10m3, and a fourth set of alignment marks 10m4 on the sides of the layers of the substrate 10), and each of the sets of alignment marks has the same number of alignment marks. The pitch of the alignment marks is substantially the same. For example, the distance between any two adjacent alignment marks is substantially the same. The width of the alignment marks is substantially the same. In some embodiments, the width of each alignment mark is about 20 micrometers (pm).

[0027] Several sets of alignment marks 10m1, 10m2, 10m3, and 10m4 can be used to determine whether the layers of the substrate 10 (and the patterned conductive layers within the substrate 10) are aligned with each other. For example, as shown in Figure 1A The alignment marks 10m1, 10m2, 10m3, and 10m4 of the substrate 10 are aligned with each other, and thus it is determined that the layers of the substrate 10 (and the patterned conductive layers within the substrate 10) are aligned with each other. In other words, the shift, deviation, or drift is minimized or reduced in the layers of the substrate 10.

[0028] As shown in Figure 1B The set of alignment marks 10m2 (the second set from the top) is misaligned with the other sets of alignment marks 10m1, 10m3, and 10m4, and thus it is determined that the core structure 10a on which the set of alignment marks 10m2 is disposed has a shift, deviation, or drift. The distance or amount of shift, deviation, or drift of the layer 10b can be determined based on the position of the set of alignment marks 10m2 relative to the position of the set of alignment marks 10m1 or 10m3.

[0029] Due to limitations in manufacturing the alignment marks, the pitch of the alignment marks can be limited (e.g., the minimum pitch of the alignment marks is about 20 pm to about 25 pm), reducing the accuracy for determining the shift, deviation, or drift. In addition, as shown in Figure 1C It can be difficult to measure the shift distance of the alignment marks, Figure 1C to show an image of a substrate including alignment marks.

[0030] Figure 2 A top view of a portion (e.g., a quarter of the layer) of one layer of a multilayer substrate according to some embodiments of the disclosure (e.g., the substrate 20 as shown in Figure 3A or Figure 3B A top view of a portion (e.g., a quarter of the layer) of one layer of a multilayer substrate according to some embodiments of the disclosure (e.g., the substrate 20 as shown in Figure 2 The substrate 20 as illustrated in Figure 1A is similar to the substrate 10 as illustrated in Figure 2 Some descriptions of the substrate 10 can apply to the substrate 20 in Figure 2 The depicted layers of the substrate 20 include a circuit region 22 (which can extend beyond the lower right corner of the layer as shown in

[0031] The layers of the substrate 20 include several sets of alignment marks 20m1, 20m2, and each set of alignment marks includes multiple alignment marks. It should be noted that in some other embodiments, a substrate or a layer of a substrate can include a single set (only one set) of alignment marks. The several sets of alignment marks 20m1 and 20m2 are located at the spaces (e.g., side rails) between the edges of the layers of the substrate 20 and the circuit region 22. The set of alignment marks 20m1 is disposed along the edge 201. The set of alignment marks 20m2 is disposed along the edge 202. As shown in Figure 2 The lengths of the alignment marks in the several sets of alignment marks 20m1 and 20m2 are different from each other, as shown in

[0032] The substrate 20 can include multiple layers, each having the same and / or similar patterned conductive layers and alignment marks as shown in Figure 2 Figure 3A or Figure 3B The circuit region 22 and the several sets of alignment marks 20m1, 20m2 of the layers of the substrate 20 are aligned with each other. If there is minimal or no shift, deviation, or drift in any of the layers of the substrate 20, then each layer of the substrate 20 should have the same number of alignment marks on its side as shown in Figure 3A or Figure 3B For example, as shown in Figure 3A ​As shown, each of the layers in substrate 20 has an alignment mark on its side, thus ensuring that there is no displacement, misalignment, or drift in any of the layers in substrate 20. Similarly, as Figure 3B As shown, each of the layers in substrate 20 has three alignment marks on its side, thus ensuring that there is no displacement, deviation or drift in any of the layers in substrate 20.

[0033] Figure 3A The structure and Figure 3B One difference between the structures is the number of alignment marks displayed on the sides of each layer of substrate 20. The number of alignment marks ranges from... Figure 3A and Figure 3B One of the reasons for the side exposure of each layer of substrate 20, as described herein, is that during the monomerization operation of the substrate strip, the side exposure is used for... Figure 3B The cutting device for substrate 20 described herein is relatively wide.

[0034] Figure 4A and Figure 4B This is a perspective view illustrating a substrate 20 according to some embodiments of the present disclosure, showing a situation where one of the layers of the substrate 20 is displaced, misaligned, or drifted. (See diagram below.) Figure 4A and Figure 4B As shown, the number of alignment marks in a set of alignment marks on the side surface of one layer of substrate 20 differs from the number of alignment marks in other sets of alignment marks on the side surfaces of other layers of substrate 20. For example, as Figure 4A As shown, the number of alignment marks in the group of alignment marks 20m1' on the side surface of the layer of substrate 20 is different from (greater than) the number of alignment marks in other groups of alignment marks 20m1, 20m1”, and 20m1”’ on the side surface of other layers of substrate 20, and therefore it is determined that the layer on which the group of alignment marks 20m1' is positioned has displacement, deviation, or drift. Similarly, as Figure 4B As shown, the number of alignment marks in the group of alignment marks 20m1” on the side surface of the layer of substrate 20 is different from (greater than) the number of alignment marks in other groups of alignment marks 20m1, 20m1' and 20m1”' on the side surface of other layers of substrate 20, and therefore it is determined that the layer on which the group of alignment marks 20m1” is positioned has displacement, deviation or drift. In other words, whether the layer of substrate 20 has displacement, deviation or drift can be determined based on the number of alignment marks shown on the side surface of the layer of substrate 20.

[0035] Furthermore, the distance of shift, deviation, or drift of the layers of substrate 20 can be determined based on the number of alignment marks via the shifted layer relative to the number of alignment marks without any other shifted layer. For example, such as Figure 4AAs shown, the layer on which the alignment mark 20m1' is positioned has two more alignment marks on its side surface than the other alignment marks in the other sets of alignment marks 20m1, 20m1" and 20m1"' on the side surface of other layers. Therefore, the displacement distance of the shifted layer relative to other unshifted layers is 2×N, where N is the length difference between two adjacent alignment marks. For example, if N is 5 μm, then the displacement distance of the second layer is approximately 10 μm. Similarly, as... Figure 4B As shown, the layer with the alignment mark 20m1” positioned thereon has four more alignment marks on its side than the other alignment marks 20m1', 20m1', and 20m1”' on the side of other layers. Therefore, the displacement distance of the third layer relative to the other layers is 4×N, where N is the length difference between two adjacent alignment marks.

[0036] In some embodiments, alignment marks may be displayed on two adjacent sides of each layer of substrate 20, such as Figure 5 As shown in the figure, the displacement, deviation, or drift of the layer can be measured in both the x and y directions.

[0037] Figure 6A A top view illustrating a portion (e.g., a quarter of a layer) of a multilayer substrate according to some embodiments of the present disclosure. Figure 6A The structure described in the text is similar to Figure 2 The structure in, and one of the differences between them is Figure 6A The alignment marks in the several sets of alignment marks 60m1 and 60m2 described herein are aligned with the edges 201 and 202 of the substrate layer, respectively, by means of drawing. Therefore, as Figure 6B As shown, if a layer of the substrate is displaced, misaligned, or drifted, the number of alignment marks on the side of the displaced layer of the substrate (e.g., the layer on which the set of alignment marks 60m1' is positioned) is less than the number of alignment marks in the sets of alignment marks 60m1, 60m1”, and 60m1”' on the other sides of the substrate that are not displaced.

[0038] according to Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5 , Figure 6A and Figure 6B In this embodiment, since the displacement distance is determined by the number of alignment marks displayed on the side of the displacement layer relative to the number of alignment marks displayed on the side without the displacement layer, it is possible to measure the displacement distance easily and accurately. Furthermore, the component used to determine the displacement distance is based on the length difference between two adjacent alignment marks—rather than by means such as... Figure 1Aand 1B The width of the alignment mark shown in the figure is used to determine this, which can provide greater accuracy when determining the displacement distance.

[0039] Figure 7A , Figure 7B , Figure 7C and Figure 7D This invention describes a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure.

[0040] refer to Figure 7A A substrate strip 70 comprising multiple multilayer substrates (e.g., substrate 20) is provided. As shown in FIG. 7, alignment marks may be positioned corresponding to each row and column of substrates. In other embodiments, alignment marks may be selectively positioned (e.g., at the four corners or edges of the substrate strip 70). In some embodiments, each substrate of the substrate strip 70 may also include alignment marks. Therefore, it is easier to determine which column or row of substrates contains displacement, misalignment, or drift. Additionally, if it is determined that a column or row of substrates contains displacement, misalignment, or drift, it is easier to determine which substrate in that column or row contains displacement, misalignment, or drift.

[0041] refer to Figure 7B Electronic components 71 (e.g., dies or chips) are bonded to each of the substrate.

[0042] refer to Figure 7C Package 72 is formed on substrate strip 70 to cover or encapsulate electronic component 71. In some embodiments, package 72 may be formed by, for example, transfer molding, compression molding or any other molding technique.

[0043] refer to Figure 7D Monomerization can be performed to separate individual semiconductor package devices. That is, monomerization is performed through the package 72 and the substrate strip 70 comprising multiple multilayer substrates (e.g., substrate 20). For example, monomerization can be performed using a dicing machine, laser, or other suitable dicing techniques.

[0044] Figure 8 This describes a semiconductor device package 8 according to some embodiments of the present disclosure. The semiconductor device package 8 includes a substrate 80, electronic components 81a, 81b, a package body 82, and electrical contacts 83. In some embodiments, the semiconductor device package 8 may use... Figure 7A , Figure 7B , Figure 7C and Figure 7D The operations shown in the document or any other appropriate manufacturing process are formed.

[0045] In some embodiments, substrate 80 is a multilayer substrate. For example, substrate 80 may be or may contain... Figure 1A ,Figure 1B Figure 2 Figure 3A Figure 3B Figure 4A Figure 4B Figure 5 Figure 6A Figure 6B Substrate 80 has a surface 801 and a surface 802 opposite surface 801.

[0046] Electrical components 81a and 81b are disposed on top surface 801 of substrate 80. Electrical component 81a can be an active component, such as an integrated circuit (IC) chip or die. Electrical component 81b can be a passive electrical component, such as a capacitor, resistor, or inductor. Each electrical component 81a and 81b can be electrically connected to one or more of the other electrical components 81a and 81b and / or to substrate 80 (e.g., to an RDL), and the electrical connections can be obtained by means of flip-chip or wire bonding techniques.

[0047] Encapsulant 82 is disposed on surface 801 of substrate 80 and encapsulates surface 801 of substrate 80 and a portion of electrical components 81a and 81b. In some embodiments, encapsulant 82 includes an epoxy resin having a filler dispersed therein.

[0048] Electrical contacts 83 (e.g., solder balls) are disposed on surface 802 of substrate 80 and can provide electrical connections between semiconductor device package 8 and external components (e.g., external circuitry or a circuit board). In some embodiments, electrical contacts 83 include controlled collapse chip connections (C4) bumps, ball grid array (BGA), or land grid array (LGA).

[0049] In some embodiments, semiconductor device package 8 can be formed by a process including: (i) providing substrate 80; (ii) disposing electronic components 81a and 81b on surface 801 of substrate 80; (iii) forming encapsulant 82 on surface 801 of substrate 80 to cover electronic components 81a and 81b; and (iv) forming electrical components 83 on surface 802 of substrate 80.

[0050] ​​​​​​​​As used herein, the terms“substantially,”“essentially,”“approximately,” and“about” are used to describe and account for small variations. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation of ±10% or less of the numerical value, such as ±5% or less, ±4% or less, ±3% or less, ±2% or less, ±1% or less, ±0.5% or less, ±0.1% or less, or ±0.05% or less of the variation. As another example, a thickness of a film or layer that is“substantially uniform” can refer to a standard deviation of less than or equal to ±10% of the average thickness of the film or layer, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05% of the standard deviation. The term“substantially coplanar” can refer to two surfaces that are within microns along the same plane, such as within 40 pm, within 30 pm, within 20 pm, within 10 pm, or within 1 pm along the same plane. Two surfaces or components can be considered“substantially perpendicular” if an angle between the two surfaces or components is, for example, 90° ± 10° (such as ±5°, ±4°, ±3°, ±2°, ±1°, ±0.5°, ±0.1°, or ±0.05°). When used in conjunction with an event or circumstance, the terms“substantially,”“essentially,”“approximately,” and“about” can refer to instances in which the event or circumstance occurs exactly as well as instances in which the event or circumstance occurs approximately.

[0051] As used herein, the singular terms“a,”“an,” and“the” can include plural referents unless the context clearly dictates otherwise. In describing some embodiments, components that are“on” or“over” another component, can encompass cases where the component is directly on the other component (e.g., in physical contact with the other component) as well as cases where one or more intervening components are present.

[0052] As used herein, the terms“conductive,”“electrically conductive,” and“conductivity” refer to the ability to transport an electric current. Conductive materials generally refer to those materials that exhibit little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Generally, conductive materials are materials that have a conductivity greater than about 10 4 S / m (e.g., at least 10 5 S / m or at least 10 6 S / m). The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0053] Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood as having been preceeded by the words "comprising at least one of" and followed by the words "consisting of' or "consisting essentially of' so as to render equally valid the claim both in its "permeable" and its "impermeable" interpretation. It must be noted that as used herein and in the appended claims, the singular forms "a", "an" and "the" include plural reference unless the context clearly dictates otherwise. Thus, for example, a reference to "a component" is a reference to one or more components and includes the possibilities of a single component and plural components.

[0054] While the disclosure has been described and illustrated with reference to specific embodiments thereof, those skilled in the art will appreciate that various adaptations, changes, modifications, substitutions, deletions, or additions of procedures and protocols can be made without departing from the true spirit and scope of the disclosure. It is understood that the specification and figures are illustrative in nature and not restrictive. Modifications can be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the disclosure. All such modifications are intended to be within the scope of the claims. Although methods disclosed herein have been described with reference to particular sequences, it is to be understood that these sequences have been presented for illustration and explanation only and are not a limitation. It is further understood that the sequences can be combined, subdivided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Therefore, unless specifically indicated, the order and grouping of operations are not limitations of the disclosure.

Claims

1. A package substrate, comprising: a first dielectric layer; a first set of alignment marks disposed on the first dielectric layer and adjacent to a first edge of the first dielectric layer, the first set of alignment marks including a plurality of alignment marks, wherein distances between the plurality of alignment marks in the first set of alignment marks and the first edge are different from one another; a second dielectric layer disposed on the first dielectric layer; and a second set of alignment marks disposed on the second dielectric layer and adjacent to a second edge of the second dielectric layer, the second set of alignment marks including a plurality of alignment marks, wherein distances between the plurality of alignment marks in the second set of alignment marks and the second edge are different from one another.

2. The package substrate of claim 1, wherein the first dielectric layer has a first corner adjacent to the first edge, and lengths of the plurality of alignment marks in the first set of alignment marks are shorter closer to the first corner in a direction generally parallel to the first edge.

3. The package substrate of claim 2, wherein the first dielectric layer has a third edge adjacent to the first edge, the first edge and the third edge defining the first corner, lengths of the plurality of alignment marks in the first set of alignment marks are longer farther from the third edge.

4. The package substrate of claim 2, wherein the second dielectric layer has a second corner adjacent to the second edge, and lengths of the plurality of alignment marks in the second set of alignment marks are longer closer to the second corner in a direction generally parallel to the second edge.

5. The package substrate of claim 4, wherein the second corner is generally coincident with the first corner.

6. The package substrate of claim 1, wherein the first set of alignment marks is arranged along the first edge, and the second set of alignment marks is arranged along the second edge, the first edge and the second edge are not parallel to one another.

7. The package substrate of claim 6, wherein lengths of the plurality of alignment marks in the first set of alignment marks are longer farther from the second set of alignment marks.

8. The package substrate of claim 6, wherein lengths of the plurality of alignment marks in the second set of alignment marks are shorter farther from the first set of alignment marks.

9. The package substrate of claim 1, further comprising: a first patterned conductive layer disposed on the first dielectric layer, wherein the first set of alignment marks is closer to the first edge than the first patterned conductive layer.

10. The package substrate of claim 9, further comprising: a second patterned conductive layer disposed on the second dielectric layer, wherein the second set of alignment marks is closer to the second edge than the second patterned conductive layer.

11. The package substrate of claim 1, further comprising: a substrate strip including a plurality of substrates, wherein the plurality of substrates are arranged in rows and columns, and wherein the first set of alignment marks and the second set of alignment marks are disposed at edges of the substrate strip. ​ 12. A package substrate, comprising: a first dielectric layer; a first set of alignment marks disposed on the first dielectric layer and adjacent to a first edge of the first dielectric layer, the first set of alignment marks including a plurality of alignment marks, wherein lengths of the plurality of alignment marks in the first set of alignment marks differ from one another; a second dielectric layer disposed on the first dielectric layer; and a second set of alignment marks disposed on the second dielectric layer and adjacent to a second edge of the second dielectric layer, the second set of alignment marks including a plurality of alignment marks, wherein lengths of the plurality of alignment marks in the second set of alignment marks differ from one another.

13. The package substrate of claim 12, wherein the first dielectric layer has a first corner adjacent to the first edge, and in a direction generally parallel to the first edge, distances between the plurality of alignment marks in the first set of alignment marks and the first edge are farther away from the first corner.

14. The package substrate of claim 12, wherein widths of the plurality of alignment marks in the first set of alignment marks differ from one another.

15. The package substrate of claim 12, wherein pitches of the plurality of alignment marks in the first set of alignment marks are generally equal to one another.

16. The package substrate of claim 12, further comprising: a patterned conductive layer disposed on the first dielectric layer, wherein the first set of alignment marks is closer to the first edge than the patterned conductive layer, and the second set of alignment marks is closer to the second edge than the patterned conductive layer.

17. The package substrate of claim 12, further comprising: a substrate strip including a plurality of substrates, wherein the plurality of substrates are arranged in rows and columns, wherein the first set of alignment marks and the second set of alignment marks are disposed at edges of the substrate strip.

18. A method for manufacturing a semiconductor device package, comprising: providing a substrate having a first dielectric layer, a first set of alignment marks disposed on the first dielectric layer and adjacent to a first edge of the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, and a second set of alignment marks disposed on the second dielectric layer and adjacent to a second edge of the second dielectric layer, the first set of alignment marks including a plurality of alignment marks, and the second set of alignment marks including a plurality of alignment marks, wherein distances between the plurality of alignment marks in the first set of alignment marks and the first edge differ from one another, and lengths of the plurality of alignment marks in the second set of alignment marks differ from one another, wherein at least one alignment mark in the first set of alignment marks is exposed from a side of the first dielectric layer; and disposing an electronic component on the substrate.

19. The method of claim 18, further comprising: forming an encapsulation on the substrate to cover the electronic component.

20. The method of claim 19, further comprising: performing a dicing operation through the encapsulation and the substrate to singulate the substrate into a plurality of units.

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