Control method of interleaved parallel PFC (Power Factor Correction) circuit

Abstract

The invention relates to a control method of an interleaving parallel PFC circuit, the interleaving parallel PFC circuit comprises m parallel PFC branches, and the control method comprises the following steps: selecting an interleaving parallel operation mode of the interleaving parallel PFC circuit based on an actual power parameter and a critical parameter of the interleaving parallel PFC circuit; the interlaced parallel operation mode comprises a full-path interlaced operation mode, a partial interlaced operation mode and a non-interlaced operation mode; when the partial interleaving operation mode is selected, selecting an interleaving number n based on the loss parameter of each parallel PFC branch; wherein m and n are positive integers, m is greater than n, and m is greater than or equal to 3. By implementing the control method of the interleaving PFC circuit, loss increase caused by inadaptation of an interleaving operation mode of the interleaving PFC circuit can be reduced, the overall loss is reduced, and the overall efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power factor correction (PFC) control, in particular to a control method of an interleaved parallel PFC circuit. BACKGROUND

[0002] For a high-power PFC (power factor correction) circuit, when it works in a DCM (discontinuous conduction mode), a CrM (critical conduction mode) or a TCM (triangular current mode), zero-voltage turn-on or zero-current turn-on of a switching tube can be realized, so as to greatly reduce switching loss of the system and improve switching frequency of the system. However, a single-path DCM / CrM / TCM state PFC circuit has the defects of too large current ripple and too high peak current of the switching tube, so an interleaved parallel mode is usually used to share current stress and reduce input current ripple. However, in actual application, the control method of the existing interleaved parallel PFC circuit has the following problems: in a light load condition, there is a large redundancy, and in a lower power, the reduction of the on-state loss of the multi-path interleaved parallel is limited, but the switching loss is additionally increased, so that the total loss is increased and the light load efficiency is reduced. SUMMARY

[0003] The technical problem solved by the present application is to provide a control method of an interleaved parallel PFC circuit, which can reduce system loss and improve system efficiency, in view of the above defects of the prior art.

[0004] The technical solution adopted by the present application to solve the technical problem is: a control method of an interleaved parallel PFC circuit is constructed, the interleaved parallel PFC circuit includes m parallel PFC branches, and the control method includes:

[0005] selecting an interleaved parallel operation mode of the interleaved parallel PFC circuit based on the obtained actual power parameters and critical parameters of the interleaved parallel PFC circuit, wherein the interleaved parallel operation mode includes a full-path interleaved operation mode, a partial interleaved operation mode and a non-interleaved operation mode, the full-path interleaved operation mode is an operation mode in which all PFC branches participate in interleaving, the partial interleaved operation mode is an operation mode in which only part of the PFC branches participate in interleaving, and the non-interleaved operation mode is an operation mode in which no PFC branch participates in interleaving;

[0006] when the partial interleaving mode is selected, selecting the interleaving number n based on the loss parameter of each parallel PFC branch in the m-parallel PFC branches;

[0007] wherein m and n are positive integers, m is greater than n, and m is greater than or equal to 3.

[0008] In the control method of the interleaving parallel PFC circuit, the selecting of the interleaving number n based on the loss parameter of each parallel PFC branch in the m-parallel PFC branches comprises:

[0009] For each PFC branch, the loss parameter of the PFC branch is calculated, and the loss parameter of the PFC branch is refined by using the current parameter; based on the loss parameter of each parallel PFC branch, the total loss parameter of the interleaving parallel PFC circuit is calculated and minimized to calculate the interleaving number n.

[0010] In the control method of the interleaving parallel PFC circuit, the calculating of the loss parameter of each PFC branch and the refining of the loss parameter of each PFC branch by using the current parameter comprises:

[0011] The loss parameter of each parallel PFC branch is calculated based on the following formula:

[0012] P loss_per =P MOS_sw +P MOS_cond +P L_Cu +P L_Fe

[0013] wherein P MOS_sw represents the switching loss of the switching tube of the parallel PFC branch, P MOS_cond represents the conduction loss of the switching tube of the parallel PFC branch, P L_Cu represents the line loss of the inductor of the parallel PFC branch, P L_Fe represents the core loss of the inductor of the parallel PFC branch.

[0014] The refining of the loss parameter of each parallel PFC branch by using the current parameter is as follows:

[0015]

[0016] wherein C ds represents the equivalent parallel capacitance of the switching tube of the parallel PFC branch, f represents the switching frequency of the parallel PFC branch; V ds represents the drain-source voltage of the switching tube of the parallel PFC branch; I rms represents the current effective value of the parallel PFC branch, R ds_onR represents the on-resistance of the switch tube of the parallel PFC branch L_DC R represents the DC impedance of the inductance of the parallel PFC branch L_AC I represents the AC impedance of the inductance of the parallel PFC branch AC_rms K, a, b represent the inductance material constant of the parallel PFC branch, V e I represents the volume of the inductance of the parallel PFC branch pk N represents the number of turns of the inductance of the parallel PFC branch, A e R represents the magnetic circuit cross-sectional area value of the inductance of the parallel PFC branch.

[0017] In the control method of the interleaved parallel PFC circuit, the total loss parameter of the interleaved parallel PFC circuit is calculated based on the loss parameter of each parallel PFC branch, and the total loss parameter is minimized to calculate the interleaving number n, which comprises

[0018] Define i n As the current of each parallel PFC branch when n parallel interleaving, define P loss_per_n = f(i n ) is the loss parameter of each parallel PFC branch when n parallel interleaving, wherein f() represents the relationship function between current i n and loss parameter P loss_per_n ;

[0019] Solve the following standard formula to calculate the total loss parameter of the interleaved parallel PFC circuit, and minimize the total loss parameter to calculate the interleaving number n:

[0020] Minimization target:

[0021] Constraint condition: 1≤n≤m.

[0022] In the control method of the interleaved parallel PFC circuit, further comprising:

[0023] Select n parallel PFC branches for interleaved parallel in the interleaved parallel PFC circuit based on the operating parameters; the operating parameters include time parameters or temperature parameters.

[0024] In the control method of the interleaved parallel PFC circuit, when the operating parameters include time parameters, the n parallel PFC branches for interleaved parallel in the interleaved parallel PFC circuit are selected based on the operating parameters, comprising:

[0025] Record the running time of each parallel PFC branch in real time;

[0026] when the difference between the running time of the longest running parallel PFC branch and the running time of the shortest running parallel PFC branch is greater than a first set threshold, the longest running parallel PFC branch is closed and the shortest running parallel PFC branch is opened.

[0027] In the control method of the interleaved parallel PFC circuit, when the running parameter comprises a temperature parameter, the selection of the n parallel PFC branches for interleaved parallel in the interleaved parallel PFC circuit based on the running parameter comprises:

[0028] the running temperature of each parallel PFC branch is recorded in real time;

[0029] when the difference between the running temperature of the parallel PFC branch with the maximum running temperature and the running temperature of the parallel PFC branch with the minimum running temperature is greater than a second set threshold, the parallel PFC branch with the maximum running temperature is closed and the parallel PFC branch with the minimum running temperature is opened.

[0030] In the control method of the interleaved parallel PFC circuit, the selection of the interleaved parallel operation mode of the interleaved parallel PFC circuit based on the actual power parameter and the critical parameter of the interleaved parallel PFC circuit comprises:

[0031] when the actual power parameter is greater than a first critical parameter, the interleaved parallel operation mode of the interleaved parallel PFC circuit is selected as a full-path interleaved operation mode;

[0032] when the actual power parameter is less than a second critical parameter, the interleaved parallel operation mode of the interleaved parallel PFC circuit is selected as a non-interleaved operation mode;

[0033] when the actual power parameter is between the first critical parameter and the second critical parameter, the interleaved parallel operation mode of the interleaved parallel PFC circuit is selected as a partial-interleaved operation mode;

[0034] the first critical parameter is greater than the second critical parameter.

[0035] In the control method of the interleaved parallel PFC circuit, the selection of the interleaved parallel operation mode of the interleaved parallel PFC circuit based on the actual power parameter and the critical parameter of the interleaved parallel PFC circuit comprises:

[0036] when the interleaved parallel PFC circuit is in the partial-interleaved operation mode and the actual power parameter is greater than a first critical parameter, the interleaved parallel PFC circuit is switched to the full-path interleaved operation mode;

[0037] switching the interleaved parallel PFC circuit to the partial interleaving operation mode when the interleaved parallel PFC circuit is in the full interleaving operation mode and the actual power parameter is less than a third critical parameter;

[0038] switching the interleaved parallel PFC circuit to the partial interleaving operation mode when the interleaved parallel PFC circuit is in the full interleaving operation mode and the actual power parameter is less than a third critical parameter;

[0039] switching the interleaved parallel PFC circuit to the partial interleaving operation mode when the interleaved parallel PFC circuit is in the full interleaving operation mode and the actual power parameter is less than a third critical parameter;

[0040] wherein the first critical parameter > the third critical parameter > the second critical parameter > the fourth critical parameter.

[0041] In the control method of the interleaved parallel PFC circuit, when the partial interleaving operation mode is selected, the number of interleaving n is further selected based on the loss parameters of each parallel PFC branch.

[0042] The temperatures of m parallel PFC branches are compared, and the n parallel PFC branches with the lowest temperatures are selected for n-way interleaving operation.

[0043] The control method of the interleaved parallel PFC circuit according to the present application selects the interleaving parallel operation mode of the interleaved parallel PFC circuit based on the actual power parameter and the critical parameter of the interleaved parallel PFC circuit, which can select different interleaving parallel operation modes according to the actual circuit parameters, thereby reducing the interleaved parallel PFC circuit and the increased loss caused by the inadaptation of the interleaving parallel operation mode. When the partial interleaving operation mode is selected, the number of interleaving n is selected based on the loss parameters of each parallel PFC branch, which can further reduce the overall loss and improve the overall efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0044] The present application will be further described below with reference to the accompanying drawings and examples, in which:

[0045] Figure 1 is a flow chart of the preferred embodiment of the control method of the interleaved parallel PFC circuit according to the present application;

[0046] Figure 2 is a circuit diagram of the interleaved parallel PFC circuit to which the control method of the interleaved parallel PFC circuit according to the present application is applicable;

[0047] Figures 3A-3C is Figure 2 the waveform diagram of the interleaved parallel PFC circuit shown in FIG. 4;

[0048] Figure 4 is a flow chart of a preferred embodiment of mode selection of the control method of the interleaved parallel PFC circuit of the present application;

[0049] Figure 5 is a flow chart of another preferred embodiment of mode selection of the control method of the interleaved parallel PFC circuit of the present application;

[0050] Figure 6 is a flow chart of a preferred embodiment of module selection of the control method of the interleaved parallel PFC circuit of the present application;

[0051] Figure 7 is a flow chart of another preferred embodiment of module selection of the control method of the interleaved parallel PFC circuit of the present application;

[0052] Figure 8 is a flow chart of another preferred embodiment of the control method of the interleaved parallel PFC circuit of the present application;

[0053] Figure 9 is a schematic diagram of the switching process of the control method of the interleaved parallel PFC circuit of the present application. DETAILED DESCRIPTION

[0054] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0055] Figure 1 is a flow chart of a preferred embodiment of the control method of the interleaved parallel PFC circuit of the present application. The control method of the interleaved parallel PFC circuit of the present application is applicable to any known interleaved parallel PFC circuit. Figure 2 is a circuit diagram of the interleaved parallel PFC circuit to which the control method of the interleaved parallel PFC circuit of the present application is applicable, which includes three parallel PFC branches. Figures 3A-3C is Figure 2 is a waveform diagram of the interleaved parallel PFC circuit shown in Figure 2 When the interleaved parallel PFC circuit shown in is working in a full load working state, for example, three parallel PFC branches are working simultaneously; taking the A phase as an example, the driving signals of the three interleaved switching tubes are mutually different by 120 degrees, and the current waveforms of the inductors La1-La3 and the driving signal waveforms of the lower tubes are as shown in Figure 3AWhen the load decreases to the critical value P1, the switching loss of the parallel PFC branches of the interleaved parallel PFC circuit increases in interleaving, which is greater than the conduction loss caused by interleaving reduction, the interleaved parallel PFC circuit is switched from three-way interleaving mode to two-way interleaving mode, and the angle difference between the driving is switched from 120 degrees to 180 degrees. The current waveform of the inductance La1-La2 and the lower tube driving signal waveform are as shown in Figure 3B When the load continues to decrease below the critical value P2, the efficiency of the single non-interleaved mode of the interleaved parallel PFC circuit will be higher than that of the two-way interleaving mode, and the interleaved parallel PFC circuit is switched to single non-interleaved operation. Similarly, the inductance current waveform and the driving waveform are as shown in Figure 3C

[0056] In the interleaved parallel PFC circuit, those skilled in the art know that the aforementioned critical power P2 and P1 can be obtained by analytical calculation, simulation analysis or experimental test. Therefore, based on this, the present application proposes Figure 1 The control method of the interleaved parallel PFC circuit shown in the figure. It should be noted that the interleaved parallel PFC circuit of the present application is not only applicable to Figure 2 The interleaved parallel PFC circuit shown in the figure is also applicable to any known other interleaved parallel PFC circuit. The interleaved parallel PFC circuit includes m parallel PFC branches, where m can be any value, such as m=3, m=4, etc.

[0057] In step S1, the interleaved parallel operation mode of the interleaved parallel PFC circuit is determined based on the actual power parameters and critical parameters of the interleaved parallel PFC circuit obtained; wherein the interleaved parallel operation mode includes full interleaving operation mode, partial interleaving operation mode and non-interleaving operation mode, the full interleaving operation mode is the operation mode in which all PFC branches participate in interleaving, the partial interleaving operation mode is the operation mode in which only part of the PFC branches participate in interleaving, and the non-interleaving operation mode is the operation mode in which no PFC branch participates in interleaving.

[0058] In one preferred embodiment of the present application, when the actual power parameter is greater than the first critical parameter, the interleaved parallel operation mode of the interleaved parallel PFC circuit is selected as the full interleaving operation mode; when the actual power parameter is less than the second critical parameter, the interleaved parallel operation mode of the interleaved parallel PFC circuit is selected as the non-interleaving operation mode; when the actual power parameter is between the first critical parameter and the second critical parameter, the interleaved parallel operation mode of the interleaved parallel PFC circuit is selected as the partial interleaving operation mode; the first critical parameter is greater than the second critical parameter.

[0059] ​In a preferred embodiment of the present application, the first critical parameter and the second critical parameter can be the circuit power value of the interleaved parallel PFC circuit calculated in real time. In another preferred embodiment of the present application, the first critical parameter and the second critical parameter can be the current reference value calculated by the voltage loop, in which the current value I has a direct corresponding relationship with the power value P according to the formula P = UI, where U represents the voltage value. We take the current reference value Iref as the basis for example to illustrate how to determine the interleaved parallel operation mode that should be entered at present.

[0060] Figure 4 is the flow chart of the mode selection of the control method of the interleaved parallel PFC circuit of the present application, which is illustrated by taking the three-way interleaved parallel PFC circuit shown in Figure 2 as an example. As shown in Figure 4 , first, the current reference value Iref obtained by the circuit voltage control loop circuit, and then determine whether the current reference value Iref is greater than the critical current I1, if yes, select the full-way interleaved operation mode (i.e. three-way interleaved operation mode), otherwise further determine whether the current reference value Iref is greater than the critical current I2, if yes, select the n-way interleaved mode (i.e. two-way interleaved operation mode), otherwise select the non-interleaved operation mode. The critical current I1 is greater than the critical current I2. Among them, the critical current I1, I2 can be calculated according to the relationship between the critical power P1 and P2 and the input voltage U, I1 = P1 / U, I2 = P2 / U. As described above, in the interleaved parallel PFC circuit, the skilled person in the art knows that the aforementioned critical power P2 and P1 can be obtained by analytical calculation, simulation analysis or experimental test.

[0061] We further illustrate the m-way interleaved parallel PFC circuit, i.e. the interleaved parallel PFC circuit includes m parallel PFC branches, and m > 3. At this time, we can set m-1 critical parameters, such as m-1 critical currents, or m-1 critical powers, in which the first critical parameter to the m-1 critical parameter decreases in turn. Then with Figure 4The embodiment shown is similar, when the actual power parameter is greater than the first critical parameter, the interleaved parallel operation mode of the interleaved parallel PFC circuit is selected as the full-path interleaved operation mode; when the actual power parameter is less than the (m-1)th critical parameter, the interleaved parallel operation mode of the interleaved parallel PFC circuit is selected as the non-interleaved operation mode; when the actual power parameter is between the first critical parameter and the (m-1)th critical parameter, the interleaved parallel operation mode of the interleaved parallel PFC circuit is selected as the partial-interleaved operation mode. Similarly, when the actual power parameter is greater than the first critical parameter but greater than the second critical parameter, the interleaved parallel operation mode of the interleaved parallel PFC circuit is selected as the (m-1)th-path interleaved operation mode (i.e. n = m-1 at this time); when the actual power parameter is greater than the second critical parameter but greater than the third critical parameter, the interleaved parallel operation mode of the interleaved parallel PFC circuit is selected as the (m-2)th-path interleaved operation mode (i.e. n = m-2 at this time), and so on.

[0062] In specific practice, in order to reduce the frequent switching of the module caused by interference, we also need to add a hysteresis control scheme. When the interleaved parallel PFC circuit is in the partial-interleaved operation mode and the actual power parameter is greater than the first critical parameter, the interleaved parallel PFC circuit is switched to the full-path interleaved operation mode; when the interleaved parallel PFC circuit is in the non-interleaved operation mode and the actual power parameter is greater than the second critical parameter, the interleaved parallel PFC circuit is switched to the partial-interleaved operation mode; when the interleaved parallel PFC circuit is in the full-path interleaved operation mode and the actual power parameter is less than the third critical parameter, the interleaved parallel PFC circuit is switched to the partial-interleaved operation mode; when the interleaved parallel PFC circuit is in the partial-interleaved operation mode and the actual power parameter is less than the fourth critical parameter, the interleaved parallel PFC circuit is switched to the non-interleaved operation mode; wherein the first critical parameter > the third critical parameter > the second critical parameter > the fourth critical parameter.

[0063] Figure 5 is a flow chart of another preferred embodiment of the mode selection of the control method of the interleaved parallel PFC circuit of the present application, which is explained by taking Figure 2 The three-path interleaved parallel PFC circuit shown is taken as an example for explanation. As shown in Figure 5As shown in FIG. 6, when the interleaved parallel PFC circuit is in the two-way interleaved operation mode and the actual power parameter is greater than a first critical parameter (critical power P2 or critical current I2), the interleaved parallel PFC circuit is switched to the three-way interleaved operation mode; when the interleaved parallel PFC circuit is in the non-interleaved operation mode and the actual power parameter is greater than a second critical parameter (critical power P1 or critical current I1), the interleaved parallel PFC circuit is switched to the two-way interleaved operation mode; when the interleaved parallel PFC circuit is in the three-way interleaved operation mode and the actual power parameter is less than a third critical parameter (critical power P2-ΔP or critical current I2-ΔI), the interleaved parallel PFC circuit is switched to the two-way interleaved operation mode; when the interleaved parallel PFC circuit is in the two-way interleaved operation mode and the actual power parameter is less than a fourth critical parameter (critical power P1-ΔP or critical current I1-ΔI), the interleaved parallel PFC circuit is switched to the non-interleaved operation mode; wherein the first critical parameter (critical power P2 or critical current I2) > the third critical parameter (critical power P2-ΔP or critical current I2-ΔI) > the second critical parameter (critical power P2 or critical current I2) > the fourth critical parameter (critical power P1-ΔP or critical current I1-ΔI).

[0064] In step S2, when the partial interleaved operation mode is selected, the interleaved number n is selected based on the loss parameter of each parallel PFC branch in the m-way parallel PFC branch; wherein m and n are positive integers, m is greater than n, and m is greater than or equal to 3. In some scenarios, the modules running in the system can be intelligently selected according to the temperature, running time and other parameters of the interleaved module, thereby improving the overall reliability of the system.

[0065] In a preferred embodiment of the present application, when the interleaved parallel operation mode of the interleaved parallel PFC circuit is the partial interleaved operation mode, the temperatures of the m-way parallel PFC branches are compared, and the n parallel PFC branches with the lowest temperatures are selected for n-way interleaved operation. Figure 6 FIG. 7 is a flowchart of a preferred embodiment of module selection of the control method of the interleaved parallel PFC circuit of the present application; which is described by taking the three-way interleaved parallel PFC circuit shown in FIG. 6 as an example. Figure 2 As shown in FIG. 6, when the interleaved parallel PFC circuit is in the three-way interleaved operation mode, it is determined whether the actual power parameter is less than a third critical parameter (critical power P2-ΔP or critical current I2-ΔI), if yes, the temperatures of the three-way PFC branches M1, M2 and M3 are compared. Here, comparing the temperatures of the three-way PFC branches M1, M2 and M3 means comparing the temperatures of the power tubes thereof, and the two PFC branches with the lowest temperatures are selected to enter the two-way interleaved operation mode. As shown in FIG. 6, when the actual power parameter is less than the third critical parameter (critical power P2-ΔP or critical current I2-ΔI), the temperatures of the three-way PFC branches M1, M2 and M3 are compared, and the two PFC branches with the lowest temperatures are selected to enter the two-way interleaved operation mode. Figure 6 As shown in FIG. 6, when the interleaved parallel PFC circuit is in the three-way interleaved operation mode, it is determined whether the actual power parameter is less than a third critical parameter (critical power P2-ΔP or critical current I2-ΔI), if yes, the temperatures of the three-way PFC branches M1, M2 and M3 are compared. Here, comparing the temperatures of the three-way PFC branches M1, M2 and M3 means comparing the temperatures of the power tubes thereof, and the two PFC branches with the lowest temperatures are selected to enter the two-way interleaved operation mode. As shown in FIG. 6, when the actual power parameter is less than the third critical parameter (critical power P2-ΔP or critical current I2-ΔI), the temperatures of the three-way PFC branches M1, M2 and M3 are compared, and the two PFC branches with the lowest temperatures are selected to enter the two-way interleaved operation mode.Figure 6 As shown, when the PFC branch M1 has the highest temperature, the PFC branches M2 and M3 are selected to enter the two-way interleaving operation mode; when the PFC branch M2 has the highest temperature, the PFC branches M1 and M3 are selected to enter the two-way interleaving operation mode; when the PFC branch M3 has the highest temperature, the PFC branches M2 and M1 are selected to enter the two-way interleaving operation mode.

[0066] In further preferred embodiments of the present application, the selection of the PFC branches can be made according to efficiency and reliability. Figure 7 is a flow chart of another preferred embodiment of the module selection of the control method of the interleaving parallel PFC circuit of the present application. As shown, Figure 7 In step S1, the loss parameter of each PFC branch is calculated, and the current parameter is used to refine the loss parameter of the PFC branch.

[0067] Preferably, the loss parameter of each parallel PFC branch is calculated based on the following formula:

[0068] P loss_per = P MOS_sw + P MOS_cond + P L_Cu + P L_Fe

[0069] Wherein, P MOS_sw represents the switching loss of the switching tube of the parallel PFC branch, P MOS_cond represents the conduction loss of the switching tube of the parallel PFC branch, P L_Cu represents the line loss of the inductor of the parallel PFC branch, P L_Fe represents the core loss of the inductor of the parallel PFC branch;

[0070] The current parameter is used to refine the loss parameter of each parallel PFC branch as follows:

[0071]

[0072] Wherein, C ds represents the equivalent parallel capacitance of the switching tube of the parallel PFC branch, f represents the switching frequency of the parallel PFC branch; V ds represents the drain-source voltage of the switching tube of the parallel PFC branch; I rms represents the current effective value of the parallel PFC branch, R ds_on represents the conduction resistance of the switching tube of the parallel PFC branch, R L_DC represents the DC impedance of the inductor of the parallel PFC branch, R L_AC represents the AC impedance of the inductor of the parallel PFC branch, I AC_rmsrepresents the effective value of AC ripple of the inductance of the parallel PFC branch; K, a, b represent the inductance material constant of the parallel PFC branch, V e represents the volume of the inductance of the parallel PFC branch; pk represents the peak value of the current flowing through the parallel PFC branch, N represents the number of winding turns of the inductance of the parallel PFC branch, A e represents the magnetic circuit cross-sectional area value of the inductance of the parallel PFC branch.

[0073] In step S2, based on the loss parameter of each parallel PFC branch, the total loss parameter of the interleaved parallel PFC circuit is calculated and minimized to calculate the interleaving number n. Preferably, define i n as the current of each parallel PFC branch when n-parallel interleaving, define P loss_per_n = f(i n ) as the loss parameter of each parallel PFC branch when n-parallel interleaving, wherein f() represents the relationship function between the current i n and the loss parameter P loss_per_n ;

[0074] The following standard formula is solved to calculate the total loss parameter of the interleaved parallel PFC circuit, and the total loss parameter is minimized to calculate the interleaving number n:

[0075] Minimization target:

[0076] Constraint condition: 1≤n≤m.

[0077] The principle of the selection step of the interleaving number n is further described as follows. For a PFC circuit, its loss mainly comes from the loss of the inductor and the loss of the power tube. When multiple parallel, the loss P loss_per of each branch can be expressed as:

[0078] P loss_per = P MOS_sw + P MOS_cond + P L_Cu + P L_Fe

[0079] Wherein, P MOS_sw is the switching loss of the switch tube, P MOS_cond is the conduction loss of the switch tube, P L_Cu is the wire loss (copper loss) of the inductor, and P L_Fe is the core loss (iron loss) of the inductor.

[0080] Specifically, the above-mentioned each part of the loss can be refined into an expression related to the current value in the circuit:

[0081]

[0082] where C ds is the equivalent parallel capacitance of the switch, f is the switching frequency, V ds is the drain-source voltage of the switch of the parallel PFC branch. is the switching loss when the system works in DCM / CrM state. I rms is the current effective value, R ds_on is the on-resistance of the switch, R L_DC is the DC impedance of the inductor, R L_Ac is the AC impedance of the inductor, I AC_rms is the AC ripple effective value of the inductor. K, a, b are the material constants of the inductor, f is the switching frequency of the system, B max is the maximum inductor flux, V e is the volume of the inductor.

[0083] The inductor flux can be further expressed as the expression of the current:

[0084]

[0085] where I pk is the current peak value, N is the number of turns of the inductor, A e is the inductor magnetic circuit cross-sectional area value.

[0086] In the PFC circuit, the addition and subtraction of the parallel PFC branch will affect the size of the circuit current, and we define i n as the current when n parallel branches are connected, P loss_per_n = f(i n ) is the loss of each branch when n parallel branches are connected. At this time, the number of interleaved branches can be abstracted as an optimization problem of optimizing system efficiency, and the standard formula is:

[0087] Minimization target:

[0088] Constraint condition: 1 ≤ n ≤ n max

[0089] The above optimization problem can be solved by using optimization solving tools by bringing in device parameters (physical parameters of switches and inductors) and current variables related to the number of interleaved branches n obtained by calculation or simulation, to obtain the optimal number of interleaved branches n. In this regard, those skilled in the art know how to perform the foregoing solving work, which will not be repeated here.

[0090] After obtaining the optimal number of interleaved branches n by the efficiency optimization method, we further design the optimal interleaved module selection method from the reliability point of view, and allocate the optimal number of interleaved branches n. Figure 8is a flow chart of another preferred embodiment of the control method of the interleaved parallel PFC circuit of the present application. Figure 8 The embodiment shown in Figure 1 On the basis of the embodiment shown, step S3 is added, selecting n parallel PFC branches for interleaved parallel in the interleaved parallel PFC circuit based on operating parameters; the operating parameters include time parameters or temperature parameters.

[0091] The selection of the number of interleaved paths mainly affects the inductance and the switching element. The reliability of the inductance is relatively high, while the switching element is relatively easy to damage. According to the research of material science, the damage mechanism of the switching element is mainly caused by long-term stress (including electrical and thermal stress) and fatigue accumulation during switching. Therefore, the optimization of reliability starts from these two mechanisms, and two strategies are designed, i.e. a strategy based on time parameters or a strategy based on temperature parameters.

[0092] In the strategy based on time parameters, the running time of each parallel PFC branch is recorded in real time; when the difference between the running time of the parallel PFC branch with the longest running time and the running time of the parallel PFC branch with the shortest running time is greater than a first set threshold, the parallel PFC branch with the longest running time is closed and the parallel PFC branch with the shortest running time is opened.

[0093] According to the Coffin-Manson failure model, the switching action of the switching element will cause the fluctuation of the junction temperature, and multiple temperature cycles will cause the internal solder joints of the switching element to gradually age and fail. Therefore, in the strategy based on time parameters, the running time of each interleaved PFC branch is counted and recorded as t1, t2,..., tn. A maximum running time difference threshold Δt max is set, and when the time difference between the running time of the interleaved PFC branch with the longest running time and the running time of the interleaved PFC branch with the shortest running time in the interleaved parallel PFC circuit is greater than the maximum running time threshold, the module switching is performed. The conversion into pseudo code is as follows:

[0094] If: max(t i )-min(t i )≥Δt max

[0095] Then: the interleaved PFC branch with the longest total running time is closed, and the interleaved PFC branch with the shortest total running time is enabled.

[0096] Here, the skilled person in the art can select suitable parallel PFC branches according to the teachings of the present application and the conventional detection methods and calculation formulas in the art.

[0097] In the temperature-based strategy, the operating temperature of each parallel PFC branch is recorded in real time. When the difference between the operating temperature of the parallel PFC branch with the highest operating temperature and the operating temperature of the parallel PFC branch with the lowest operating temperature is greater than a second set threshold, the parallel PFC branch with the highest operating temperature is shut down and the parallel PFC branch with the lowest operating temperature is turned on.

[0098] According to the Arrhenius equation, the reaction rate of a material is positively correlated with temperature. Therefore, increased temperature leads to accelerated aging of switching devices, primarily manifested as gate oxide layer aging and breakdown. Thus, during multi-channel interleaved operation, the operating temperature of each parallel PFC branch is monitored and recorded as T1, T2, ..., Tn. When the temperature difference between the highest and lowest temperature PFC branch exceeds the maximum temperature threshold ΔT... max Then, the switching between running PFC branches is performed, and the control logic is as follows:

[0099] If: max(T) i )-min(T i )≥ΔT max && Running in multi-path interleaving conditions

[0100] Then: the interleaved PFC branch with the highest temperature is turned off, and the interleaved PFC branch with the lowest temperature is turned on.

[0101] Here, those skilled in the art, based on the teachings of this invention and conventional detection methods and calculation formulas in the field, can select a suitable parallel PFC branch.

[0102] In addition, to ensure the transient reliability of the staggered switching operation strategy, we will first enter the full module operation mode when switching, and then switch out the staggered path that needs to rest. Figure 9 This is a schematic diagram illustrating the switching process of the control method for the interleaved parallel PFC circuit of the present invention. For example... Figure 9 As shown, when it is necessary to switch from the rest mode of the first parallel PFC branch to the rest mode of the second parallel PFC branch, we first enable all three parallel PFC branches and run them stably before shutting down the second parallel PFC branch. This ensures that the current stress of each branch will not be abnormal during the transient process of connecting the first and second parallel PFC branches. The same applies to the switching between other branches, which will not be elaborated here.

[0103] The control method of the staggered parallel PFC circuit of the present application can select different staggered parallel operation modes according to actual circuit parameters by selecting the staggered parallel operation mode of the staggered parallel PFC circuit based on actual power parameters and critical parameters of the staggered parallel PFC circuit, thereby reducing the staggered parallel PFC circuit, and thus reducing the increase in loss caused by the inadaptation of the staggered parallel operation mode; and when the partial staggered operation mode is selected, the staggered number n is selected based on the loss parameters of each parallel PFC branch, which can further reduce the overall loss and improve the overall efficiency.

[0104] The present application is directed to a staggered parallel PFC module operating in DCM / CrM / TCM mode, and proposes a method of intelligently enabling the module operating in the system according to power or current as a reference, so as to achieve the purpose of improving system efficiency and reliability. The method includes the definition of power tube driving mode of the system in different staggered operation processes, the control logic of the system selecting different parallel PFC branch operation, the anti-interference method of the system switching between different states, and the optimization of staggered module switching logic design for reliability.

[0105] Although the present application is described by specific embodiments, those skilled in the art should understand that various modifications and equivalent substitutions can be made to the present application without departing from the scope of the present application. In addition, various modifications can be made to the present application for specific situations or materials without departing from the scope of the present application. Therefore, the present application is not limited to the disclosed specific embodiments, but should include all embodiments falling within the scope of the claims of the present application.

[0106] The above is only the preferred embodiment of the present application, and is not intended to limit the present application. Any modification, equivalent substitution and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A control method for an interleaved parallel PFC circuit, wherein the interleaved parallel PFC circuit comprises m parallel PFC branches, characterized in that, The control method includes: Based on the actual power parameters and critical parameters of the interleaved parallel PFC circuit, the interleaved parallel operation mode of the interleaved parallel PFC circuit is determined; wherein, the interleaved parallel operation mode includes a full-path interleaved operation mode, a partial-path interleaved operation mode, and a non-interleaved operation mode, the full-path interleaved operation mode is the operation mode in which all PFC branches participate in interleaving, the partial-path interleaved operation mode is the operation mode in which only some PFC branches participate in interleaving, and the non-interleaved operation mode is the operation mode in which no PFC branches participate in interleaving; When the interleaved parallel operation mode is the partially interleaved operation mode, the number of interleaving n is selected based on the loss parameters of each parallel PFC branch in the m parallel PFC branches. Where m and n are positive integers, m is greater than n, and m is greater than or equal to 3.

2. The control method for the interleaved parallel PFC circuit according to claim 1, characterized in that, The selection of the interleaving number n based on the loss parameters of each of the m parallel PFC branches includes: For each PFC branch, calculate the loss parameters of the PFC branch, and refine the loss parameters of the PFC branch using current parameters. Based on the loss parameters of each parallel PFC branch, the total loss parameters of the interleaved parallel PFC circuit are calculated and the total loss parameters are minimized to calculate the number of interleavings n.

3. The control method for the interleaved parallel PFC circuit according to claim 2, characterized in that, For each PFC branch, the loss parameters of that PFC branch are calculated, and the loss parameters of that PFC branch are refined using current parameters, including: The loss parameters for each parallel PFC branch are calculated using the following formula: P loss_per =P MOS_sw +P MOS_cond +P L_Cu +P L_Fe Among them, P MOS_sw P represents the switching loss of the switching transistor in the parallel PFC branch. MOS_cond P represents the conduction loss of the switching transistor in the parallel PFC branch. L_Cu P represents the line loss of the inductor in the parallel PFC branch. L_Fe This represents the core loss of the inductor in the parallel PFC branch; The loss parameters of each parallel PFC branch are refined using current parameters as follows: Among them, C ds V represents the equivalent parallel capacitance of the switching transistor in the parallel PFC branch, and f represents the switching frequency of the parallel PFC branch; ds The drain-source voltage of the switching transistor in the parallel PFC branch; I rms R represents the effective value of the current in the parallel PFC branch. ds_on R represents the on-resistance of the switching transistor in the parallel PFC branch. L_DC R represents the DC impedance of the inductor in the parallel PFC branch. L_AC I represents the AC inductance of the parallel PFC branch. AC_rms The RMS value of the AC ripple of the inductor in the parallel PFC branch is represented by K, a, and b; these represent the inductor material constants of the parallel PFC branch; V e Indicates the inductance volume of the parallel PFC branch; I pk The value represents the peak current flowing through the parallel PFC branch, where N represents the number of inductor coils in the parallel PFC branch, and A represents the current peak value. e This represents the magnetic circuit cross-sectional area of ​​the inductor in the parallel PFC branch.

4. The control method for the interleaved parallel PFC circuit according to claim 3, characterized in that, The calculation of the total loss parameter of the interleaved parallel PFC circuit based on the loss parameter of each parallel PFC branch, and minimizing the total loss parameter to calculate the interleaving number n, includes: Define i n Let P be the current in each parallel PFC branch when n parallel branches are interleaved. loss_per_n =f(i n Let f(i) represent the loss parameters of each parallel PFC branch when n parallel branches are interleaved, where f(i) represents the current i. n With loss parameter P loss_per_n Relationship functions; Solve the following standard formula to calculate the total loss parameter of the interleaved parallel PFC circuit, and minimize the total loss parameter to calculate the number of interleavings n: Minimize objective: Constraints: 1 ≤ n ≤ m.

5. The control method for the interleaved parallel PFC circuit according to any one of claims 1 to 4, characterized in that, Further includes: Based on the operating parameters, n parallel PFC branches are selected in the interleaved parallel PFC circuit for interleaved parallel connection; The operating parameters include time parameters or temperature parameters.

6. The control method for the interleaved parallel PFC circuit according to claim 5, characterized in that, When the operating parameters include time parameters, the step of selecting n parallel PFC branches in the interleaved parallel PFC circuit based on the operating parameters for interleaved parallel connection includes: Record the running time of each parallel PFC branch in real time; When the difference between the running time of the longest parallel PFC branch and the running time of the shortest parallel PFC branch exceeds a first set threshold, the longest parallel PFC branch is shut down and the shortest parallel PFC branch is turned on.

7. The control method for the interleaved parallel PFC circuit according to claim 5, characterized in that, When the operating parameters include temperature parameters, the step of selecting n parallel PFC branches in the interleaved parallel PFC circuit based on the operating parameters for interleaved parallel connection includes: Record the operating temperature of each parallel PFC branch in real time; When the difference between the operating temperature of the parallel PFC branch with the highest operating temperature and the operating temperature of the parallel PFC branch with the lowest operating temperature is greater than a second set threshold, the parallel PFC branch with the highest operating temperature is shut down and the parallel PFC branch with the lowest operating temperature is turned on.

8. The control method for the interleaved parallel PFC circuit according to claim 5, characterized in that, The selection of the interleaved parallel operation mode of the interleaved parallel PFC circuit based on the actual power parameters and critical parameters of the interleaved parallel PFC circuit includes: When the actual power parameter is greater than the first critical parameter, the interleaved parallel operation mode of the interleaved parallel PFC circuit is selected as the full-path interleaved operation mode. When the actual power parameter is less than the second critical parameter, the interleaved parallel operation mode of the interleaved parallel PFC circuit is selected as the non-interleaved operation mode. When the actual power parameter is between the first critical parameter and the second critical parameter, the interleaved parallel operation mode of the interleaved parallel PFC circuit is selected as the partial interleaved operation mode. The first critical parameter is greater than the second critical parameter.

9. The control method for the interleaved parallel PFC circuit according to claim 5, characterized in that, The selection of the interleaved parallel operation mode of the interleaved parallel PFC circuit based on the actual power parameters and critical parameters of the interleaved parallel PFC circuit includes: When the interleaved parallel PFC circuit is in the partially interleaved operation mode and the actual power parameter is greater than the first critical parameter, the interleaved parallel PFC circuit is switched to the full-path interleaved operation mode. When the interleaved parallel PFC circuit is in the non-interleaved operation mode and the actual power parameter is greater than the second critical parameter, the interleaved parallel PFC circuit is switched to the partially interleaved operation mode. When the interleaved parallel PFC circuit is in the full-path interleaved operation mode and the actual power parameter is less than the third critical parameter, the interleaved parallel PFC circuit is switched to the partial interleaved operation mode. When the interleaved parallel PFC circuit is in the partially interleaved operation mode and the actual power parameter is less than the fourth critical parameter, the interleaved parallel PFC circuit is switched to the non-interleaved operation mode. Wherein the first critical parameter > the third critical parameter > the second critical parameter > the fourth critical parameter.

10. The control method for the interleaved parallel PFC circuit according to claim 1, characterized in that, When the partially interleaved operation mode is selected, the selection of the interleaving number n based on the loss parameters of each parallel PFC branch further includes: Compare the temperatures of m parallel PFC branches, and select the n parallel PFC branches with the lowest temperatures for n-way staggered operation.

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