Output overcurrent circuit with adjustable protection time

Abstract

The invention discloses an output overcurrent circuit with adjustable protection time, which belongs to the technical field of power supply control and comprises a diode D1, a transformer auxiliary winding T1B, an NMOS (N-channel Metal Oxide Semiconductor) tube Q3, an NMOS tube Q4 and an NMOS tube Q5, the anode of the diode D1 is connected with the starting power supply Vstart; the anode of the diode D2 is connected with one end of an auxiliary winding T1B of the transformer; the drain electrode of the NMOS tube Q3 is connected with the base electrode of the triode Q1. The grid electrode of the NMOS tube Q4 is connected with one end of a resistor R9 and the anode of a voltage-regulator tube ZD1 at the same time, and the grid electrode of the NMOS tube Q5 is connected with one end of a resistor R10 and the anode of a voltage-regulator tube ZD2 at the same time. According to the invention, the detection voltage value and the hiccup time of the power supply can be adjusted, the starting overpower time can also be adjusted, the two-stage protection of current limiting and hiccup can be realized especially in cooperation with a secondary output constant current circuit, and the practicability and flexibility of the circuit are greatly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to power supply control technical field, specifically to an output over-current circuit with adjustable protection time. BACKGROUND

[0002] The output over-current protection circuit is a rigid requirement and a core component for guaranteeing the safe and reliable operation of the switching power supply, protecting the load device and meeting the safety regulations. There are many ways to realize over-current protection, and the common ones are to realize over-current protection by triggering the protection function of the main control chip. One of the protection modes is the hiccup mode, that is, the output voltage drops to zero, and restarts after a fixed time in the chip; the other is the over-power protection mode, that is, when the over-current point is reached, the chip protection function is triggered, the output voltage starts to drop, but the drive does not shut down, the current continues to increase, and the voltage continues to drop. The two protection modes have their own advantages and disadvantages. The former uses the protection function of the chip, which is sensitive and can quickly turn off the drive, greatly reducing the stress of semiconductor devices, but for some inductive and capacitive loads at the output end, the over-current protection of the chip is triggered during the output voltage rising process after starting, which will cause the power supply to be in repeated hiccup protection and unable to start normally. The protection mechanism of the latter has strong inductive and capacitive load carrying capacity, and is highly adaptable to loads in the industrial control field, which is the more mainstream protection mode in this field. However, as the load increases, although the output voltage decreases, the output current also increases with the load, which will cause high current stress of semiconductor and magnetic devices, and long-term use will cause damage to the switching power supply. SUMMARY

[0003] In view of the problems existing in the prior art, the purpose of the present application is to provide an output over-current circuit with adjustable protection time to solve the problems in the background art of the protection circuit.

[0004] To achieve the above purpose, the present application provides the following technical scheme: An output over-current circuit with adjustable protection time, comprising a diode D1, a diode D2, a diode D3, a resistor R1, a transformer auxiliary winding T1B, a triode Q2, an NMOS tube Q3, a triode Q1, an NMOS tube Q4, a stabilizing tube ZD1, a stabilizing tube ZD2 and an NMOS tube Q5. The anode of the diode D1 is connected with a starting power V_start; the cathode of the diode D1 is connected with the cathode of the diode D3, the anode of the diode D3 is connected with one end of the resistor R1, the other end of the resistor R1 is connected with the cathode of the diode D2, the anode of the diode D2 is connected with one end of the transformer auxiliary winding T1B, and the other end of the transformer auxiliary winding T1B is grounded. The cathode of diode D1 and one end of resistor R3 are connected, the other end of resistor R3 is connected with the base of triode Q1 and one end of resistor R4, the other end of resistor R4 is connected with the drain of NMOS Q4; The emitter of triode Q1 is connected with the cathode of diode D1; The collector of triode Q1 is connected with one end of resistor R5 and one end of capacitor C3, the other end of capacitor C3 is grounded; The other end of resistor R5 is connected with the gate of NMOS Q3 and one end of resistor R7, the other end of resistor R7 is grounded; The drain of NMOS Q3 is connected with the base of triode Q1 and one end of resistor R2, the other end of resistor R2 is connected with the cathode of diode D1; The collector of triode Q1 is connected with the cathode of diode D1, the emitter of triode Q1 is connected with power supply VCC_IC; The gate of NMOS Q4 is connected with one end of resistor R9 and the anode of ZD1, the other end of resistor R9 is grounded; The cathode of ZD1 is connected with one end of capacitor C4, the other end of capacitor C4 is grounded; The cathode of ZD1 is connected with the drain of NMOS Q5, the source of NMOS Q5 is grounded; The gate of NMOS Q5 is connected with one end of resistor R10 and the anode of ZD2, the other end of resistor R10 is grounded; The cathode of ZD2 is connected with the anode of diode D3; The cathode of ZD1 is connected with the anode of diode D4, the cathode of diode D4 is connected with power supply VCC_IC.

[0005] As a further scheme of the application, the two ends of capacitor C1 are connected in parallel with resistor R11.

[0006] As a further scheme of the application, the source of NMOS Q3 is grounded.

[0007] As a further scheme of the application, the drain of NMOS Q4 is grounded.

[0008] As a further scheme of the application, the anode of diode D3 is connected with the anode of capacitor C1, the cathode of capacitor C1 is grounded.

[0009] As a further scheme of the application, the cathode of diode D1 is connected with the anode of capacitor C2, the cathode of capacitor C2 is grounded.

[0010] As a further scheme of the present application, one end of the emitter of the triode Q1 is connected with the resistor R6, and the other end of the resistor R6 is grounded.

[0011] As a further scheme of the present application, the diode D4 is provided with the resistor R8 in parallel.

[0012] As a further scheme of the present application, the capacitor C1 and the capacitor C2 are both electrolytic capacitors.

[0013] As a further scheme of the present application, the triode Q1 is an NPN triode, and the triode Q2 is a PNP triode.

[0014] Compared with the prior art, the present application has the following beneficial effects: In the over-power protection mode, the present application uses the primary auxiliary winding voltage coupled with the secondary output winding to perform the hiccup protection after the output voltage drops to the set value, and can adjust the detection voltage value and the power hiccup time, and can also adjust the start-up over-power time, especially in combination with the secondary output constant current circuit to realize the two-stage protection of current limiting and hiccup, thereby greatly improving the practicability and flexibility of the circuit. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 It is a schematic diagram of an output over-current circuit with adjustable protection time. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0017] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "provided with", "connected with", and "connected" should be understood in a broad sense; for example, it can be fixed connection, or detachable connection, or integrally connected, or mechanical connection, or electrical connection, or direct connection, or indirect connection through an intermediate medium, or internal communication of two elements. Those skilled in the art can understand the specific meaning of the above terms in the present application according to the specific circumstances.

[0018] The application provides an output overcurrent protection circuit with adjustable protection time.

[0019] Please refer to Figure 1 The application provides an output overcurrent protection circuit with adjustable protection time, which comprises a diode D1, a diode D2, a diode D3, a resistor R1, a transformer auxiliary winding T1B, a capacitor C1, a resistor R11, a capacitor C2, a resistor R3, a resistor R4, a triode Q2, a resistor R5, a resistor R4, a capacitor C3, a resistor R7, an NMOS tube Q3, a resistor R2, a triode Q1, a resistor R6, an NMOS tube Q4, a voltage stabilizing tube ZD1, a voltage stabilizing tube ZD2, a resistor R8, a resistor R9, a capacitor C4, an NMOS tube Q5 and a resistor R10. The anode of the diode D1 is connected with a starting power V_start; the cathode of the diode D1 is connected with the cathode of the diode D3, the anode of the diode D3 is connected with one end of the resistor R1, the other end of the resistor R1 is connected with the cathode of the diode D2, the anode of the diode D2 is connected with one end of the transformer auxiliary winding T1B, and the other end of the transformer auxiliary winding T1B is grounded. The anode of the diode D3 is connected with the anode of the capacitor C1, and the cathode of the capacitor C1 is grounded. The capacitor C1 is provided with the resistor R11 in parallel at both ends. The cathode of the diode D1 is connected with the anode of the capacitor C2, and the cathode of the capacitor C2 is grounded. The cathode of the diode D1 is connected with one end of the resistor R3, the other end of the resistor R3 is connected with the base of the triode Q1 and one end of the resistor R4, and the other end of the resistor R4 is connected with the drain of the NMOS tube Q4. The emitter of the triode Q1 is connected with the cathode of the diode D1. The collector of the triode Q1 is connected with one end of the resistor R5 and one end of the capacitor C3, and the other end of the capacitor C3 is grounded. The other end of the resistor R5 is connected with the gate of the NMOS tube Q3 and one end of the resistor R7, and the other end of the resistor R7 is grounded. The source of the NMOS tube Q3 is grounded. The drain of the NMOS tube Q3 is connected with the base of the triode Q1 and one end of the resistor R2, and the other end of the resistor R2 is connected with the cathode of the diode D1. The collector of the triode Q1 is connected with the cathode of the diode D1; the emitter of the triode Q1 is connected with the power supply VCC_IC; The emitter of the triode Q1 is connected with one end of the resistor R6, and the other end of the resistor R6 is grounded. The gate of the NMOS Q4 is connected with one end of the resistor R9 and the anode of the Zener ZD1, and the other end of the resistor R9 is grounded. The drain of the NMOS Q4 is grounded. The cathode of the Zener ZD1 is connected with one end of the capacitor C4, and the other end of the capacitor C4 is grounded. The cathode of the Zener ZD1 is connected with the drain of the NMOS Q5; the source of the NMOS Q5 is grounded. The gate of the NMOS Q5 is connected with one end of the resistor R10 and the anode of the Zener ZD2, and the other end of the resistor R10 is grounded. The cathode of the Zener ZD2 is connected with the anode of the diode D3. The cathode of the Zener ZD1 is connected with the anode of the diode D4; the cathode of the diode D4 is connected with the power supply VCC_IC. The resistor R8 is connected in parallel with the diode D4.

[0020] The capacitor C1 is an electrolytic capacitor.

[0021] The capacitor C2 is an electrolytic capacitor.

[0022] The triode Q1 is an NPN triode, and the triode Q2 is a PNP triode.

[0023] The V_start of the application is a power supply starting voltage, after power-up, the V_start passes through the diode D1 to the capacitor C2, at this time, the NMOS tube Q4 has no driving voltage and is in the closed state, at the same time, the PNP transistor Q2 is in the closed state because it has not reached the open condition, the NMOS tube Q3 has no driving voltage and is in the closed state, the NPN transistor Q1 is turned on, the starting voltage passes through the NPN transistor Q1 to the VCC_IC to supply power to the chip, when the output voltage of the power supply rises, because the transformer auxiliary winding T1B is coupled with the secondary winding, the T1B winding passes through the diode D2 and the resistor R1 to the capacitor C1 to form a rectifier filter circuit, with the rise of the output voltage, the voltage of the capacitor C1 rises in the ratio of turns, when the voltage of C1 reaches the sum of the breakdown voltage of the ZD2 voltage stabilizing tube and the turn-on threshold voltage of the NMOS tube Q5, the Q5 is turned on, the cathode voltage of the ZD1 voltage stabilizing tube is almost close to zero and will not break down and turn on, the NMOS tube Q4 is in the closed state, the NPN transistor Q1 is continuously turned on, the V_start can supply power to the VCC_IC all the time, and the power supply is in the normal working state. When overcurrent occurs in the output, the output voltage drops, and the voltage of the capacitor C1 also drops in the same proportion, when the voltage of C1 drops below the sum of the breakdown voltage of the ZD2 voltage stabilizing tube and the turn-on threshold voltage of the NMOS tube Q5 with the drop of the output voltage, the NMOS tube Q5 is turned off, at the same time, the VCC_IC charges the capacitor C4 through the resistor R8, when the voltage of the capacitor C4 reaches the sum of the breakdown voltage of the ZD1 voltage stabilizing tube and the turn-on threshold voltage of the NMOS tube Q4, the NMOS tube Q4 is turned on, and then the PNP transistor Q2 is turned on, the capacitor C3 is charged instantaneously, the voltage of the capacitor C3 is charged to a high voltage value instantaneously, at the same time, when the voltage of C3 exceeds the turn-on threshold voltage of the NMOS tube Q3 through the voltage division of the resistor R5 and the resistor R7, the Q3 is turned on, the base of the transistor Q1 is pulled low and turned off, the chip supply is cut off and the output is turned off, at the same time, the capacitor C1 is discharged through the resistor R11, and the capacitor C3 is discharged through the resistor R5 and the resistor R7, when the voltage of C3 is lower than the turn-on threshold voltage of the NMOS tube Q3 through the voltage division of the resistor R5 and the resistor R7, the Q3 is turned off, the Q1 is turned on again, and the chip is continuously supplied with power, so as to realize the hiccup protection. On the other hand, when the output voltage rises in the process of starting the power supply, overcurrent or short circuit occurs in the secondary, the voltage of the capacitor C1 is not enough to break down and turn on the ZD2 voltage stabilizing tube, the VCC_IC charges the capacitor C4 through the resistor R8 to reach the state of turning on the NMOS tube Q4, at this time, the same working mechanism as described before is passed, the Q2 is turned on→the Q3 is turned on→the Q1 is turned off, the capacitor C4 is discharged rapidly through the diode D4 to the resistor and the chip to reset, and then the C3 capacitor is discharged→the Q3 is turned off→the Q1 is turned on, so as to realize the hiccup protection. As described above, the NMOS tubes Q3 and Q4 have been selected, the time of starting the work of the chip is determined by the resistor R8, the capacitor C4 and the ZD1 voltage stabilizing value, and can be flexibly adjusted. The chip shutdown time is determined by the resistor R5, the resistor R7 and the capacitor C3, and can also be flexibly adjusted.

[0024] The application provides a time-adjustable output overcurrent circuit implementation method, in the over-power type protection mode, the voltage of the primary auxiliary winding coupled with the secondary output winding is detected, the output voltage can be reduced to the set value, the hiccup protection can be performed, the detection voltage value and the power hiccup time can be adjusted, the starting over-power time can be adjusted, especially in cooperation with the secondary output constant current circuit, the two-stage protection of current limiting and hiccup can be realized, the practicability and flexibility of the circuit are greatly improved.

[0025] It is apparent to a person skilled in the art that the present application is not limited to the details of the foregoing exemplary embodiments, and that the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered in all respects as illustrative and not restrictive, the scope of the present application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference signs in the claims should not be construed as limiting the claims to the figures in which the reference signs are used.

[0026] Furthermore, it should be understood that, although the present specification is described in terms of embodiments, not every embodiment exhibits every characteristic or option described in the specification. In addition, it should be understood that, although the specification has been described in terms of embodiments, not every embodiment only contains one independent technical solution, and the specification is described in this way only for the sake of clarity, and a person skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be properly combined to form other embodiments that can be understood by a person skilled in the art.

Claims

1. An output overcurrent circuit with adjustable protection time, characterized in that, The diode D1, the diode D2, the diode D3, the transformer auxiliary winding T1B, the triode Q2, the NMOS Q3, the triode Q1, the NMOS Q4, the Zener ZD1, the Zener ZD2 and the NMOS Q5 are arranged in series. The anode of the diode D1 is connected with the starting power supply V_start; the cathode of the diode D1 is connected with the cathode of the diode D3, the anode of the diode D3 is connected with one end of the resistor R1, the other end of the resistor R1 is connected with the cathode of the diode D2, the anode of the diode D2 is connected with one end of the transformer auxiliary winding T1B, the other end of the transformer auxiliary winding T1B is grounded. The cathode of the diode D1 is connected with one end of the resistor R3, the other end of the resistor R3 is connected with the base of the triode Q1 and one end of the resistor R4, the other end of the resistor R4 is connected with the drain of the NMOS Q4. The emitter of the triode Q1 is connected with the cathode of the diode D1. The collector of the triode Q1 is connected with one end of the resistor R5 and one end of the capacitor C3, the other end of the capacitor C3 is grounded. The other end of the resistor R5 is connected with the gate of the NMOS Q3 and one end of the resistor R7, the other end of the resistor R7 is grounded. The drain of the NMOS Q3 is connected with the base of the triode Q1 and one end of the resistor R2, the other end of the resistor R2 is connected with the cathode of the diode D1. The collector of the triode Q1 is connected with the cathode of the diode D1, the emitter of the triode Q1 is connected with the power supply VCC_IC. The gate of the NMOS Q4 is connected with one end of the resistor R9 and the anode of the Zener ZD1, the other end of the resistor R9 is grounded. The cathode of the Zener ZD1 is connected with one end of the capacitor C4, the other end of the capacitor C4 is grounded. The cathode of the Zener ZD1 is connected with the drain of the NMOS Q5, the source of the NMOS Q5 is grounded. The gate of the NMOS Q5 is connected with one end of the resistor R10 and the anode of the Zener ZD2, the other end of the resistor R10 is grounded. The cathode of the Zener ZD2 is connected with the anode of the diode D3. The cathode of the Zener ZD1 is connected with the anode of the diode D4, the cathode of the diode D4 is connected with the power supply VCC_IC.

2. The output overcurrent protection circuit with adjustable time according to claim 1, wherein, The capacitor C1 is connected with the resistor R11 in parallel.

3. The output overcurrent protection circuit with adjustable time according to claim 2, wherein, The source of the NMOS Q3 is grounded.

4. The output overcurrent protection circuit with adjustable time according to claim 3, wherein, The drain of the NMOS Q4 is grounded.

5. The output overcurrent protection circuit with adjustable time according to claim 4, wherein, The anode of the diode D3 is connected with the anode of the capacitor C1, the cathode of the capacitor C1 is grounded.

6. The output overcurrent protection circuit with adjustable time according to claim 5, wherein, The cathode of the diode D1 is connected with the anode of the capacitor C2, the cathode of the capacitor C2 is grounded.

7. The output overcurrent protection circuit with adjustable time according to claim 6, wherein, The emitter of the triode Q1 is connected with one end of the resistor R6, the other end of the resistor R6 is grounded.

8. The output overcurrent protection circuit with adjustable time according to claim 7, wherein, The diode D4 is connected with the resistor R8 in parallel.

9. The output overcurrent protection circuit with adjustable time according to claim 8, wherein, The capacitor C1 and the capacitor C2 are electrolytic capacitors.

10. The output overcurrent protection circuit with adjustable time according to claim 9, wherein, The triode Q1 is an NPN triode, and the triode Q2 is a PNP triode.

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