Dual comparison loop control system for switched capacitor DC-DC converter

Abstract

The invention discloses a dual-comparison loop control system for a switched capacitor DC-DC converter. The dual-comparison loop control system comprises a main comparator, a secondary comparator, a D trigger triggered by multiple clocks, a charge pump and a voltage-controlled oscillator. Through the comparison of two loops of the main comparator and the secondary comparator, the reference voltage is quickly adjusted to be between the maximum value and the minimum value of the output voltage ripple by adjusting the pulse number of a driving clock of the converter by utilizing the characteristics of the output ripple of the converter. Due to the fact that the secondary comparator loop can be triggered for multiple times in the working process and is not influenced by a driving clock signal of the main comparator, the control system enables the converter to rapidly recover the steady state under the condition of load transient. A driving clock signal of the main comparator is generated by the voltage-controlled oscillator, and the frequency of the driving clock signal is proportional to the size of the load current, so that the energy loss of the control system under the light load is reduced, and the quick response of load transient is realized under the condition that the efficiency is not lost.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuits, and particularly relates to a double comparison loop control system for a switched capacitor DC-DC converter. BACKGROUND

[0002] The switched capacitor DC-DC converter is a kind of switched power supply, which can convert a certain value of DC voltage or a certain range of DC voltage into another DC voltage, and is generally composed of a power switch, a flying capacitor and an output capacitor. As a key module of the power management system, the switched capacitor DC-DC converter can adapt to the changes of the load, ensure the stability of the output voltage and continuously supply power to the load. In recent years, the rapid development of the Internet of Things system has put forward the requirements of miniaturization and high efficiency for the power management unit, and the switched capacitor DC-DC converter does not need to use a large off-chip inductor compared with the switched inductor DC-DC converter, so it has gradually become a research hotspot in the power management unit. In order to adapt to different working conditions and application scenarios, under the premise of ensuring high efficiency, the switched capacitor DC-DC converter should adjust the frequency and other strategies through closed-loop feedback control to cope with the changes of the load, and the system should quickly enter the stable working state when the load changes from light load to heavy load, which puts forward strict requirements for the load transient response time of the switched capacitor DC-DC converter.

[0003] The traditional control strategy for the switched capacitor DC-DC converter generally adopts PFM (pulse frequency modulation) or single-loop low-side hysteresis comparison scheme to cope with the changes of the load. For example, the document [Y. Lu and J. Jiang. A multi-phase switched capacitor DC-DC converter loop with fast transient response and small ripple characteristics. IEEE Journal of Solid-State Circuits, February 2017, vol. 52, no. 2, pp. 579-591] proposes a pulse frequency modulation control strategy, but the length of the pulse frequency modulation loop adopted by it is limited, which results in slow response speed of the converter when the load changes suddenly, and additional transient response enhancement circuit is needed. The traditional low-side hysteresis control scheme compares the output voltage with the reference voltage by using a higher frequency clock, thereby improving the response time of the system. For example, the document [N. Butzen and M. S. J. Steyaert. Scalable charge-repartitioning: design of a highly efficient fully integrated switched capacitor DC-DC converter. IEEE Journal of Solid-State Circuits, December 2016, vol. 51, no. 12, pp. 2843-2853], but the higher frequency will result in higher power consumption of the controller, which will damage the overall efficiency of the system. SUMMARY

[0004] In view of the above, the application provides a double comparison loop control system for a switched capacitor DC-DC converter, which can improve the conversion efficiency of the DC-DC converter under light load and greatly reduce the power consumption of the control circuit.

[0005] A double comparison loop control system for a switched capacitor DC-DC converter comprises: a main comparator for comparing the minimum value of the output voltage ripple of the switched capacitor DC-DC converter with a reference voltage when the clock rising edge comes, and generating a pulse increase signal PUMP and a pulse decrease signal SKIP; a secondary comparator for comparing the maximum value of the output voltage ripple of the switched capacitor DC-DC converter with the reference voltage when the clock rising edge comes, and generating two pulse increase signals PUMP2 and PUMP3, the secondary comparator being turned on after the converter clock is inverted; a multi-clock triggered D flip-flop for increasing or decreasing the pulses of the converter clock according to the pulse increase signals PUMP, PUMP2 and PUMP3, so as to generate a clock signal for driving the switched capacitor DC-DC converter and a clock signal for driving the secondary comparator; a charge pump for generating the input voltage of a voltage-controlled oscillator through switched capacitor technology according to the pulse increase signals PUMP2 and PUMP3 and the pulse decrease signal SKIP, so as to control the increase or decrease of the clock frequency of the main comparator; a voltage-controlled oscillator for generating a clock signal with a frequency proportional to the input voltage to drive the main comparator.

[0006] Further, the main comparator comprises five NMOS tubes M0, M1, M2, M4 and M5, six PMOS tubes M3, M6, M7, M8, M9 and M10, and two CMOS inverters I0 and I1. 10 The source of M0 is grounded, the gate of M0 is connected to a clock signal VCLK, the drain of M0 is connected to the source of M1 and the source of M2, the gate of M1 is connected to a reference voltage VREF, the drain of M1 is connected to the drain of M3 and the source of M4, the gate of M2 is connected to the output voltage VOUT of the switched capacitor DC-DC converter, the drain of M2 is connected to the source of M5 and the drain of M6, the gate of M3 is connected to the gate of M6, the gate of M7 and the gate of M10, the source of M3 is connected to the source of M6, the source of M7, the source of M8, the source of M9 and the source of M10, the gate of M4 is connected to the gate of M8, the drain of M9, the drain of M5, the drain of M6 and the drain of M7, the source of M5 is connected to the drain of M2 and the drain of M6, the drain of M6 is connected to the drain of M3 and the source of M4, the gate of M6 is connected to the gate of M3, the gate of M7 and the gate of M10, the source of M6 is connected to the source of M3, the source of M7, the source of M8, the source of M9 and the source of M10, the gate of M7 is connected to the gate of M3, the gate of M6 and the gate of M10, the source of M7 is connected to the source of M3, the source of M6, the source of M8, the source of M9 and the source of M10, the gate of M8 is connected to the gate of M4, the source of M8 is connected to the source of M3, the source of M6, the source of M7, the source of M9 and the source of M10, the gate of M9 is connected to the gate of M4, the source of M9 is connected to the source of M3, the source of M6, the source of M7, the source of M8 and the source of M10, the gate of M10 is connected to the gate of M3, the gate of M6 and the gate of M7, and the source of M10 is connected to the source of M3, the source of M6, the source of M7, the source of M8 and the source of M9. REF OUT 10 10 10 ​​​​The drain of M4 is connected to the drain of M7, the drain of M8, the gate of M9, the gate of M5, and the input of I1. The output of I0 generates a pulse decrease signal SKIP, and the output of I1 generates a pulse increase signal PUMP.

[0007] Further, the secondary comparator comprises two rising edge triggered comparators CMP2 and CMP3, wherein the clock terminal of CMP2 is connected to the clock signal CLK D , the clock terminal of CMP3 is connected to the clock signal CLK DB , the non-inverting input terminal of CMP2 is connected to the non-inverting input terminal of CMP3 and connected to the reference voltage V REF , the inverting input terminal of CMP2 is connected to the inverting input terminal of CMP3 and connected to the switched capacitor DC-DC converter output voltage V OUT , the output of CMP2 generates a pulse increase signal PUMP2, and the output of CMP3 generates a pulse increase signal PUMP3.

[0008] Further, the D flip-flop comprises nine CMOS inverters I2-I 10 , three delay buffers B0-B2, three 2-input AND gates A0-A2, a 3-input OR gate O1, and four CMOS transmission gates T1-T4, wherein the input of I2 is connected to the first input of A0 and connected to the pulse increase signal PUMP, the output of I2 is connected to the input of B0, the output of B0 is connected to the second input of A0, the output of A0 is connected to the first input of O1; the input of I3 is connected to the first input of A1 and connected to the pulse increase signal PUMP2, the output of I3 is connected to the input of B1, the output of B1 is connected to the second input of A1, the output of A1 is connected to the second input of O1; the input of I4 is connected to the first input of A2 and connected to the pulse increase signal PUMP3, the output of I4 is connected to the input of B2, the output of B2 is connected to the second input of A2, the output of A2 is connected to the third input of O1, the output of O1 is connected to the input of I 10 , the first clock terminal of T1, the first clock terminal of T2, the first clock terminal of T3, and the first clock terminal of T4, the output of I 10The output end of the D flip-flop is connected with the second clock end of T1, the second clock end of T2, the second clock end of T3 and the second clock end of T4, the input end of T1 is the input end of the D flip-flop, the output end of T1 is connected with the input end of I5 and the output end of T2, the output end of I5 is connected with the input end of T3 and the input end of I6, the output end of I6 is connected with the input end of T2, the output end of T3 is connected with the input end of I7 and the output end of T4, the output end of I7 is connected with the input end of I9 and the input end of I8 and is the positive output end of the D flip-flop, the output end of I9 is the negative output end of the D flip-flop, and the output end of I8 is connected with the input end of T4.

[0009] Further, the positive output end of the D flip-flop generates a clock signal CLK SW for driving the switched-capacitor DC-DC converter. SW The clock signal CLK D is generated after being delayed by a delay time T D by a delay buffer B3 and is used to drive the comparator CMP2. D The clock signal CLK 11 is generated after being inverted by an inverter I DB and is used to drive the comparator CMP3. D The input end of the D flip-flop is connected with the negative output end.

[0010] Further, the delay time T D of the delay buffer B3 is initially set as the time difference between the minimum value and the maximum value of the output voltage ripple of the switched-capacitor DC-DC converter, and then is fixed by simulation under the condition of the maximum load of the system, so as to be applicable to the full load range of the system.

[0011] Further, the charge pump comprises a 2-input OR gate O2, a CMOS inverter I 12 , a capacitor C0, two NMOS transistors M 11 and M 12 , and two PMOS transistors M 13 and M 14 . 12 The two input ends of O2 are respectively connected with pulse increase signals PUMP2 and PUMP3, the output end of O2 is connected with the input end of I 12 , the output end of I 14 is connected with the gate of M 14 , the source of M 14 is connected with the power supply voltage VDD, the drain of M 13 is connected with the source of M 13 , the gate of M 13 is connected with an external bias voltage VBP, and the drain of M 12 is connected with one end of C0 and the source of Mdrain of M CTRL , M 12 gate of M 12 source of M 11 drain of M 11 gate of M 11 source of C0 is grounded.

[0012] Further, the voltage-controlled oscillator comprises three CMOS inverters I 13 ~I 15 , five NMOS transistors M 21 ~M 24 , M 15 , a resistor R1 and five PMOS transistors M 16 ~M 20 , wherein the source of M 16 is connected to the source of M 17 , the source of M 18 , the source of M 19 , the source of M 20 and the source of M 15 , the gate of M CTRL is connected to the input voltage V 21 of the voltage-controlled oscillator, the source of M 22 is grounded, the source of M 23 is grounded, the source of M 24 is grounded and one end of R1 is grounded, the source of M 15 is connected to the other end of R1, the drain of M 15 is connected to the gate of M 16 , the drain of M 16 , the gate of M 17 , the gate of M 18 , the gate of M 19 and the gate of M 20 , the drain of M 17 is connected to the gate of M 21 , the drain of M 21 , the gate of M 22 , the gate of M 23 and the gate of M 24 , the drain of M 22 is connected to the ground terminal of I 13 , the drain of M 18 is connected to the power supply terminal of I 13 , the drain of M 19 is connected to the power supply terminal of I 14 , the drain of M 23 is connected to the ground terminal of I 14 , the drain of M 20 is connected to I15 the ground terminal of the M 24 the drain terminal of the I 15 the ground terminal of the I 13 the input terminal of the I 15 the output terminal of the I 13 the output terminal of the I 14 the input terminal of the I 14 the output terminal of the I 15 the input terminal of the I

[0013] The application utilizes the ripple characteristics of the output voltage of the switched capacitor DC-DC converter, and makes the reference voltage between the maximum and minimum values of the output voltage ripple through the two comparison loops of the main comparator and the secondary comparator; the main comparator can ensure the normal operation of the system in the steady state, and the secondary comparator generates the clock pulse increase signal or the pulse decrease signal to adjust the number of pulses of the driving clock of the converter when the load suddenly changes, so that the converter quickly recovers to the steady state. Since the secondary comparator can be triggered multiple times and quickly drive the converter, compared with the traditional pulse frequency modulation scheme which needs to wait for the response of the converter after the frequency is changed once, then compares and adjusts, the transient response of the system is greatly improved; in addition, the driving clock of the main comparator can adjust the frequency according to the change of the load, and when the load is large, the comparison and reaction are carried out at a faster speed, and when the load is small, the comparison is carried out at a slower frequency, so that the power consumption of the controller is proportional to the load, and the conversion efficiency under light load is improved. In the steady state, the application only needs to compare twice in one period, so that the power consumption of the control circuit is greatly reduced.

[0014] Compared with the prior art, the application utilizes the ripple characteristics of the output voltage of the converter, the main comparator compares the minimum value of the output voltage ripple with the reference voltage, and the secondary comparator compares the maximum value of the output voltage ripple with the reference voltage, and the number of pulses of the driving clock of the converter is increased or decreased according to the comparison results of the main comparator and the secondary comparator. In addition, the application adjusts the input voltage of the voltage-controlled oscillator according to the comparison results of the main comparator and the secondary comparator to adjust the clock frequency, so that the driving clock frequency of the main comparator is proportional to the load, and the control strategy only compares twice in one period in the steady state, so that the power consumption of the control circuit is reduced. The application adjusts the driving clock of the converter to make the value of the reference voltage fall between the maximum and minimum values of the output voltage ripple of the converter, so that the steady state is reached. Simulation results show that when the control system of the application is applied to the recursive switched capacitor DC-DC converter system, the response time of the load current transient (10 μA ↔ 1 mA) is less than 3 μs, and the closed-loop efficiency of the system reaches 86.2%. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 It is a structure schematic diagram of the switched capacitor DC-DC converter and the control system thereof in the application.

[0016] Figure 2 This is a timing diagram of the dual comparator loop control system for the switched capacitor DC-DC converter in this invention.

[0017] Figure 3 This is a schematic diagram of the main comparator in the control system of the present invention.

[0018] Figure 4 This is a schematic diagram of the structure of a multi-clock triggered D flip-flop in the control system of the present invention.

[0019] Figure 5 This is a schematic diagram of the charge pump and voltage-controlled oscillator in the control system of the present invention.

[0020] Figure 6 This is a schematic diagram of the load transient response of the control system of the present invention. Detailed Implementation

[0021] To describe the present invention in more detail, the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] Figure 1 It includes a switched-capacitor DC-DC converter and a load capacitor C. L Load resistance R L The invention also describes the circuit structure of the dual-comparison loop control system, which consists of a main comparator, a secondary comparator, a multi-clock triggered D flip-flop, a charge pump, and a voltage-controlled oscillator.

[0023] like Figure 1 As shown, due to the output voltage V of the switched capacitor DC-DC converter OUT There is ripple, and the output voltage V in each cycle is... OUT Does there exist a minimum value V? OUT(MIN) and maximum value V OUT(MAX) Reference voltage V REF It is a relatively stable DC value. When the system is in steady state, the reference voltage V REF It should be within the range of the output voltage ripple, that is, satisfy V OUT(MIN) <V REF <V OUT(MAX) At this time, the main comparator CMP1 is driven by the clock signal VCLK generated by the voltage-controlled oscillator, and compares V once every VCLK clock cycle. REF With V OUT(MIN) The PUMP signal increments by one pulse (generating a rising edge), while the SKIP signal decrements by remaining low. A multi-clock triggered D flip-flop receives the rising edge of the PUMP signal and triggers it once, causing the converter to drive the clock signal CLK. SWA flip produces a rising edge (or falling edge), CLK SW The flip is delayed by time T after passing through delay buffer B3. D , making CLK D The toggle generates a rising edge (or a falling edge) for the clock signal CLK. D After passing through CMOS inverter I 11 Then make the clock signal CLK DB The toggle generates a falling edge (or a rising edge), driving the secondary comparators CMP2 and CMP3 for comparison. Since the clock signals of secondary comparators CMP2 and CMP3 are inverted (180° out of phase), only one of comparators CMP2 and CMP3 is in normal operation when the secondary comparison loop is working, while the other waits for the clock to drive it. A suitable clock signal T is selected. D Delay, the comparator can be used for V REF and V OUT(MAX) A comparison is made, generating pulse-increment signals PUMP2 and PUMP3. In steady state, both PUMP2 and PUMP3 are low, i.e., V... REF <V OUT(MAX) This indicates that the converter drives the clock signal CLK. SW It has reached near its optimal value. In steady state, the multi-clock triggered D flip-flop toggles only once per VCLK clock cycle, generating a uniformly pulsed converter clock CLK. SW The switched capacitor DC-DC converter is stably driven by a two-phase non-overlapping clock generation circuit.

[0024] like Figure 2 As shown, when the system load changes from heavy load to light load, the minimum ripple value of the output voltage of the switched capacitor DC-DC converter will be higher than the reference voltage, i.e., V. OUT(MIN) >V REF When the rising edge of the clock signal VCLK arrives, the main comparator compares and obtains V. OUT(MIN) >V REF When the pulse decrease signal SKIP changes from low to high, and the pulse increase signal PUMP remains low, the multi-clock triggered D flip-flop is not triggered, thus driving the converter's clock CLK. SW Without flipping, the secondary comparator is not triggered due to the load R. L The function of switched capacitor DC-DC converter output voltage V OUT It gradually decreases until the next rising edge of VCLK arrives. When the main comparator detects V... OUT(MIN) <V REF When the pulse increment signal PUMP generates a high level, it triggers the multi-clock triggered D flip-flop to flip, the secondary comparator is re-triggered, and the output voltage V of the switched capacitor DC-DC converter is adjusted. OUTUntil the reference voltage V REF Falling back to V OUT The ripple is between its maximum and minimum values. During this process, the pulse reduction signal SKIP, through a charge pump, reduces the input voltage V of the voltage-controlled oscillator. CTRL The comparison frequency of the main comparator gradually decreases as the load decreases, thus reducing the power consumption of the controller under light load conditions.

[0025] When the load changes from light load to heavy load, such as Figure 2 As shown, the output voltage drops due to a surge in load, causing V to... OUT The maximum value of the ripple is less than the reference voltage V. REF V OUT(MAX) <V REF When the rising edge of the VCLK clock arrives, the main comparator compares and obtains V. OUT(MIN) <V REF When the pulse increase signal PUMP changes from low to high, and the pulse decrease signal SKIP remains low, the multi-clock triggered D flip-flop produces a toggle, driving the switched-capacitor DC-DC converter's clock CLK. SW A rising edge (or a falling edge) is generated, and the switched-capacitor DC-DC converter performs one charge transfer, V OUT Slow rise. Clock signal CLK SW The change is delayed by time T after passing through delay buffer B3. D The comparator is then triggered to perform the comparison and obtain V. OUT(MAX) <V REF The pulse increment signal PUMP2 or PUMP3 generates a pulse (changing from low to high), triggering the clock CLK of the driver converter. SW The flip-flop generates a falling edge (or a rising edge), driving the switched-capacitor DC-DC converter to output capacitor C. L Charging, output voltage V OUT Continue to rise. Delay T D The selection of T is determined by the time difference between the minimum and maximum output voltage ripple under maximum load conditions of the switched capacitor DC-DC converter. Under maximum load conditions, T is selected... D This delay value is then applicable across the entire system load range. Clock signal CLK SW The flip is delayed by time T after passing through delay buffer B3. D The comparator is then triggered again. The comparator's ability to be triggered multiple times significantly reduces the response time to load surges. Pulse increment signals PUMP2 and PUMP3, via a charge pump, increase the input voltage V of the voltage-controlled oscillator. CTRL As the load increases, the comparison frequency of the main comparator also increases until the reference voltage V... REFThe output voltage V OUT The maximum and minimum values of the ripple, entering a steady state.

[0026] As Figure 3 shown, the main comparator includes NMOS tubes M0~M2 and M4~M5, PMOS tube M3 and M6~M 10 and CMOS inverters I0 and I1, wherein NMOS tube M0 acts as a tail current source of the comparator when VCLK is high, NMOS tube M1 and NMOS tube M2 are two input tubes, and the voltages of the gates are input V REF and V OUT are converted into currents in proportion. When the clock VCLK is high, the voltages of OUT+ and OUT- gradually start to drop from VDD, and if V REF >V OUT , since the input tubes are NMOS tubes, the current flowing through NMOS tube M1 is larger, and the signal OUT- drops faster. NMOS tube M4, PMOS tube M8, NMOS tube M5, and PMOS tube M9 constitute a latch circuit composed of two CMOS inverters connected in series, and when the signal OUT- drops to below the flip level of the CMOS inverter composed of NMOS tube M5 and PMOS tube M9, the signal OUT+ becomes high, and the signals OUT- and OUT+ are saved through the latch circuit until the next time VCLK becomes high. PMOS tube M3, PMOS tube M6, PMOS tube M7, and PMOS tube M 10 are reset switches, and when the clock VCLK is low, the signals OUT+ and OUT- are reset to VDD, that is, the output signals PUMP and SKIP are reset to low.

[0027] As Figure 4 shown, the multi-clock triggered D flip-flop includes CMOS inverters I2~I 10 , delay buffers B0~B2, 2-input AND gates A0~A2, a 3-input OR gate O1, and CMOS transmission gates T1~T4, wherein the rising edge of the PUMP signal can be extracted through the AND operation of the pulse increasing signal PUMP and the signal PUMP after the pulse increasing signal PUMP passes through the CMOS inverter I2 and the delay buffer B0, and the rising edges of the pulse increasing signals PUMP2 and PUMP3 are also extracted in the same way. The 2-input AND gates A0~A2 generate signals CKP, CKP2, and CKP3 as the output of the 3-input OR gate O1, and the clock signal CLKUP generated through the 3-input OR gate O1 contains the rising edge information of the three pulse increasing signals. CLKUP passes through the inverter I 10The inverse clock signal CLKUPB is obtained. The CMOS transfer gates T1-T4 and the CMOS inverters I5-I9 form a D flip-flop, the CMOS transfer gate T2, the CMOS inverter I5 and the CMOS inverter I6 form a latch, and the CMOS transfer gate T4, the CMOS inverter I7 and the CMOS inverter I8 form a latch. When the clock signal CLKUP is low, the input signal D is stored in the first latch, and the second latch is disconnected from the first latch and keeps the output signal Q unchanged; when the clock signal CLKUP is high, the output signal Q of the second latch is refreshed to the value of the input signal D, and the first latch is disconnected from the input signal and keeps the value of the latch, thus the flip-flop can make the output signal equal to the input signal at the rising edge of the clock signal CLKUP, i.e. Q=D, and keep the output signal Q unchanged at other times. The output signal QB is the inverse of the output signal Q, and when the input signal D and the output signal QB are connected together, the rising edge of the clock signal CLKUP makes the output signal Q flip once, and keeps unchanged at other times.

[0028] As shown in Figure 5 , the charge pump comprises a PMOS transistor M 13 ~M 14 , an NMOS transistor M 11 ~M 12 , a 2-input OR gate O2, a CMOS inverter I 12 , and a capacitor C0, wherein the gate of the PMOS transistor M 14 is connected to the output of the CMOS inverter I 12 and to the UP signal, and the gate of the NMOS transistor M 11 is connected to the SKIP signal generated by the main comparator to control the conduction or turn-off of the upper and lower current sources and generate the input voltage V CTRL of the voltage-controlled oscillator. The voltage-controlled oscillator comprises a resistor R1, NMOS transistors M 15 and M 21 ~M 24 , PMOS transistors M 16 ~M 20 , and CMOS inverters I 13 ~I 15 , wherein the source of the NMOS transistor M 15 is connected to one end of the resistor R1 to form a source negative feedback, so that the current flowing through the NMOS transistor M 15 has a relatively linear relationship with the gate voltage V 15 of the NMOS transistor M CTRL , the PMOS transistors M 16 ~M 20 and the NMOS transistors M 21 ~M 24 are current mirrors to copy the NMOS transistor M 15The current flowing through it controls the CMOS inverter I. 13 ~I 15 The charging and discharging current is used to control the delay time. CMOS inverter I 13 ~I 15 An odd-order loop is formed, which can oscillate and generate a clock signal VCLK under the influence of slight disturbances, with an input voltage V. CTRL The larger the value, the higher the frequency of the clock signal VCLK generated by the voltage-controlled oscillator.

[0029] like Figure 6 As shown, when the load current I LOAD When the voltage suddenly changes from 1mA to 10μA, the pulse increase signals PUMP2 and PUMP3 remain at a low level, while the pulse decrease signal SKIP changes from a low level to a high level. The input voltage V of the voltage-controlled oscillator is then obtained via a charge pump. CTRL Continuously decrease until the reference voltage V REF Reaching the output voltage V OUT Between the maximum and minimum values ​​of ripple. When the load current I... LOAD When the voltage suddenly changes from 10μA to 1mA, the pulse increment signal PUMP goes high, triggering the converter clock CLK. SW The flip, after T D After a delay, comparators CMP2 and CMP3 are triggered for comparison. The pulse increment signals PUMP2 and PUMP3 change from low to high, which again triggers the converter clock CLK. SW The flip, V OUT The voltage then gradually increases until it reaches the reference voltage V. REF Returning to the output voltage V OUT The ripple value is between its maximum and minimum values. The delay T of delay buffer B3. D This is a constant value obtained from simulation under the system's maximum load condition, and it is applicable to the entire load range of the system. In this system, T... D Take 10.8 ns. For example... Figure 6 As shown, the load current I LOAD When the voltage drops from 1 mA to 10 μA, the transient response time of the system is 1 μs, and when the voltage drops from 10 μA to 1 mA, the transient response time of the system is 2.8 μs, which shows that the system of the present invention has the ability to respond quickly to load transients.

[0030] The control system of this invention compares two loops, a main comparator and a secondary comparator, and utilizes the output ripple characteristics of a switched-capacitor DC-DC converter. By adjusting the number of pulses in the converter's drive clock, the reference voltage V is rapidly adjusted. REF Adjust to output voltage V OUTThe maximum and minimum values of the ripple. Since the secondary comparator loop can be triggered multiple times during operation without being affected by the main comparator driving clock signal VCLK, the control system enables the switched-capacitor DC-DC converter to quickly recover to steady state in the case of load transients. The main comparator driving clock signal VCLK is generated by a voltage-controlled oscillator, the frequency of which is proportional to the size of the load current, reducing the energy loss of the control system under light load, thereby achieving fast response to load transients without loss of efficiency. Simulation results show that the response time of the control system of the present application is not more than 3 μs under the load current from 10 μA ↔ 1 mA transients.

[0031] The above description of the embodiments is to facilitate the understanding and application of the present application for those skilled in the art, and those skilled in the art can easily make various modifications to the above embodiments, and apply the general principles described herein to other embodiments without creative labor. Therefore, the present application is not limited to the above embodiments, and the improvements and modifications made to the present application by those skilled in the art based on the disclosure of the present application should be within the scope of protection of the present application.

Claims

1. A dual comparator loop control system for a switched-capacitor DC-DC converter, characterized in that, include: The main comparator compares the minimum output voltage ripple of the switched capacitor DC-DC converter with the reference voltage at the rising edge of the clock, generating a pulse increase signal PUMP and a pulse decrease signal SKIP. The secondary comparator is turned on after a delay after the converter clock flips. It is used to compare the maximum value of the output voltage ripple of the switched capacitor DC-DC converter with the reference voltage when the rising edge of the clock arrives, and generate two pulse increment signals PUMP2 and PUMP3. The multi-clock triggered D flip-flop increments or decrements the converter clock pulses based on the pulse increment signals PUMP, PUMP2, and PUMP3, thereby generating the clock signal to drive the switched capacitor DC-DC converter and the clock signal to drive the secondary comparator. The charge pump generates the input voltage of the voltage-controlled oscillator based on the pulse increase signals PUMP2 and PUMP3 and the pulse decrease signal SKIP through switched capacitor technology, which is used to control the increase or decrease of the clock frequency of the main comparator. A voltage-controlled oscillator is used to generate a clock signal whose frequency is proportional to the input voltage to drive the main comparator.

2. The dual comparator loop control system for a switched-capacitor DC-DC converter according to claim 1, characterized in that: The main comparator comprises five NMOS tubes M0, M1, M2, M4, M5, six PMOS tubes M3, M6, M7, M8, M9, M 10 and two CMOS inverters I0 and I1, wherein the source of M0 is grounded, the gate of M0 is connected with a clock signal VCLK, the drain of M0 is connected with the source of M1 and the source of M2, the gate of M1 is connected with a reference voltage V REF , the drain of M1 is connected with the drain of M3 and the source of M4, the gate of M2 is connected with the output voltage V OUT of the switched capacitor DC-DC converter, the drain of M2 is connected with the source of M5 and the drain of M6, the gate of M3 is connected with the gate of M6, the gate of M7 and the gate of M 10 , the source of M3 is connected with the source of M6, the source of M7, the source of M8, the source of M9 and the source of M 10 , the gate of M4 is connected with the gate of M8, the drain of M9, the drain of M5, the drain of M 10 and the input end of I0, the drain of M4 is connected with the drain of M7, the drain of M8, the gate of M9, the gate of M5 and the input end of I1, the output end of I0 generates a pulse reduction signal SKIP, and the output end of I1 generates a pulse increase signal PUMP.

3. The dual comparator loop control system for a switched-capacitor DC-DC converter according to claim 1, characterized in that: The secondary comparator comprises two rising edge triggered comparators CMP2 and CMP3, wherein the clock terminal of CMP2 is connected to the clock signal CLK D , the clock terminal of CMP3 is connected to the clock signal CLK DB , the non-inverting input terminal of CMP2 is connected to the non-inverting input terminal of CMP3 and connected to the reference voltage V REF , the inverting input terminal of CMP2 is connected to the inverting input terminal of CMP3 and connected to the switched capacitor DC-DC converter output voltage V OUT , the output terminal of CMP2 generates the pulse increase signal PUMP2, and the output terminal of CMP3 generates the pulse increase signal PUMP3.

4. The dual comparator loop control system for a switched-capacitor DC-DC converter according to claim 1, characterized in that: The D flip-flop comprises nine CMOS inverters I2~I 10 three delay buffers B0~B2, three 2-input AND gates A0~A2, a 3-input OR gate O1 and four CMOS transmission gates T1~T4, wherein the input end of I2 is connected with the first input end of A0 and connected with a pulse increasing signal PUMP, the output end of I2 is connected with the input end of B0, the output end of B0 is connected with the second input end of A0, the output end of A0 is connected with the first input end of O1; the input end of I3 is connected with the first input end of A1 and connected with a pulse increasing signal PUMP2, the output end of I3 is connected with the input end of B1, the output end of B1 is connected with the second input end of A1, the output end of A1 is connected with the second input end of O1; the input end of I4 is connected with the first input end of A2 and connected with a pulse increasing signal PUMP3, the output end of I4 is connected with the input end of B2, the output end of B2 is connected with the second input end of A2, the output end of A2 is connected with the third input end of O1, the output end of O1 is connected with the input end of I 10 , the first clock end of T1, the first clock end of T2, the first clock end of T3 and the first clock end of T4, the output end of I 10 is connected with the second clock end of T1, the second clock end of T2, the second clock end of T3 and the second clock end of T4, the input end of T1 is the input end of the D flip-flop, the output end of T1 is connected with the input end of I5 and the output end of T2, the output end of I5 is connected with the input end of T3 and the input end of I6, the output end of I6 is connected with the input end of T2, the output end of T3 is connected with the input end of I7 and the output end of T4, the output end of I7 is connected with the input end of I9 and the input end of I8 and is the positive output end of the D flip-flop, the output end of I9 is the negative output end of the D flip-flop, the output end of I8 is connected with the input end of T4.

5. The dual comparator loop control system for a switched-capacitor DC-DC converter according to claim 3, characterized in that: The non-inverted output of the D flip-flop generates a clock signal CLK for driving a switched-capacitor DC-DC converter SW , CLK SW After being delayed by a delay buffer B3 by a time T D , the clock signal CLK D is generated for driving the comparator CMP2 D After being inverted by an inverter I 11 , the clock signal CLK DB is generated for driving the comparator CMP3, the input of the D flip-flop being connected to the inverted output.

6. The dual comparator loop control system for a switched-capacitor DC-DC converter according to claim 5, characterized in that: The time delay duration T of the time delay buffer B3 D The initial value is the time difference between the minimum and maximum values of the output voltage ripple of the switched capacitor DC-DC converter, and the final value is obtained by simulation under the maximum load condition of the system, so as to be applicable to the full load range of the system.

7. The dual comparator loop control system for a switched-capacitor DC-DC converter according to claim 1, characterized in that: The charge pump comprises a 2-input OR gate O2, a CMOS inverter I 12 , a capacitor C0, two NMOS transistors M 11 and M 12 , and two PMOS transistors M 13 and M 14 , wherein the two inputs of O2 are connected to pulse increase signals PUMP2 and PUMP3 respectively, the output of O2 is connected to the input of I 12 , the output of I 12 is connected to the gate of M 14 , the source of M 14 is connected to a power supply voltage VDD, the drain of M 14 is connected to the source of M 13 , the gate of M 13 is connected to a bias voltage VBP, the drain of M 13 is connected to one end of C0 and the drain of M 12 to generate an input voltage V CTRL of a voltage-controlled oscillator, the gate of M 12 is connected to a bias voltage VBN, the source of M 12 is connected to the drain of M 11 , the gate of M 11 is connected to a pulse decrease signal SKIP, and the source of M 11 is connected to the other end of C0, both of which are grounded.

8. The dual comparator loop control system for a switched-capacitor DC-DC converter according to claim 1, characterized in that: The voltage-controlled oscillator comprises three CMOS inverters I 13 ~I 15 、 five NMOS transistors M 21 ~M 24 and M 15 , one resistor R1 and five PMOS transistors M 16 ~M 20 , wherein the source of M 16 is connected to the source of M 17 , the source of M 18 , the source of M 19 and the source of M 20 , the gate of M 15 is connected to the input voltage V CTRL of the voltage-controlled oscillator, the source of M 21 is connected to the source of M 22 , the source of M 23 , the source of M 24 and one end of R1, the source of M 15 is connected to the other end of R1, the drain of M 15 is connected to the gate of M 16 , the drain of M 16 , the gate of M 17 , the gate of M 18 , the gate of M 19 and the gate of M 20 , the drain of M 17 is connected to the gate of M 21 , the drain of M 21 , the gate of M 22 , the gate of M 23 and the gate of M 24 , the drain of M 22 is connected to the ground terminal of I 13 , the drain of M 18 is connected to the power supply terminal of I 13 , the drain of M 19 is connected to the power supply terminal of I 14 , the drain of M 23 is connected to the ground terminal of I 14 , the drain of M 20 is connected to the power supply terminal of I 15 , the drain of M 24 is connected to the ground terminal of I 15 , the input terminal of I 13 is connected to the output terminal of I 15 and generates a clock signal VCLK used to drive the main comparator, the output terminal of I 13 is connected to the input terminal of I 14 , the output terminal of I 14 is connected to the output terminal of I 15 The input terminal is connected.

Images