Mode control circuit of converter and converter

Abstract

The invention relates to the technical field of voltage conversion, and discloses a mode control circuit of a converter and the converter, the converter comprises an inductor, the mode control circuit is characterized in that a first detection end of a first voltage detection unit is connected with a first end of the inductor, and a second detection end of the first voltage detection unit is connected with a second end of the inductor; the first voltage detection unit is configured to detect and maintain the voltages at the two ends of the inductor to obtain a first voltage detection value and a second voltage detection value, and the difference between the first voltage detection value and the second voltage detection value is used for representing the difference between the voltage at the input end and the voltage at the output end of the converter; the control unit is configured to control an operating mode of the converter based on a difference between the first voltage detection value and the second voltage detection value. According to the invention, by optimizing the judgment condition of mode switching, the accuracy of mode control on the converter is greatly improved, and the stability and the working efficiency of the converter are further improved.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a mode control circuit for a converter and a converter. Background Technology

[0002] A converter can typically adjust the output voltage to be higher or lower than the input voltage. It usually consists of a Buck circuit or a Boost circuit, which is composed of a switching transistor, an inductor, an input capacitor, and an output capacitor.

[0003] Due to the non-ideal characteristics of the components in the circuit, signal jumps occur during the transition between different operating modes. Nonlinear control is generally required to improve the smoothness of the mode switching process. However, the prerequisite for using nonlinear control is determining which operating mode the converter should be in and when mode switching is necessary.

[0004] In related technologies, the relationship between input voltage and output voltage is generally used to control the switching of modes. However, due to the complex circuit structure of the converter, it is difficult to achieve effective switching of the converter's operating modes, thus affecting the converter's buck-boost performance. Summary of the Invention

[0005] This application provides a mode control circuit and converter for a converter, which solves the technical problem that the mode switching point determined by directly using the relationship between the input voltage and the output voltage has low accuracy. By optimizing the judgment conditions for mode switching, the accuracy of mode control of the converter is greatly improved, thereby improving the stability and working efficiency of the converter.

[0006] To achieve the above objectives, the main technical solutions adopted in this application include:

[0007] In a first aspect, embodiments of this application provide a mode control circuit for a converter, the converter including an inductor, a first end of the inductor being adapted to be connected to the input terminal of the converter, and a second end of the inductor being adapted to be connected to the output terminal of the converter, the mode control circuit including:

[0008] A first voltage detection unit is configured to detect and hold the voltage across the inductor to obtain a first voltage detection value and a second voltage detection value. The difference between the first voltage detection value and the second voltage detection value is used to characterize the difference between the input voltage and the output voltage of the converter.

[0009] A control unit is configured to control the operating mode of the converter based on the difference between the first voltage detection value and the second voltage detection value, wherein the operating mode of the converter includes at least one of a boost mode, a buck mode, and a buck-boost mode.

[0010] The mode control circuit proposed in this application realizes real-time monitoring of the voltage difference across the inductor during charging and discharging by using the difference between the first voltage detection value and the second voltage detection value detected by the first voltage detection unit. The control unit then controls the converter's operating mode based on the real-time monitoring results, achieving precise switching between boost and buck modes. Therefore, compared to the traditional method of directly using the relationship between input and output voltages for mode switching, this application's mode control circuit accurately detects the difference between the converter's input and output voltages, effectively eliminating the influence of circuit impedance changes such as the switching of transistors on the converter's mode switching. This significantly improves the accuracy of determining the mode switching point, which is beneficial for balancing the converter's stability and efficiency, and improving the converter's buck-boost performance.

[0011] Optionally, in some embodiments of this application, the first voltage detection unit is further configured to detect the voltage across the inductor when the inductor is directly connected to the input and output terminals of the converter.

[0012] Optionally, in some embodiments of this application, the first voltage detection unit is further configured to perform voltage holding operation when the inductor is not directly connected between the input and output terminals of the converter, and to perform voltage detection operation when the inductor is directly connected between the input and output terminals of the converter.

[0013] This embodiment of the application, by setting the working process of voltage detection and voltage holding of the first voltage detection unit, can effectively suppress the interference of the switching action of the switching transistor in the converter on voltage detection, and improve the accuracy of the voltage detection result of the first voltage detection unit on the two ends of the inductor.

[0014] Optionally, in some embodiments of this application, the first voltage detection unit is further configured to,

[0015] After the inductor is directly connected to the input and output terminals of the converter, there is a first delay before the voltage detection is performed, and the voltage holding operation is performed continuously during the first time.

[0016] This embodiment of the application ensures that the first detection unit can effectively detect the voltage across the inductor by delaying the voltage detection operation at the first time, thereby improving the accuracy of voltage detection.

[0017] Optionally, in some embodiments of this application, the control unit is further configured to control the converter to exit the buck mode when the difference between the first voltage detection value and the second voltage detection value is less than a first reference value;

[0018] If the difference between the first voltage detection value and the second voltage detection value is greater than the sum of the first reference value and the first preset threshold, the converter is controlled to enter the buck mode.

[0019] Optionally, in some embodiments of this application, the control unit is further configured to control the converter to exit the boost mode when the opposite of the difference between the first voltage detection value and the second voltage detection value is less than a second reference value;

[0020] If the negative of the difference between the first voltage detection value and the second voltage detection value is greater than the sum of the second reference value and the second preset threshold, the converter is controlled to enter the boost mode.

[0021] This application embodiment uses a control unit to determine the converter's operating mode switching based on a comparison between the voltage difference across the inductor, a relevant reference value, and a preset threshold. This precise control over the converter's operating mode switching is achieved by using this control unit as the criterion for switching. Compared to traditional methods that directly switch modes based on the relationship between input and output voltages, the mode control circuit proposed in this application embodiment effectively eliminates the interference of circuit impedance changes caused by the on-resistance of the switching transistors on the operating mode switching. This significantly improves the accuracy of determining the mode switching point, enabling the converter to switch efficiently between boost and buck modes and improving the converter's buck-boost performance.

[0022] Optionally, in some embodiments of this application, the mode control circuit further includes:

[0023] The second voltage detection unit has a first detection terminal connected to the first terminal of the inductor and a second detection terminal connected to the second terminal of the inductor. The second voltage detection unit is configured to detect the voltage drop generated by the parasitic resistance of the inductor and send the voltage drop to the control unit.

[0024] This application embodiment enables real-time detection of the voltage drop generated by the parasitic resistance of the inductor, i.e., the equivalent series resistance (ESR), by setting a second voltage detection unit. This eliminates the influence of the voltage drop of the parasitic resistance of the inductor on the mode switching of the converter, thereby further improving the accuracy of the mode switching point of the converter.

[0025] Optionally, in some embodiments of this application, the control unit is further configured to,

[0026] If the difference between the first voltage detection value and the second voltage detection value and the difference between the voltage drop are less than the first reference value, the converter is controlled to exit the buck mode;

[0027] If the difference between the first voltage detection value and the second voltage detection value and the difference between the voltage drop are greater than the sum of the first reference value and the first preset threshold, the converter is controlled to enter the buck mode.

[0028] Optionally, in some embodiments of this application, the control unit is further configured to,

[0029] If the difference between the voltage drop and the difference between the first voltage detection value and the second voltage detection value is less than the second reference value, the converter is controlled to exit the boost mode;

[0030] If the difference between the voltage drop and the difference between the first voltage detection value and the second voltage detection value is greater than the sum of the second reference value and the second preset threshold, the converter is controlled to enter the boost mode.

[0031] This application embodiment uses the comparison result between the voltage difference across the inductor, relevant reference values, and a preset threshold as the judgment condition for switching the converter's operating mode by the control unit, thereby accurately controlling the switching of the converter's operating mode. Furthermore, the mode control circuit proposed in this application embodiment can effectively eliminate the interference of circuit impedance changes caused by the on-resistance of the switching transistor and the ESR of the inductor on the switching mode switching, greatly improving the accuracy of the mode switching point determination, thereby enabling the converter to switch efficiently between boost mode and buck mode, and improving the buck-boost effect of the converter.

[0032] Optionally, in some embodiments of this application, the second voltage detection unit includes:

[0033] A first resistor, one end of which is connected to the first end of the inductor;

[0034] A second resistor, one end of which is connected to the second end of the inductor;

[0035] A first capacitor, one end of which is connected to the other end of the first resistor and has a first node, and the other end of the first capacitor is grounded;

[0036] The second capacitor has one end connected to the other end of the second resistor and has a second node, and the other end of the second capacitor is grounded.

[0037] A first differential amplifier is used, with its positive input terminal connected to the first node and its negative input terminal connected to the second node. The output terminal of the first differential amplifier is used to output the voltage drop.

[0038] This application embodiment utilizes a circuit structure composed of resistors and capacitors to realize the voltage sampling and holding function of the second voltage detection unit, and combines it with the first differential amplifier to realize accurate calculation and stable output of the voltage drop detection result, thereby helping the control unit to improve the accuracy of the converter mode switching point by using the detection result output by the first differential amplifier.

[0039] Optionally, in some embodiments of this application, the first voltage detection unit includes:

[0040] A third resistor, one end of which is connected to the first end of the inductor;

[0041] A fourth resistor, one end of which is connected to the second end of the inductor;

[0042] A third capacitor, one end of which is connected to the other end of the third resistor and has a third node, and the other end of the third capacitor is grounded;

[0043] A fourth capacitor, one end of which is connected to the other end of the fourth resistor and has a fourth node, and the other end of the fourth capacitor is grounded;

[0044] A first controllable switch, the first end of which is connected to the third node, and the second end of which is connected to the fourth node;

[0045] The fifth capacitor has one end connected to the third end of the first controllable switch and has a fifth node, and the other end of the fifth capacitor is grounded.

[0046] A sixth capacitor, one end of which is connected to the fourth terminal of the first controllable switch and has a sixth node, and the other end of which is grounded;

[0047] The fifth node is used to output the first voltage detection value, and the sixth node is used to output the second voltage detection value.

[0048] Optionally, in some embodiments of this application, the first voltage detection unit is configured to,

[0049] When the inductor is not directly connected between the input and output terminals of the converter, the first controllable switch is opened and the first voltage detection unit performs voltage holding operation.

[0050] When the inductor is directly connected between the input and output terminals of the converter, the first controllable switch is closed, and the first voltage detection unit performs voltage detection.

[0051] Optionally, in some embodiments of this application, the first voltage detection unit further includes:

[0052] The second controllable switch has its first terminal connected to the third node, its second terminal connected to the fourth node, and its third and fourth terminals connected together and then grounded.

[0053] Optionally, in some embodiments of this application, the first voltage detection unit is configured to,

[0054] Before the first controllable switch is closed, the second controllable switch is controlled to close for a second time and then open. The second controllable switch is opened when the inductor is directly connected between the input and output terminals of the converter. The first controllable switch is delayed for a third time after the second controllable switch is opened, and then closes again.

[0055] The first voltage detection unit proposed in this application controls the charging and discharging states of the third and fourth capacitors through the switching action of the first controllable switch. It also samples the voltage across the inductor using the third and fourth resistors and holds the sampling results through the fifth and sixth capacitors. This enables accurate detection of the voltage across the inductor and yields the corresponding first and second voltage detection values. This helps to improve the accuracy of the converter mode switching point by using the first and second voltage detection values. Furthermore, the active control of the charging and discharging of the third and fourth capacitors through the second controllable switch shortens the delay time and improves the detection efficiency.

[0056] Optionally, in some embodiments of this application, the first voltage detection unit further includes:

[0057] The second differential amplifier has its positive input terminal connected to the fifth node and its negative input terminal connected to the sixth node. The output terminal of the second differential amplifier is used to output the difference between the first voltage detection value and the second voltage detection value.

[0058] In this embodiment, a second differential amplifier is used to accurately calculate and stably output the difference between the first voltage detection value and the second voltage detection value, so as to obtain an accurate detection result of the difference between the input voltage and the output voltage of the converter. This helps the mode control circuit to improve the accuracy of the converter mode switching point by using the detection result output by the second differential amplifier.

[0059] Optionally, in some embodiments of this application, the first voltage detection unit further includes:

[0060] A third controllable switch has its first terminal connected to the input terminal of the converter, its second terminal connected to the output terminal of the converter, its third terminal connected to the fifth node, and its fourth terminal connected to the sixth node. When the third controllable switch is closed and the first controllable switch is open, the first voltage detection value output by the fifth node is the input voltage of the converter, and the second voltage detection value output by the sixth node is the output voltage of the converter.

[0061] Optionally, in some embodiments of this application, the first voltage detection unit is further configured to control the third controllable switch to close and the first controllable switch to open when the absolute value of the difference between the input voltage and the output voltage of the converter is greater than a preset voltage threshold, or when the converter is in standby mode or light-load high-efficiency mode.

[0062] In this embodiment, a third controllable switch is provided in the first voltage detection unit. When the difference between the input voltage and the output voltage of the converter is too large, or when the converter is in standby mode or light-load high-efficiency mode, the third controllable switch is closed and the first controllable switch is opened to ensure effective detection of the mode control circuit. This ensures that the mode control circuit can achieve accurate working mode switching under special conditions. Therefore, the setting of the third controllable switch improves the adaptability of the mode control circuit under special conditions.

[0063] Optionally, in some embodiments of this application, the control unit includes:

[0064] A first subtractor is configured to subtract the voltage drop from the difference between the first voltage detection value and the second voltage detection value to obtain a first calculated value;

[0065] A first hysteresis comparator is configured to compare the first calculated value with a first reference value to determine whether the converter has exited the buck mode.

[0066] This embodiment uses a first subtractor and a first hysteresis comparator to compare the difference between the first voltage detection value and the second voltage detection value, the voltage drop, and the magnitude relationship between relevant reference values. Based on the comparison result, it controls whether the converter exits the buck mode. The hysteresis effect of the first hysteresis comparator avoids frequent switching of the converter in buck mode, thereby improving the stability of the converter.

[0067] Optionally, in some embodiments of this application, the control unit further includes:

[0068] A second subtractor is configured to subtract the voltage drop from the difference between the first voltage detection value and the second voltage detection value to obtain a second calculated value;

[0069] A second hysteresis comparator is configured to compare the second calculated value with a second reference value to determine whether the converter has exited the boost mode.

[0070] This embodiment uses a second subtractor and a second hysteresis comparator to compare the difference between the first and second voltage detection values, the voltage drop, and the magnitude relationship between relevant reference values. Based on the comparison result, it controls whether the converter exits the boost mode. The hysteresis effect of the second hysteresis comparator avoids frequent switching of the converter in boost mode, thereby improving the stability of the converter.

[0071] Optionally, in some embodiments of this application, the control unit further includes:

[0072] A first adder is configured to add the voltage drop, the second voltage detection value, and the first reference value to obtain a third calculated value;

[0073] A third hysteresis comparator is configured to compare the third calculated value with the first voltage detection value to determine whether the converter has exited the buck mode.

[0074] This embodiment compares the magnitudes of the inductor voltage drop, the first voltage detection value, the second voltage detection value, and related reference values ​​using a first adder and a third hysteresis comparator. Based on the comparison result, it controls whether the converter exits buck mode. The hysteresis effect of the third hysteresis comparator avoids frequent switching of the converter in buck mode, thereby improving the stability of the converter.

[0075] Optionally, in some embodiments of this application, the control unit further includes:

[0076] A second adder is configured to add the voltage drop and the second voltage detection value to obtain a fourth calculated value;

[0077] A third adder is configured to add the first voltage detection value and the second reference value to obtain a fifth calculated value;

[0078] A fourth hysteresis comparator is configured to compare the fourth calculated value with the fifth calculated value to determine whether the converter has exited the boost mode.

[0079] This application embodiment uses a second adder, a third adder, and a fourth hysteresis comparator to compare the magnitude relationship between the inductor voltage drop, the first voltage detection value, the second voltage detection value, and related reference values. Based on the comparison result, it controls whether the converter exits the boost mode. The hysteresis effect of the fourth hysteresis comparator avoids frequent switching of the converter in boost mode, thereby improving the stability of the converter.

[0080] Secondly, embodiments of this application provide a converter, including:

[0081] inductance;

[0082] At least one switching transistor;

[0083] The mode control circuit according to the above embodiments.

[0084] The converter proposed in this application uses a mode control circuit to monitor the voltage difference across the inductor in real time during charging and discharging, and controls the converter's operating mode based on the monitoring results, achieving precise switching between boost and buck modes. Therefore, compared to the traditional method of directly using the relationship between input and output voltages for mode switching, this application's mode control circuit accurately detects the difference between the converter's input and output voltages, effectively eliminating the influence of circuit impedance changes such as the switching of transistors on mode switching. This significantly improves the accuracy of mode switching point determination, contributing to balanced converter stability and efficiency, and enhancing the converter's buck-boost performance.

[0085] Optionally, in some embodiments of this application, the converter is a boost converter, a buck converter, or a buck-boost converter. Attached Figure Description

[0086] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0087] Figure 1 This is a circuit diagram of a converter in related technologies;

[0088] Figure 2This is a schematic diagram of the mode control circuit of a converter according to one embodiment of this application;

[0089] Figure 3 This is a schematic diagram of the mode control circuit of a converter according to another embodiment of this application;

[0090] Figure 4 This is a circuit diagram of the second voltage detection unit proposed in an embodiment of this application;

[0091] Figure 5 This is a circuit diagram of a first voltage detection unit according to an embodiment of this application;

[0092] Figure 6 A circuit diagram of a first voltage detection unit according to another embodiment of this application;

[0093] Figure 7 This is a circuit diagram of a control unit proposed in one embodiment of this application;

[0094] Figure 8 This is a circuit diagram of a control unit according to another embodiment of this application;

[0095] Figure 9 This is a circuit diagram of a control unit according to yet another embodiment of this application;

[0096] Figure 10 A circuit diagram of the control unit proposed in one embodiment of this application is also provided;

[0097] Figure 11 This is a schematic diagram of the converter proposed in the embodiments of this application. Detailed Implementation

[0098] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0099] Switching converters, as important components widely used in power supply circuits, can regulate the output voltage to be lower or higher than the input voltage. In related technologies, the circuit topology of a positive voltage output buck-boost switching converter is as follows: Figure 1 As shown, the buck-boost switching converter consists of switching transistors Q1, Q2, Q3, and Q4, an inductor L, and an output capacitor C. The output voltage can be regulated by controlling the duty cycle of the four switching transistors.

[0100] The buck-boost switching converter typically has the following operating modes:

[0101] At input voltage V IN Significantly higher than the output voltage V OUT In this case, a buck operating mode is adopted. In buck operating mode, switching transistor Q4 remains on and switching transistor Q3 remains off. The output voltage V is adjusted by regulating the duty cycle of switching transistor Q1. OUT Furthermore, the switching states of switch Q2 and switch Q1 are complementary;

[0102] At input voltage V IN Significantly lower than the output voltage V OUT In this case, a boost mode is adopted. In boost mode, switching transistor Q1 remains on and switching transistor Q2 remains off. The output voltage V is adjusted by regulating the duty cycle of switching transistor Q3. OUT Furthermore, the switching states of switch Q4 and switch Q3 are complementary.

[0103] These operating modes enable buck-boost switching converters to maintain a stable output voltage under different input voltage conditions. However, due to the non-ideal characteristics of the devices, there are signal jumps during the transition between the above operating modes. Generally, nonlinear control is needed to improve the smoothness of the mode switching process. Nonlinear control can effectively smooth the mode switching process, and the use of nonlinear control is to determine which operating mode the converter should be in and when mode switching is required.

[0104] In related technologies, the relationship between input voltage and output voltage is generally used to control the switching mode. However, due to the complex circuit structure of the converter, the direct use of input voltage and output voltage is easily affected by load current, switching transistor on-resistance and inductor on-resistance. For example, for buck mode, the inductor current rise slope of switching transistor Q1 during the turn-on phase is shown in the following formula (1):

[0105]

[0106] In the formula, V represents the rising slope of the inductor current mentioned above. IN V is the input voltage. OUT For the output voltage, I L R is the inductor current, L is the inductance value, and R is the inductor current. ESR R is the equivalent series resistance (ESR) of the inductor. dsQ1 R is the on-resistance of the switching transistor Q1. dsQ4 This is the on-resistance of the switching transistor Q4.

[0107] To ensure that the inductor current reaches this rising slope within the required time, the input voltage must meet the requirements of the following formula (2):

[0108] V IN -I L ×(R dsQ1 +R dsQ4 +R ESR )-V OUT >V TH Formula (2)

[0109] In the formula, V TH This is a preset limit voltage.

[0110] Therefore, the converter needs to be able to operate at an input voltage V IN Less than I L ×(R dsQ1 +R dsQ4 +R ESR )+V OUT +V TH Then it exits the buck mode. This shows that directly using the relationship between input and output voltage to determine whether to switch modes has low accuracy, making it difficult to effectively switch the converter's operating modes and thus affecting the converter's buck-boost performance.

[0111] Alternatively, duty cycle can be used as a criterion for mode switching in related technologies. However, this method is easily affected by the converter's operating state and makes it difficult to accurately determine the timing of mode switching. For example, during converter startup and dynamic load changes, the duty cycle changes rapidly, which may lead to false triggering of mode switching. Furthermore, when the converter operates at reduced frequency under light load, the duty cycle is relatively small, which can also lead to incorrect mode switching detection.

[0112] This application provides a mode control circuit 100 for a converter, which can be applied to power supply devices with voltage conversion functions, such as converters and chargers. Figure 2 As shown, the mode control circuit 100 includes an inductor L1, wherein the first end of the inductor L1 is adapted to be connected to the input terminal of the converter, and the second end of the inductor L1 is adapted to be connected to the output terminal of the converter. The mode control circuit 100 includes a first voltage detection unit 110 and a control unit 120.

[0113] The first detection terminal SW1 of the first voltage detection unit 110 is connected to the first terminal of the inductor L1, and the second detection terminal SW2 of the first voltage detection unit 100 is connected to the second terminal of the inductor L1. The first voltage detection unit 110 is configured to detect and hold the voltage across the inductor L1 to obtain a first voltage detection value V. SW1_SAM Second voltage detection value VSW2_SAM Among them, the first voltage detection value V SW1_SAM With the second voltage detection value V SW2_SAM The difference V between SW1_SW2 Used to characterize the input voltage V of the converter IN With the output voltage V of the converter OUT difference.

[0114] Control unit 120 is configured to base on first voltage detection value V SW1_SAM With the second voltage detection value V SW2_SAM The difference V between SW1_SW2 The operating mode of the control converter includes at least one of boost mode, buck mode, and buck-boost mode.

[0115] The mode control circuit 100 proposed in this application embodiment uses the first voltage detection value V detected by the first voltage detection unit 110. SW1_SAM With the second voltage detection V SW2_SAM The difference V between SW1_SW2 This enables real-time monitoring of the voltage difference across inductor L1 during charging and discharging. The control unit 120 outputs a mode signal based on the real-time monitoring results to control the converter's operating mode, achieving precise switching between boost mode and buck mode.

[0116] Specifically, in the aforementioned first voltage detection value V SW1_SAM With the second voltage detection V SW2_SAM If the difference is greater than the first preset voltage value, the control unit 120 controls the converter 10 to switch its operating mode to buck mode. SW2_SAM With the first voltage detection value V SW1_SAM If the difference is less than the second preset voltage value, the control unit 120 controls the converter 10 to switch the working mode to boost mode.

[0117] Therefore, this embodiment does not directly detect the voltage at the input and output terminals of the converter, but rather detects the voltage at the first detection terminal SW1 and the second detection terminal SW2 across the inductor L1. This effectively eliminates the influence of circuit impedance changes such as the switching of the switching transistor on the converter's mode switching, achieving accurate detection of the difference between the input and output voltages of the converter. This greatly improves the accuracy of determining the mode switching point, which is beneficial for balancing the stability and efficiency of the converter and improving its buck-boost performance. In some embodiments of this application, the first voltage detection unit 110 is also configured to detect the voltage across the inductor L1 when it is directly connected to the input and output terminals of the converter.

[0118] Furthermore, the aforementioned first voltage detection unit 110 is also configured to perform voltage holding operation when the inductor L1 is not directly connected between the input and output terminals of the converter; and to perform voltage detection operation when the inductor L1 is directly connected between the input and output terminals of the converter.

[0119] When inductor L1 is directly connected between the input and output terminals of the converter, i.e., both switching transistors Q1 and Q4 are simultaneously on, the first voltage detection unit 110 charges for a period of time to perform voltage detection and obtain the detection voltages at the first detection terminal SW1 and the second detection terminal SW2. When inductor L1 is not directly connected between the input and output terminals of the converter, i.e., at least one of switching transistors Q1 and Q4 is off, the first voltage detection unit 110 performs voltage holding operation.

[0120] Therefore, by setting the voltage holding and voltage detection operation processes of the first voltage detection unit 110, this embodiment of the application can effectively suppress the interference of the switching action of the switching transistor in the converter on the voltage detection, improve the accuracy of the voltage detection result of the first voltage detection unit 100 on the two ends of the inductor L1, and thus obtain a reliable and accurate voltage detection value.

[0121] Specifically, in this embodiment of the application, the first voltage detection unit 110 is further configured to delay for a first time after entering the state where the inductor L1 is directly connected to the input and output terminals of the converter, and then perform voltage detection, and to continuously perform the voltage holding operation within the first time.

[0122] This embodiment of the application delays the voltage detection process at the first moment to ensure that the voltage rises to meet the detection requirements, thereby ensuring that the first detection unit can effectively detect the voltage across the inductor and improving the accuracy of voltage detection.

[0123] In some embodiments of this application, such as Figure 3As shown, the above-mentioned mode control circuit 100 also includes a second voltage detection unit 130, wherein the first detection terminal SW1 of the second voltage detection unit 130 is connected to the first terminal of the inductor L1, the second detection terminal SW2 of the second voltage detection unit 130 is connected to the second terminal of the inductor L1, and the second voltage detection unit 130 is configured to detect the voltage drop generated by the parasitic resistance of the inductor L1 and send the voltage drop to the control unit 120.

[0124] This application embodiment enables real-time detection of the voltage drop generated by the parasitic resistance of inductor L1, i.e., the equivalent series resistance (ESR), by setting a second voltage detection unit 130. This eliminates the influence of the inductor's voltage drop on the converter's mode switching, thereby further improving the accuracy of the converter's mode switching point.

[0125] In some embodiments of this application, such as Figure 4 As shown, the second voltage detection unit 130 includes a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, and a first differential amplifier U1. One end of the first resistor R1 is connected to the first terminal SW1 of the inductor L1; one end of the second resistor R2 is connected to the second terminal SW2 of the inductor L1; one end of the first capacitor C1 is connected to the other end of the first resistor R1 and has a first node; the other end of the first capacitor C1 is grounded; one end of the second capacitor C2 is connected to the other end of the second resistor R2 and has a second node; the other end of the second capacitor C2 is grounded; the positive input terminal of the first differential amplifier U1 is connected to the first node; the negative input terminal of the first differential amplifier U1 is connected to the second node; and the output terminal of the first differential amplifier U1 is used to output the voltage drop V. ESR .

[0126] It should be noted that, Figure 4 The inductance L' of inductor L1 and the equivalent series resistance R of inductor L1 are shown. ESR In fact, the inductance L' and the equivalent series resistance R ESR As a whole, it represents inductor L1.

[0127] In some embodiments of this application, R1 = R2 and C1 = C2 can be selected, and the resistor and capacitor satisfy the following formula (3):

[0128]

[0129] The output voltage of the first differential amplifier U1 is related to the parasitic resistance R of the inductor. ESR The resulting voltage drop is completely in phase.

[0130] This embodiment utilizes a circuit structure composed of resistors and capacitors to realize the voltage sampling and holding function of the second voltage detection unit 130. It also combines the first differential amplifier U1 to calculate the voltage difference between the first node and the second node, thereby achieving accurate calculation and stable output of the voltage drop detection result. This helps the control unit 120 utilize the detection result V output by the first differential amplifier U1. ESR Improve the accuracy of converter mode switching points.

[0131] In some embodiments of this application, such as Figure 5 As shown, the first voltage detection unit 110 includes a third resistor R3, a fourth resistor R4, a third capacitor C3, a fourth capacitor C4, a first controllable switch S1, a fifth capacitor C5, and a sixth capacitor C6. One end of the third resistor R3 is connected to the first terminal SW1 of the inductor L1; one end of the fourth resistor R4 is connected to the second terminal SW2 of the inductor L1; one end of the third capacitor C3 is connected to the other end of the third resistor R3 and has a third node; the other end of the third capacitor C3 is grounded; one end of the fourth capacitor C4 is connected to the other end of the fourth resistor R4 and has a fourth node; the other end of the fourth capacitor C4 is grounded; the first terminal of the first controllable switch S1 is connected to the third node; the second terminal of the first controllable switch S1 is connected to the fourth node; one end of the fifth capacitor C5 is connected to the third terminal of the first controllable switch S1 and has a fifth node; the other end of the fifth capacitor C5 is grounded; one end of the sixth capacitor C6 is connected to the fourth terminal of the first controllable switch S1 and has a sixth node; the other end of the sixth capacitor C6 is grounded.

[0132] The fifth node mentioned above is used to output the first voltage detection value V. SW1_SAM The sixth node mentioned above is used to output the second voltage detection value V. SW2_SAM .

[0133] Furthermore, in some embodiments of this application, the voltage detection and voltage holding processes of the first voltage detection unit 110 are specifically described as follows:

[0134] When the inductor L1 is not directly connected between the input and output terminals of the converter, that is, when at least one of the converter's switching transistors Q1 and Q4 is in the off state, the first controllable switch S1 is opened and the first voltage detection unit 110 performs voltage holding operation.

[0135] When inductor L1 is directly connected between the input and output terminals of the converter, that is, when the converter's switching transistors Q1 and Q4 are simultaneously in the on state, the first controllable switch S1 is closed, and the first voltage detection unit 110 performs voltage detection.

[0136] It should be noted that in some embodiments of this application, the first controllable switch S1 is delayed in closing after both switch Q1 and switch Q4 are turned on, so as to ensure that the voltages of the third capacitor C3 and the fourth capacitor C4 rise to meet the detection requirements when the first controllable switch S1 is closed.

[0137] In some other embodiments of this application, the first voltage detection unit 110 further includes a second controllable switch S2, the first end of the second controllable switch S2 is connected to the third node, the second end of the second controllable switch S2 is connected to the fourth node, and the third and fourth ends of the second controllable switch S2 are connected and then grounded.

[0138] By setting the second controllable switch S2, the charging and discharging of the third capacitor C3 and the fourth capacitor C4 can be actively controlled, thereby shortening the delay time and improving the voltage detection efficiency.

[0139] Specifically, the first voltage detection unit 110 is configured as follows:

[0140] Before the first controllable switch S1 is closed, the second controllable switch S2 is closed for a second time and then opened. The second controllable switch S2 is opened when the inductor L1 is directly connected between the input and output terminals of the converter. The first controllable switch S1 is closed after a third time delay after the second controllable switch S2 is opened.

[0141] In this embodiment, the second controllable switch S2 is closed at a second time to actively control the discharge of the third capacitor C3 and the fourth capacitor C4. It should be noted that the second controllable switch S2 can be closed at the moment when both switching transistors Q1 and Q4 start to conduct, or at any time when at least one of switching transistors Q1 and Q4 is in the off state.

[0142] Furthermore, in this embodiment, the first controllable switch S1 is set to close after a third time following the opening of the second controllable switch S2. This ensures that the third capacitor C3 and the fourth capacitor C4 can maintain a charging state for a period of time, thereby ensuring that the voltage of the third capacitor C3 and the fourth capacitor C4 rises to meet the detection requirements before closing the first controllable switch S1 for voltage detection.

[0143] For example, when the second controllable switch S2 is closed and the first controllable switch S1 is open, the third capacitor C3 and the fourth capacitor C4 are in a discharging state and are discharged to zero level, while the fifth capacitor C5 and the sixth capacitor C6 maintain the sampling voltage of the previous detection cycle.

[0144] After the second time period, the second controllable switch S2 is opened, while the first controllable switch S1 remains open. At this time, the third capacitor C3 and the fourth capacitor C4 are in a charging state, and the charging time constant is R3*C3. In this embodiment, the duration for which the first controllable switch S1 and the second controllable switch S2 remain open can be set to more than 4 times the charging time constant, that is, the duration is at least 4*R3*C3.

[0145] After a third period, the second controllable switch S2 remains open, the first controllable switch S1 closes, and the first voltage detection unit 110 performs voltage detection. Since the first controllable switch S1 is closed, the voltage across the fifth capacitor C5 is equal to the voltage across the third capacitor C3, and the voltage across the sixth capacitor C6 is equal to the voltage across the fourth capacitor C4. Therefore, the detected first voltage value V... SW1_SAM Second voltage detection value V SW2_SAM As shown in the following formulas (4) and (5):

[0146] V SW1_SAM =V IN -I L ×R dsQ1 Formula (4)

[0147] V SW2_SAM =V OUT +I L ×R dsQ4 Formula (5)

[0148] In the formula, V IN V is the input voltage of the converter. OUT I is the output voltage of the converter. L R is the inductor current. dsQ1 R is the on-resistance of the switching transistor Q1. dsQ4 This is the on-resistance of the switching transistor Q4. It should be noted that... Figure 5 In the circuit structure of the first voltage detection unit shown, since the resistance values ​​of the third resistor R3 and the fourth resistor R4 are very small, their voltage division effect can be ignored.

[0149] Furthermore, since parasitic inductance and capacitance are unavoidable in actual circuits, these parasitic inductance and capacitance will cause non-ideal behavior at the first terminal SW1 and the second terminal SW2. Therefore, in Figure 5 In the circuit structure shown, the third resistor R3, the third capacitor C3, the fourth resistor R4, and the fourth capacitor C4 can suppress the high-frequency power supply oscillation at the first terminal SW1 and the second terminal SW2 after the switching transistor in the converter is turned on and off.

[0150] Subsequently, with the second controllable switch S2 open and the first controllable switch S1 open, the first voltage detection unit 110 performs voltage holding operation. Since the first controllable switch S1 is open, the fifth capacitor C5 and the sixth capacitor C6 maintain the voltage at the time of the first controllable switch S1 until the next detection cycle.

[0151] The first voltage detection unit 110 proposed in this embodiment controls the charging and discharging states of the third capacitor C3 and the fourth capacitor C4 by coordinating the on / off actions of the first controllable switch S1 and the second controllable switch S2. It also samples the voltage across the inductor L1 using the third resistor R3 and the fourth resistor R4, and holds the sampling results using the fifth capacitor C5 and the sixth capacitor C6. This allows for accurate detection of the voltage across the inductor L2 and the acquisition of the corresponding first voltage detection value V. SW1_SAM Second voltage detection value V SW2_SAM This will help in the subsequent use of the first voltage detection value V SW1_SAM Second voltage detection value V SW2_SAM Improve the accuracy of converter mode switching points.

[0152] In some embodiments of this application, such as Figure 5 As shown, the first voltage detection unit 110 also includes a second differential amplifier U2, wherein the positive input terminal of the second differential amplifier U2 is connected to the fifth node, the negative input terminal of the second differential amplifier U2 is connected to the sixth node, and the output terminal of the second differential amplifier U2 is used to output the first voltage detection value V. SW1 SAM With the second voltage detection value V SW2_SAM The difference V between SW1_SW2 .

[0153] The first voltage detection value V is calculated using the second differential amplifier U2. SW1_SAM With the second voltage detection value V SW2_SAM The difference V between SW1_SW2 Therefore, the output voltage of the second differential amplifier U2 is as shown in the following formula (6):

[0154] V SW1_SAM =V IN -V OUT -I L ×R dsQ1 -I L ×R dsQ4 Formula (6)

[0155] Therefore, it can be seen that in this embodiment, the first voltage detection value V is detected by the second differential amplifier U2. SW1_SAM Second voltage detection value V SW2_SAMThe difference between the input and output voltages is accurately calculated and output stably. Compared to directly using the relationship between the input and output voltages for mode switching, the difference V output by the first voltage detection unit 110 is more accurate. SW1_SW2 It can more accurately characterize the difference between the input and output voltages of the converter, thus providing a more accurate basis for determining the mode switching point and effectively eliminating the influence of circuit impedance changes such as the on / off state of the switching transistor on the converter mode switching.

[0156] In one embodiment of this application, the voltage across the inductor L1 is detected by the first voltage detection unit 110, and the control unit 120 controls the buck-boost mode switching of the converter according to the detection result.

[0157] Specifically, in some embodiments of this application, the control unit 120 is further configured to,

[0158] First voltage detection value V SW1_SAM With the second voltage detection value V SW2_SAM The difference between them is less than the first reference value V. REF1 In the event that the converter exits buck mode, that is, when the detection result of the first voltage detection unit 110 satisfies the following formula (7), the control unit 120 will control the converter to exit BUCK Mode:

[0159] V SW1_SAM -V SW2_SAM <V REF1 Formula (7)

[0160] First voltage detection value V SW1_SAM With the second voltage detection value V SW2_SAM The difference between them is greater than the first reference value V. REF1 With the first preset threshold V TH1 When the sum of the values ​​is satisfied, the control unit 120 will control the converter to enter buck mode, that is, when the detection result of the first voltage detection unit 110 satisfies the following formula (8), the control unit 120 will control the converter to enter BUCK mode:

[0161] V SW1_SAM -V SW2_SAM >V REF1 +V TH1 Formula (8)

[0162] First voltage detection value V SW1_SAM With the second voltage detection value V SW2_SAM The negative of the difference between them is less than the second reference value V. REF2In the event that the converter exits boost mode, that is, when the detection result of the first voltage detection unit 110 satisfies the following formula (9), the control unit 120 will control the converter to exit BOOST Mode:

[0163] V SW2_SAM -V SW1_SAM >V REF2 Formula (9)

[0164] First voltage detection value V SW1_SAM With the second voltage detection value V SW2_SAM If the negative of the difference between the two values ​​is greater than the sum of the second reference value and the second preset threshold, the converter is controlled to enter boost mode. That is, if the detection result of the first voltage detection unit 110 satisfies the following formula (10), the control unit 120 will control the converter to enter BOOST Mode:

[0165] V SW2_SAM -V SW1_SAM >V REF2 +V TH2 Formula (10)

[0166] Therefore, in this embodiment, the control unit uses the comparison result between the voltage difference across the inductor, a relevant reference value, and a preset threshold as the judgment condition for switching the converter's operating mode, thereby precisely controlling the switching of the converter's operating mode. Compared with the traditional method of directly switching modes based on the relationship between input and output voltages, the mode control circuit proposed in this embodiment can effectively eliminate the interference of circuit impedance changes caused by the on-resistance of the switching transistor on the operating mode switching, greatly improving the accuracy of determining the mode switching point, thus enabling the converter to switch efficiently between boost and buck modes, and improving the converter's buck-boost performance.

[0167] In other embodiments of this application, the voltage across the inductor L1 is detected by the first voltage detection unit 110, and the voltage drop V generated by the parasitic resistance of the inductor L1 is detected by the second voltage detection unit 120. ESR This eliminates the impact of voltage drop caused by inductor parasitic resistance on converter mode switching, thereby further improving the accuracy of converter mode switching point.

[0168] Specifically, in some other embodiments of this application, the mode control process of the control unit 120 for the converter is as follows:

[0169] First voltage detection value V SW1_SAM With the second voltage detection value V SW2_SAM The difference between them and the pressure drop V ESR The difference is less than the first reference value V REF1When the sum of the values ​​of the first voltage detection unit 110 and the second detection unit 130 satisfies the following formula (11), the control unit 120 will control the converter to exit BUCK Mode.

[0170] V SW1_SW2 -V ESR = V IN -V OUT -I L ×(R dsQ1 +R dsQ4 +R ESR ) <V REF1 Formula (11)

[0171] First voltage detection value V SW1_SAM With the second voltage detection value V SW2_SAM The difference between them and the pressure drop V ESR The difference is greater than the first reference value V REF1 With the first preset threshold V TH1 When the sum of the values ​​of the first voltage detection unit 110 and the second detection unit 130 satisfies the following formula (12), the control unit 120 will control the converter to enter BUCK Mode:

[0172] V SW1_sW2 -V ESR =V IN -V OUT -I L ×(R dsQ1 +R dsQ4 +R ESR )>V REF1 +V TH1 Formula (12)

[0173] At pressure drop V ESR With the first voltage detection value V SW1_SAM With the second voltage detection value V SW2_SAM The difference V between SW1_SW2 The difference is less than the second reference value V REF2 In the event that the converter exits the boost mode, that is, when the detection results of the first voltage detection unit 110 and the second detection unit 130 satisfy the following formula (13), the control unit 120 will control the converter to exit the boost mode:

[0174] V ESR -V SW1_SW2 =V OUT +I L×(R dsQ1 +R dsQ4 +R ESR )-V IN <V REF2 Formula (13)

[0175] At pressure drop V ESR With the first voltage detection value V SW1_SAM With the second voltage detection value V SW2_SAM The difference V between SW1_SW2 The difference is greater than the second reference value V REF2 With the second preset threshold V TH2 When the sum of the results of the first voltage detection unit 110 and the second detection unit 130 satisfies the following formula (14), the control unit 120 will control the converter to exit BOOST Mode:

[0176] V ESR -V SW1_SW2 =V OUT +I L ×(R dsQ1 +R dsQ4 +R ESR )-V IN >V REF2 +V TH2

[0177] Formula (14)

[0178] In this embodiment, the control unit 120 uses the comparison between the voltage difference across inductor L1, voltage drop, relevant reference values, and a preset threshold as the judgment condition for switching the converter's operating mode, thereby precisely controlling the switching of the converter's operating mode. Compared with traditional methods that directly switch modes based on the relationship between input and output voltages, the mode control circuit 100 proposed in this embodiment can effectively eliminate the interference of circuit impedance changes caused by the on-resistance of the switching transistor and the ESR of the inductor on the switching mode, greatly improving the accuracy of determining the mode switching point. This enables the converter to switch efficiently between boost and buck modes, improving the converter's buck-boost performance.

[0179] In some embodiments of this application, such as Figure 6As shown, the first voltage detection unit 110 also includes a third controllable switch S3. The first terminal of the third controllable switch S3 is connected to the input terminal of the converter, the second terminal of the third controllable switch S3 is connected to the output terminal of the converter, the third terminal of the third controllable switch S3 is connected to the fifth node, and the fourth terminal of the third controllable switch S3 is connected to the sixth node. When the third controllable switch S3 is closed and the first controllable switch S1 is open, the first voltage detection value V output by the fifth node... SW1_SAM The input voltage of the converter is the second voltage detection value V at the output of the sixth node. SW2_SAM This is the output voltage of the converter.

[0180] Furthermore, the first voltage detection unit 110 is also configured to control the third controllable switch S3 to close and the first controllable switch S1 to open when the absolute value of the difference between the input voltage and the output voltage of the converter is greater than a preset voltage threshold.

[0181] Furthermore, when the converter is in standby mode or light-load high-efficiency mode, the third controllable switch S3 is closed and the first controllable switch S1 is opened.

[0182] Specifically, the converter may experience some special operating conditions, such as under light-load, high-efficiency operation or standby conditions, where the converter temporarily stops switching. Another example is when the input and output voltages differ significantly, resulting in very short turn-on times for switches Q1 and Q4. The first voltage detection unit 110 needs to perform discharging, charging, voltage detection, and voltage holding operations during the simultaneous conduction of switches Q1 and Q4 to complete the voltage detection. Therefore, the short turn-on time is insufficient for the first detection terminal SW1 and the second detection terminal SW2 to reach a stable state and perform voltage sampling. To address these special operating conditions, this embodiment of the application directly samples the converter's input voltage V by setting a third controllable switch S3. IN and output voltage V OUT This shortens the voltage detection time. It should be noted that under these special operating conditions, the inductor current is very small or the input and output voltages differ greatly. The on-resistance of the switching transistor and the voltage drop across the DC resistance (DCR) of the inductor have little impact on the mode determination and can be ignored here.

[0183] Therefore, in this embodiment, a third controllable switch S3 is provided in the first voltage detection unit. When the difference between the input voltage and the output voltage of the converter is too large, or when the converter is in standby mode or light-load high-efficiency mode, the third controllable switch S3 is closed and the first controllable switch S1 is opened to ensure effective detection of the mode control circuit 100. This ensures that the mode control circuit 100 can achieve accurate working mode switching under special conditions. Therefore, the setting of the third controllable switch S3 improves the adaptability of the mode control circuit 100 under special conditions.

[0184] In some embodiments of this application, if only the detection result of the first voltage detection unit 110 is used to determine whether to exit the buck mode, then the first voltage detection value V is directly set. SW1_SAM With the second voltage detection value V SW2_SAM The difference V between SW1_SAM and the first reference value V REF1 The data is fed into the input of the first hysteresis comparator 122 for comparison.

[0185] In other embodiments of this application, if the detection results of the first voltage detection unit 110 and the second detection unit 130 are used to determine whether to exit the buck mode, then as follows: Figure 7 As shown, the control unit 120 includes a first subtractor 121 and a first hysteresis comparator 122, wherein the first subtractor 121 is configured to subtract a first voltage detection value V SW1_SAM With the second voltage detection value V SW2_SAM The difference V between SW1_SW2 With pressure drop V ESR Subtracting the first calculated value from the first calculated value, the first hysteresis comparator 122 is configured to compare the first calculated value with the first reference value V. REF1 A comparison is made to determine whether the converter has exited buck mode.

[0186] Specifically, the controller 120 is set according to the above formula (11). If the above first calculated value is less than the first reference value V, REF1 Then the first hysteresis comparator 122 outputs a mode signal to exit BUCK Mode.

[0187] Therefore, in this embodiment of the application, the difference V between the voltages across the inductor L1 is calculated using the first subtractor 121 and the first hysteresis comparator 122. SW1_SW2 Pressure drop V ESR The system compares the magnitudes of relevant reference values ​​to determine whether the converter should exit buck mode based on the comparison results. The hysteresis effect of the first hysteresis comparator 122 also prevents the converter from frequently switching between buck modes, thereby improving the stability of the converter.

[0188] In some embodiments of this application, if only the detection result of the first voltage detection unit 110 is used to determine whether to exit the boost mode, then the first voltage detection value V is directly set. SW1_SAM With the second voltage detection value V SW2_SAM The difference V between SW1_SAM Second reference value V REF2 The data is fed into the input of the first hysteresis comparator 124 for comparison.

[0189] In other embodiments of this application, if the detection results of the first voltage detection unit 110 and the second detection unit 130 are used to determine whether to exit the boost mode, then as follows: Figure 8 As shown, the control unit 120 also includes a second subtractor 123 and a second hysteresis comparator 124, wherein the second subtractor 123 is configured to subtract the voltage drop V ESR With the first voltage detection value V SW1_SAM With the second voltage detection value V SW2_SAM The difference V between SW1_SW2 Subtracting the two values ​​yields a second calculated value. The second hysteresis comparator 124 is configured to compare the second calculated value with a second reference value V. REF2 A comparison is made to determine whether the converter has exited boost mode.

[0190] Specifically, the controller 120 is set according to the above formula (13). If the above second calculated value is less than the second reference value V, REF2 Then the second hysteresis comparator 124 outputs a mode signal to exit BOOST Mode.

[0191] Therefore, in this embodiment of the application, the difference V between the voltages across the inductor L1 is calculated using the second subtractor 123 and the second hysteresis comparator 124. SW1_SW2 Pressure drop V ESR The system compares the magnitudes of relevant reference values ​​to determine whether the converter should exit boost mode. Furthermore, the hysteresis effect of the second hysteresis comparator prevents frequent switching between boost and boost modes, thereby improving the converter's stability.

[0192] In some embodiments of this application, such as Figure 9 As shown, the control unit 120 also includes a first adder 125 and a third hysteresis comparator 126, wherein the first adder 125 is configured to convert the voltage drop V... ESR Second voltage detection value V SW2_SAM and the first reference value V REF1 The values ​​are added together to obtain a third calculated value. The third hysteresis comparator 126 is configured to compare the third calculated value with the first voltage detection value V. SW1_SAM A comparison is made to determine whether the converter has exited buck mode.

[0193] Specifically, due to V in the embodiments of this application SW1_SW2 =V SW1_SAM -V SW2_SAM Therefore, the above formula (11) can also be transformed into the following formula (15):

[0194] V SW1_SAM <V REF1 +V SW2_SAM +V ESR Formula (15)

[0195] According to the above formula (15), the controller 120 is set. If the above third calculated value is greater than the first voltage detection value V, SW1_SAM Then the third hysteresis comparator 126 outputs a mode signal to exit BUCK Mode.

[0196] Therefore, in this embodiment of the application, the V of the inductor is adjusted by the first adder 125 and the third hysteresis comparator 126. ESR First voltage detection value V SW1_SAM Second voltage detection value V SW2_SAM The converter compares the magnitudes of relevant reference values ​​to determine whether to exit buck mode based on the comparison results. The hysteresis effect of the third hysteresis comparator 126 also prevents the converter from frequently switching between buck modes, thereby improving the stability of the converter.

[0197] In some embodiments of this application, such as Figure 10 As shown, the control unit 120 also includes a second adder 127, a third adder 128, and a fourth hysteresis comparator 129, wherein the second adder 127 is configured to convert the voltage drop V... ESR Second voltage detection value V SW2_SAM The values ​​are added together to obtain a fourth calculated value; the third adder 128 is configured to add the first voltage detection value V. SW1_SAM Second reference value V REF2 The values ​​are added together to obtain the fifth calculated value; the fourth hysteresis comparator 129 is configured to compare the fourth calculated value with the fifth calculated value to determine whether the converter has exited the boost mode.

[0198] Specifically, due to V in the embodiments of this application SW1_SW2 =V SW1_SAM -V SW2_SAM Therefore, the above formula (11) can be transformed into the following formula (14):

[0199] V ESR +V SW2_SAM <V REF2 +V SW1_SAM Formula (14)

[0200] The controller 120 is set according to the above formula (14). If the above fourth calculated value is less than the above fifth calculated value, the third hysteresis comparator 126 outputs a mode signal to exit BOOST Mode.

[0201] Therefore, in this embodiment of the application, the voltage drop V of the inductor is controlled by the second adder 127, the third adder 128, and the fourth hysteresis comparator 129. ESR First voltage detection value V SW1_SAM Second voltage detection value V SW2_SAM The comparison is performed between the relevant reference values ​​to control whether the converter exits the boost mode based on the comparison result. The hysteresis effect of the fourth hysteresis comparator 129 is used to avoid frequent switching of the converter in the boost mode, thereby improving the stability of the converter.

[0202] Accordingly, such as Figure 11 As shown, this application embodiment provides a converter 10, which includes an inductor L1, at least one switching transistor, and a mode control circuit 100 according to the above embodiment.

[0203] In some embodiments of this application, the converter 10 is a boost converter, a buck converter, or a buck-boost converter.

[0204] The converter 10 includes switching transistors Q1, Q2, Q3, and Q4. If the converter is a boost converter, switching transistor Q1 remains on, switching transistor Q2 remains off, and the output voltage V is adjusted by regulating the duty cycle of switching transistor Q3. OUT Furthermore, the switching states of transistors Q4 and Q3 are complementary. If the converter is a buck converter, transistor Q4 remains on, while transistor Q3 remains off. The output voltage V is adjusted by regulating the duty cycle of transistor Q1. OUT Furthermore, the switching states of switch Q2 and switch Q1 are complementary.

[0205] Therefore, the converter 10 proposed in this application embodiment monitors the voltage difference across the inductor L1 in real time during charging and discharging through a mode control circuit, and controls the operating mode of the converter 10 based on the real-time monitoring results, thereby achieving precise switching between boost mode and buck mode. Therefore, compared to the traditional method of directly using the relationship between input and output voltages for mode switching, this application embodiment achieves accurate detection of the difference between the input and output voltages of the converter 10 through the aforementioned mode control circuit 100. This effectively eliminates the influence of circuit impedance changes such as the on / off state of the switching transistors on the converter's mode switching, greatly improving the accuracy of determining the mode switching point, which is beneficial for balancing the converter's stability and operating efficiency, and improving the converter's buck-boost effect.

[0206] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0207] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0208] It should be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0209] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0210] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

[0211] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A mode control circuit for a converter, characterized in that, The converter includes an inductor, a first end of which is adapted to be connected to the input terminal of the converter, and a second end of which is adapted to be connected to the output terminal of the converter. The mode control circuit includes: A first voltage detection unit is configured to detect and hold the voltage across the inductor to obtain a first voltage detection value and a second voltage detection value. The difference between the first voltage detection value and the second voltage detection value is used to characterize the difference between the input voltage and the output voltage of the converter. A control unit is configured to control the operating mode of the converter based on the difference between the first voltage detection value and the second voltage detection value, wherein the operating mode of the converter includes at least one of a boost mode, a buck mode, and a buck-boost mode.

2. The mode control circuit according to claim 1, characterized in that, The first voltage detection unit is also configured to detect the voltage across the inductor when the inductor is directly connected to the input and output terminals of the converter.

3. The mode control circuit according to claim 1, characterized in that, The first voltage detection unit is also configured to... When the inductor is not directly connected between the input and output terminals of the converter, voltage holding is performed; Voltage detection is performed when the inductor is directly connected between the input and output terminals of the converter.

4. The mode control circuit according to claim 3, characterized in that, The first voltage detection unit is further configured to delay the voltage detection operation for a first time after entering the state where the inductor is directly connected to the input and output terminals of the converter, and to continuously perform the voltage holding operation during the first time.

5. The mode control circuit according to claim 1, characterized in that, The control unit is also configured to, If the difference between the first voltage detection value and the second voltage detection value is less than the first reference value, the converter is controlled to exit the buck mode; If the difference between the first voltage detection value and the second voltage detection value is greater than the sum of the first reference value and the first preset threshold, the converter is controlled to enter the buck mode.

6. The mode control circuit according to claim 1, characterized in that, The control unit is also configured to, If the negative of the difference between the first voltage detection value and the second voltage detection value is less than the second reference value, the converter is controlled to exit the boost mode; If the negative of the difference between the first voltage detection value and the second voltage detection value is greater than the sum of the second reference value and the second preset threshold, the converter is controlled to enter the boost mode.

7. The mode control circuit according to claim 1 or 2, characterized in that, The mode control circuit further includes: The second voltage detection unit has a first detection terminal connected to the first terminal of the inductor and a second detection terminal connected to the second terminal of the inductor. The second voltage detection unit is configured to detect the voltage drop generated by the parasitic resistance of the inductor and send the voltage drop to the control unit.

8. The mode control circuit according to claim 7, characterized in that, The control unit is also configured to, If the difference between the first voltage detection value and the second voltage detection value and the difference between the voltage drop are less than the first reference value, the converter is controlled to exit the buck mode; If the difference between the first voltage detection value and the second voltage detection value and the difference between the voltage drop are greater than the sum of the first reference value and the first preset threshold, the converter is controlled to enter the buck mode.

9. The mode control circuit according to claim 7, characterized in that, The control unit is also configured to, If the difference between the voltage drop and the difference between the first voltage detection value and the second voltage detection value is less than the second reference value, the converter is controlled to exit the boost mode; If the difference between the voltage drop and the difference between the first voltage detection value and the second voltage detection value is greater than the sum of the second reference value and the second preset threshold, the converter is controlled to enter the boost mode.

10. The mode control circuit according to claim 7, characterized in that, The second voltage detection unit includes: A first resistor, one end of which is connected to the first end of the inductor; A second resistor, one end of which is connected to the second end of the inductor; A first capacitor, one end of which is connected to the other end of the first resistor and has a first node, and the other end of the first capacitor is grounded; The second capacitor has one end connected to the other end of the second resistor and has a second node, and the other end of the second capacitor is grounded. A first differential amplifier is used, with its positive input terminal connected to the first node and its negative input terminal connected to the second node. The output terminal of the first differential amplifier is used to output the voltage drop.

11. The mode control circuit according to claim 1, characterized in that, The first voltage detection unit includes: A third resistor, one end of which is connected to the first end of the inductor; A fourth resistor, one end of which is connected to the second end of the inductor; A third capacitor, one end of which is connected to the other end of the third resistor and has a third node, and the other end of the third capacitor is grounded; A fourth capacitor, one end of which is connected to the other end of the fourth resistor and has a fourth node, and the other end of the fourth capacitor is grounded; A first controllable switch, the first end of which is connected to the third node, and the second end of which is connected to the fourth node; The fifth capacitor has one end connected to the third end of the first controllable switch and has a fifth node, and the other end of the fifth capacitor is grounded. A sixth capacitor, one end of which is connected to the fourth terminal of the first controllable switch and has a sixth node, and the other end of which is grounded; The fifth node is used to output the first voltage detection value, and the sixth node is used to output the second voltage detection value.

12. The mode control circuit according to claim 11, characterized in that, The first voltage detection unit is configured to, When the inductor is not directly connected between the input and output terminals of the converter, the first controllable switch is opened and the first voltage detection unit performs voltage holding operation. When the inductor is directly connected between the input and output terminals of the converter, the first controllable switch is closed, and the first voltage detection unit performs voltage detection.

13. The mode control circuit according to claim 11, characterized in that, The first voltage detection unit further includes: The second controllable switch has its first terminal connected to the third node, its second terminal connected to the fourth node, and its third and fourth terminals connected together and then grounded.

14. The mode control circuit according to claim 13, characterized in that, The first voltage detection unit is configured to, Before the first controllable switch is closed, the second controllable switch is controlled to close for a second time and then open. The second controllable switch is opened when the inductor is directly connected between the input and output terminals of the converter. The first controllable switch is delayed for a third time after the second controllable switch is opened, and then closes again.

15. The mode control circuit according to claim 11, characterized in that, The first voltage detection unit further includes: The second differential amplifier has its positive input terminal connected to the fifth node and its negative input terminal connected to the sixth node. The output terminal of the second differential amplifier is used to output the difference between the first voltage detection value and the second voltage detection value.

16. The mode control circuit according to claim 11, characterized in that, The first voltage detection unit further includes: A third controllable switch has its first terminal connected to the input terminal of the converter, its second terminal connected to the output terminal of the converter, its third terminal connected to the fifth node, and its fourth terminal connected to the sixth node. When the third controllable switch is closed and the first controllable switch is open, the first voltage detection value output by the fifth node is the input voltage of the converter, and the second voltage detection value output by the sixth node is the output voltage of the converter.

17. The mode control circuit according to claim 16, characterized in that, The first voltage detection unit is also configured to... When the absolute value of the difference between the input voltage and the output voltage of the converter is greater than a preset voltage threshold, or when the converter is in standby mode or light-load high-efficiency mode, the third controllable switch is controlled to close and the first controllable switch is controlled to open.

18. The mode control circuit according to claim 7, characterized in that, The control unit includes: A first subtractor is configured to subtract the voltage drop from the difference between the first voltage detection value and the second voltage detection value to obtain a first calculated value; A first hysteresis comparator is configured to compare the first calculated value with a first reference value to determine whether the converter has exited the buck mode.

19. The mode control circuit according to claim 7, characterized in that, The control unit further includes: A second subtractor is configured to subtract the voltage drop from the difference between the first voltage detection value and the second voltage detection value to obtain a second calculated value; A second hysteresis comparator is configured to compare the second calculated value with a second reference value to determine whether the converter has exited the boost mode.

20. The mode control circuit according to claim 7, characterized in that, The control unit further includes: A first adder is configured to add the voltage drop, the second voltage detection value, and the first reference value to obtain a third calculated value; A third hysteresis comparator is configured to compare the third calculated value with the first voltage detection value to determine whether the converter has exited the buck mode.

21. The mode control circuit according to claim 7, characterized in that, The control unit further includes: A second adder is configured to add the voltage drop and the second voltage detection value to obtain a fourth calculated value; A third adder is configured to add the first voltage detection value and the second reference value to obtain a fifth calculated value; A fourth hysteresis comparator is configured to compare the fourth calculated value with the fifth calculated value to determine whether the converter has exited the boost mode.

22. A converter, characterized in that, include: inductance; At least one switching transistor; The mode control circuit according to any one of claims 1-21.

23. The converter according to claim 22, characterized in that, The converter is a boost converter, a buck converter, or a buck-boost converter.

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