Switching mode power amplifier with ideal IQ combination

Abstract

The invention relates to a switched mode power amplifier with ideal IQ combination. An I converter (502) outputs I symbol data and I magnitude data based on received I data. A Q converter (504) outputs Q symbol data and Q magnitude data based on received Q data. An I-clock (404) generates an I-phase based on the I-symbol data. A Q clock (406) generates a Q phase based on the Q symbol data. An I modulator (514) generates an I magnitude pulse stream based on the I magnitude data. A Q modulator (516) generates a Q magnitude pulse stream based on the Q magnitude data. A digital logic component (518) generates an output signal based on the I-phase, the I-magnitude pulse stream, the Q-phase, and the Q-magnitude pulse stream. A power amplifier (526) generates an amplified signal based on the output signal.

Description

[0001] Related information of divisional application

[0002] This application is a divisional application of the patent application with application number 201510726069.7, titled "Switched mode power amplifier with ideal IQ combination", filed on October 30, 2015. TECHNICAL FIELD

[0003] The present disclosure relates generally to power amplifiers, and more particularly to wireless transmitter architectures with switched mode power amplifiers. BACKGROUND

[0004] Wireless applications have rapidly grown into an important market due to the development of wireless devices. The development of low cost complementary metal oxide semiconductor (CMOS) technology has made it a natural choice for radio frequency (RF) transceivers in wireless applications. Its progress has made integration of baseband and other functional blocks possible. CMOS technology will be the most viable solution for fully integrated on a single die to reduce package form factor and its cost. Additionally, due to its mature process technology and high integration, CMOS technology offers good thermal characteristics and low cost advantages. In power amplifiers (PAs), performance issues are output power, efficiency, linearity, yield, and reliability. In constant envelope systems such as global system for mobile communications (GSM), the need for high efficiency performance has taken precedence over extending battery life. For high efficiency operation, non-linear switching PAs are attractive due to their high DC-to-RF conversion efficiency. High efficiency improves the operating time and reliability of radio frequency (RF) transceivers and is one of the most important requirements for PAs for wireless applications.

[0005] The use of high efficiency in non-linear switching CMOS PAs in GSM applications is partly dependent on the fact that the transmitter only propagates phase content, i.e., there is no amplitude content to be propagated. Switching PAs are efficient because they typically drive only two states at the output (although multi-level switching PAs also exist), which represent zero or full supply voltage (V DD ). However, it is highly desirable that such PAs can be used efficiently for analog in-phase and quadrature (I and Q) input data where both phase and amplitude content exist. Currently, there are some techniques for designing these applications, which typically involve different ways of combining I and Q phase and amplitude data into a data stream that can directly modulate a switching mode PA. However, these techniques have drawbacks. One such method to be described involves changing the amplitude and phase content into a single data stream by first converting the IQ data into polar data and then converting the polar data into a single bit delta sigma stream. Using Figure 1 The operation is explained.

[0006] Figure 1A conventional system 100 for converting analog IQ data to modulate a CMOS switching PA is shown.

[0007] System 100 includes converter 102, delta sigma modulator 104, polar amplitude component 106, power component 107, polar phase component 108, and PA 110.

[0008] As shown in the figure, converter 102 is arranged to receive on lines 112 and 114 and output on lines 116, 117, and 118. Delta sigma modulator 104 is arranged to be connected between polar converter 102 via line 118 and polar amplitude component 106 via line 120. Polar amplitude component 106 is then connected to PA 110 via line 124. Polar phase component 108 is arranged to be connected to converter 102 via lines 116 and 117 and to PA 110 via line 122. Power control component 107 interfaces with polar amplitude component 106 via line 121. PA 110 outputs a signal on line 126.

[0009] Converter 102 provides the sampling and filtering functions necessary to convert Cartesian data to polar data. Delta sigma modulator 104 digitizes the analog polar amplitude data into a single bit stream. Polar amplitude component 106 converts the bit stream into a signal for modulating the supply voltage of PA 110, and polar phase component 108 provides the digitization and conversion of the digitized data to drive PA 110.

[0010] In operation, converter 102 converts analog I and Q in Cartesian x, y coordinates to polar coordinates as r (amplitude) and theta (angle). The amplitude information appearing on line 118 is digitized using delta sigma conversion by delta sigma modulator 104. Polar amplitude component 106 then conditions the resulting data stream appearing on line 120, and the output on line 124 modulates the supply to PA 110 by changing the DC bias at PA 110 or by directly changing the supply voltage. The amplitude information is thus encoded into the supply voltage to power amplifier PA 110. The polar phase (angle) information appears as a theta signal on line 116. Polar phase component 122 then digitizes and conditions these signals to drive power amplifier PA 110. Thus, by using Cartesian to polar conversion in conjunction with delta sigma modulation, analog I and Q amplitude information containing amplitude and phase information is used with a CMOS switching mode PA.

[0011] However, this system has some inherent problems. One problem occurs due to the IQ data to polar conversion process. The Cartesian to polar phase angle portion of this conversion process is non-linear (polar angle = tan -1(y / x)), this process significantly widens the bandwidth occupied by the output signal. This results in a need for a much larger channel width, or can result in adjacent channel performance problems. Another problem is that performance is limited due to low supply voltage bandwidth. Thus, while lower bandwidth data applications such as Bluetooth can be supported, high bandwidth data applications such as WiFi cannot be supported.

[0012] A second conventional system and method to convert analog IQ data to modulate a CMOS switched PA is described in U.S. Patent 7,460,612, "Method and apparatus for a fully digital quadrature modulator" by Oren E. Eliezer. This system and method combines I and Q data by using 11-bit I and Q control words applied to a switching array that drives a multi-stage PA operating at four levels representing I+Q, I-Q, -(I-Q), and -(I+Q).

[0013] A first problem is that the implementation requires the use of a multi-stage PA, even if I and Q are implemented independently using a single stage. A second problem is that I to Q leakage manifests as data corruption. The leakage is due to insufficient PA settling time for possibly large data values shifting from zero to (I+Q) in 1 / 4 of a local oscillator (LO) period.

[0014] What is needed is a system and method for combining information in analog I and Q inputs to implement a high efficiency CMOS switched PA that is not limited by the large bandwidth requirements and phase modulation drive performance limitations of the first example conventional system and does not have the multi-stage PA requirements or I to Q leakage corrupting the data problem of the second example conventional system. SUMMARY

[0015] The present invention provides a novel system and method for combining I and Q analog inputs to implement a high efficiency CMOS switched PA that is not limited by the large bandwidth requirements, phase modulation drive performance limitations, and I to Q leakage and data corruption problems of conventional systems.

[0016] Aspects of the present invention are directed to providing a converter to convert analog data streams I and Q into separate magnitude and sign data; providing a local oscillator (LO) to generate a clock having a period T; providing a pulse generator to provide a pulse to gate the magnitude data based on the sign data; providing a delta sigma modulator to generate a bit stream based on the analog magnitude data; providing digital logic to output a single data stream representing combined I and Q data and derived from gated magnitude data with sign information having a determined position in a cycle of the LO; providing a PA to generate an amplified signal based on the output signal such that the Q data is out of phase with the I data.

[0017] Other aspects of the application are directed to additional embodiments that use alternative local oscillator duty cycles and phases to represent I and Q magnitudes and signs.

[0018] Additional advantages and novel features of the present application can be understood from the following description, taken in conjunction with the accompanying drawings, in which: BRIEF DESCRIPTION OF DRAWINGS

[0019] The accompanying drawings incorporated in and forming a part of the specification, illustrate exemplary embodiments of the present application and, together with the description, serve to explain the principles of the application. In the drawings:

[0020] Figure 1 A first conventional system and method to combine analog I and Q data for modulating a CMOS switching PA is shown;

[0021] Figure 2 A general diagram of the basis for converting I and Q data to sign and magnitude according to aspects of the present application;

[0022] Figure 3 A diagram to illustrate the eight possible states of I and Q magnitude and sign;

[0023] Figure 4 A phase selection portion of a system according to aspects of the present application is illustrated;

[0024] Figure 5 A system set up according to aspects of the present application is shown;

[0025] Figure 6 A waveform representing the eight possible IQ states and generated according to aspects of the present application is illustrated; and

[0026] Figure 7 Yet another example embodiment of a phase selector. DETAILED DESCRIPTION

[0027] A first aspect of the present application is directed to setting up a converter to convert an IQ signal to I magnitude, I sign, Q magnitude, and Q sign.

[0028] A second aspect of the present application is directed to setting up an LO to provide a clock with period T, setting up an I pulse generator and a Q pulse generator to generate four pulses of a particular duty cycle of the LO clock (the start times of the pulses are separated by T / 4), and setting up an I phase selector and a Q phase selector to provide strobe pulses based on the pulse generator outputs and the I and Q signs.

[0029] A third aspect of the present invention is directed to setting a Boolean logic gate to gate the IQ magnitude data into four T / 4 slots that make up the LO cycle and combine the magnitude data into a single bit stream based on the phase selector output.

[0030] A fourth aspect of the present invention is directed to setting a high efficiency CMOS switched mode PA to amplify the single bit stream and setting a matching and filtering network to match the network load and filter out of band noise.

[0031] It will be shown how the systems and methods according to aspects of the present invention provide a high efficiency PA solution by combining analog IQ phase and magnitude data into a single bit stream. The single bit stream allows for the use of a simple single stage PA. It will further be explained how such systems and methods have significant advantages over conventional systems and methods as they avoid the bandwidth widening, variable PA response performance limitations, multi-stage PA requirements and I to Q leakage data corruption problems inherent in conventional systems and methods.

[0032] The first aspect of the present invention described above relates to the IQ data conversion concept, reference will be made to Figure 2 The IQ data conversion concept will be explained.

[0033] Figure 2 A diagram 200 showing the basis of converting IQ data into a sign and magnitude according to aspects of the present invention will be shown.

[0034] As shown in the diagram, the diagram 200 includes a waveform 202, a waveform 204, a waveform 206 and a converter 208. The converter 208 is operable to perform delta sigma modulation on its analog input, producing a digital pulse at its output.

[0035] Waveform 202 is an example waveform of an I or Q signal to be processed according to aspects of the present disclosure. Waveform 202 has both portions above and below the zero magnitude and so contains both sign and magnitude. When above zero, the sign is considered positive, and when below zero, the sign is considered negative. In operation according to the present disclosure, waveform 202 is split into a sign portion and a magnitude portion. The sign is illustrated by waveform 204, where the sign is 1 as long as waveform 202 remains above zero, and -1 as long as waveform 202 remains below zero. The sign extraction can be accomplished by several possible conventional methods, non-limiting examples of which include using the IQ signal to drive a two position switch, the two positions representing positive and negative. The magnitude is illustrated by waveform 206, which shows that the magnitude is always zero or positive, regardless of the sign. The magnitude extraction can be accomplished by one of several conventional methods, for example, using full wave rectification. Waveform 204 can be considered "digitized" since it has been a waveform that changes between two states. However, waveform 206 still contains analog variation and so requires digitization performed by converter 208, as illustrated. In operation, converter 208 is a 1-bit delta sigma modulator that converts the analog magnitude signal to a 1-bit digital data stream. Alternatively, 202 can also be a digital stream of data bits.

[0036] Figure 3 To illustrate the eight possible states of the magnitude and sign of I and Q, a polar plot (FIG. 300).

[0037] As shown in the figure, FIG. 300 includes an x-axis 302, a y-axis 304, a vector 306, a vector 308, a vector 310, a vector 312, a vector 314, a vector 316, a vector 318, and a vector 320.

[0038] X-axis 302 represents the I magnitude and Y-axis 304 represents the Q amplitude.

[0039] The vectors of FIG. 300 are the eight possible state combinations of I and Q shown on a constellation plot. Moving clockwise, FIG. 300 shows eight vectors 306, 308, 310, 312, 314, 316, 318, and 320 with polar angles of 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°, respectively. Vector 306 represents the state I = 0, Q = 1, with an amplitude of v. Vector 308 represents the state I = 1, Q = 1, with an amplitude of v√2. Vector 310 represents the state I = 1, Q = 0, with an amplitude of v. Vector 312 represents the state I = 1, Q = -1, with an amplitude of v√2. Vector 314 represents the state I = 0, Q = -1, with an amplitude of v. Vector 316 represents the state I = -1, Q = -1, with an amplitude of v√2. Vector 318 represents the state I = -1, Q = 0, with an amplitude of v. Vector 320 represents the state I = -1, Q = 1, with an amplitude of v√2.

[0040] Figure 4 A system 400 illustrating the phase selection portion of a system according to aspects of the present application.

[0041] Figure 4 The system 400 includes an LO clock 402, a pulse generator 404, a pulse generator 406, a phase selector 408, and a phase selector 410.

[0042] The LO clock 402 is arranged to output a clock signal 412 to both the pulse generator 404 and the pulse generator 406. The LO pulse generator 404 is arranged to output a signal 414 and a signal 416 to the phase selector 408. The LO pulse generator 406 is arranged to output a signal 418 and a signal 420 to the phase selector 410. The phase selector 408 is arranged to input an I symbol signal 424 and output a signal 424, while the phase selector 410 is arranged to input a Q symbol signal 422 and output a signal 428. Alternatively, the blocks 404 and 406 can be replaced by dividers, the input clock of which is twice the LO frequency and outputs four phases with the correlations between 414, 416, 418, and 420 as described above, at the LO frequency.

[0043] The LO clock 402 generates a digital clock with a period T. The LO pulse generator 404 provides a pulse with a width of T / 4. The LO pulse generator 406 also provides a pulse with a width of T / 4. The phase selector 408 provides an A / B multiplexing function based on its selection input. The phase selector 410 also provides an A / B multiplexing function based on its selection input.

[0044] In operation, the main function of the system 400 is to provide gating pulses that will ultimately depend on whether the data is I, Q, positive symbol, negative symbol, or zero, allowing the amplitude data to appear at different portions of the local oscillator clock cycle. In this way, the eight possible states of Figure 3 are encoded into a single data stream.

[0045] The LO clock 412 provides a common clock (clock signal 412) to both LO pulse generators 404 and 406. From the clock signal 412, the pulse generator 404 then generates a 0° pulse (signal 414), i.e., a 1 / 4 wave wide pulse occupying the first 1 / 4 wave period of the LO cycle. The pulse generator 404 also generates a 180° pulse (signal 416), i.e., a 1 / 4 wave wide pulse occupying the third 1 / 4 wave period of the LO cycle. Similarly, the pulse generator 406 then generates a 90° pulse (signal 418), i.e., a 1 / 4 wave wide pulse occupying the second 1 / 4 wave period of the LO cycle, and a 180° pulse (signal 420), i.e., a 1 / 4 wave wide pulse occupying the fourth and last 1 / 4 wave of the LO cycle. Depending on the state of the I symbol (signal 422) appearing at the "select" input of the phase selector 408, either the 0° pulse or the 180° pulse will appear at the output (signal 424). Similarly, depending on the state of the Q symbol (signal 426) appearing at the "select" input of the phase selector 410, either the 90° pulse or the 270° pulse will appear at the output (signal 426). The signals 424 and 426 thus provide gating pulses that allow the IQ amplitude data to be multiplexed into T / 4 wide time slots to form a single data stream. This is now described using a diagram.

[0046] Figure 5 A system 500 is shown, which is a system arranged in accordance with aspects of the present disclosure.

[0047] As shown in the diagram, the system 500 includes a converter 502, a converter 504, an LO pulse generator 404, an LO pulse generator 406, a phase selector 408, a phase selector 410, a delta sigma modulator 514, a delta sigma modulator 516, a logic component 518, a PA 526, a matching and filtering component 528, a load 530, and a ground 531. The logic component 518 includes an AND gate 520, an AND gate 522, and an OR gate 524.

[0048] In this example, converter 502, converter 504, LO pulse generator 404, LO pulse generator 406, phase selector 408, phase selector 410, ΔΣ modulator 514, ΔΣ modulator 516, logic component 518, PA 526, matching and filtering component 528, AND gate 520, AND gate 522, and OR gate 524 are different components. However, in other examples, at least two of converter 502, converter 504, LO pulse generator 404, LO pulse generator 406, phase selector 408, phase selector 410, ΔΣ modulator 514, ΔΣ modulator 516, logic component 518, PA 526, matching and filtering component 528, AND gate 520, AND gate 522, and OR gate 524 can be combined into a unified component. Furthermore, in some examples, at least one of converter 502, converter 504, LO pulse generator 404, LO pulse generator 406, phase selector 408, phase selector 410, ΔΣ modulator 514, ΔΣ modulator 516, logic component 518, PA 526, matching and filtering component 528, AND gate 520, AND gate 522, and OR gate 524 can be implemented as a non-transitory, tangible computer readable medium for carrying or having computer- executable instructions or data structures stored therein. Such non-transitory, tangible computer readable media can be any available media that can be accessed by a general purpose or special purpose computer. Non-limiting examples of non-transitory, tangible computer readable media include physical storage devices and / or memory media such as RAM, ROM, EEPROM, CD- ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to carry or store desired program code means in the form of computer-executable instructions or data structures and which can be accessed by a general purpose or special purpose computer. When information is transferred or provided over a network or another communications connection (either hardwired, wireless, or a combination of hardwired or wireless) to a computer, the computer properly views the connection as a non-transitory, tangible computer readable medium. Thus, any such connection is properly termed a non-transitory, tangible computer readable medium. Combinations of the above should also be included within the scope of non-transitory, tangible computer readable media.

[0049] Converter 502 is disposed between line 532, line 422, and line 536. Converter 504 is disposed between line 538, line 426, and line 542. Phase selector 408 is arranged to input signals 414, 416, and 422 and output signal 424. Delta sigma modulator 514 inputs a signal on line 536 and outputs a signal on line 546. Phase selector 410 is arranged to input signals 418, 420, and 426 and output signal 428. Delta sigma modulator 516 inputs a signal on line 542 and outputs a signal on line 550. AND gate 520 inputs signal 424 from phase selector 408, inputs the signal from delta sigma modulator 514 on line 546, and outputs on line 552. AND gate 522 inputs signal 428 from phase selector 410, inputs the signal from delta sigma modulator 516 on line 550, and outputs on line 554. OR gate 524 is arranged to input signals via line 552 and line 554 and outputs to PA 526 via line 556. PA 526 outputs on line 558 to matching and filtering component 528. Load 530 is disposed between line 560 from matching component 528 and ground 531. Matching and filtering component 528 is disposed between PA 526 and load 530.

[0050] Converter 502 and converter 504 each convert analog / mixed Cartesian data signals into sign and magnitude data signals. LO pulse generator 404, LO pulse generator 406, phase selector 408, phase selector 410 can operate as described above with reference to Figure 4 Delta sigma modulator 514 and delta sigma modulator 516 perform 1-bit delta sigma digitization. AND gate 520 and AND gate 522 perform a Boolean AND function, while OR gate 524 provides a Boolean OR function. PA 526 provides an amplified RF signal based on its inputs.

[0051] In operation, analog I and Q data are split into sign and magnitude portions by converter 502 and converter 504, respectively, as explained above with reference to Figure 2 LO pulse generator 404, LO pulse generator 406, phase selector 408, phase selector 410 provide gating pulses as described above with reference to Figure 4 The I magnitude signal on line 536 as an analog signal is converted to a digital stream by delta sigma modulator 514. Similarly, the Q magnitude signal on line 542 is converted to a digital stream by delta sigma modulator 516.

[0052] If the I sign is positive, AND gate 520 uses the gating pulse for signal 424 as Figure 4 described to place the I digital amplitude data on line 546 in the first (0°) 1 / 4 cycle portion of the LO cycle, or if the I sign is negative, AND gate 520 uses the gating pulse for signal 424 asFigure 4 The strobe pulse that describes the generated signal 424 places the I digital amplitude data that appears on line 546 in the third (180°) 1 / 4 cycle portion of the LO cycle. Similarly, the Q digital amplitude data that appears on line 550 is placed in the second (90°) 1 / 4 cycle portion of the LO cycle if the Q sign is positive, or in the fourth (270°) 1 / 4 cycle portion of the LO cycle if the Q sign is negative, using the strobe pulse of signal 428 by AND gate 522. The outputs of AND gate 520 and AND gate 522 are then combined using OR gate 524. Thus, there is a single data stream to power amplifier PA 526 on line 556 that encodes I sign, I magnitude, Q sign, and Q magnitude information. The waveforms if I and Q signs and magnitudes appear on line 556 are further described below in Figure 6 and are delivered to PA 526. The output impedance of PA 526 is then matched to the network and load 530 by matching and filtering component 528. Matching and filtering component 528 also filters out quantization noise generated by the delta sigma conversion process.

[0053] Figure 6 Timing diagram 600, which illustrates the eight states shown in Figure 3 and generated according to aspects of the present application as described in Figure 5 Timing diagram 600, which illustrates the eight states shown in

[0054] As shown in the figure, timing diagram 600 includes line 602, line 603, waveform 604, waveform 606, waveform 608, waveform 610, waveform 612, waveform 614, waveform 616, and waveform 618.

[0055] Line 602 is the origin. Line 603 is the end of the first LO cycle and the beginning of a new cycle. Waveform 604 represents the state I = +1, Q = 0; waveform 606 represents the state I = -1, Q = 0; waveform 608 represents the state I = 0, Q = +1; waveform 610 represents the state I = 0, Q = -1; waveform 612 represents the state I = +1, Q = +1; waveform 614 represents the state I = -1, Q = +1; waveform 616 represents the state I = +1, Q = -1; and waveform 618 represents the state I = -1, Q = -1.

[0056] As illustrated, each waveform is spread across four consecutive 1 / 4 cycles (T / 4) of the LO frequency. Since each of the eight possible IQ states is unique, each of the eight waveforms is also unique. In the above using Figures 3 to 5In the described method, the data stream combination of instances of these waveforms presents all I and Q sign and amplitude information in the analog I and Q data input to the system as a single bit data stream for CMOS switched mode PA amplification.

[0057] Reference is made to Figures 4 to 5 The described example embodiment uses multiplexers and generation of 25% duty cycle (1 / 4 period) LO pulses for symbol based phase selection. The order of amplitude data for the four 1 / 4 period slots within an LO clock period for this embodiment is: I sign positive, Q sign positive, I sign negative, Q sign negative. This is not intended to be limiting, as other embodiments can also be used to combine analog IQ data into a single bit stream by distributing amplitude data into portions of an LO clock cycle based on sign. For example, another example embodiment can use generation of 75% (3 / 4 wave) LO pulses, and the order of amplitude data within an LO clock period can be different. This case is described using a diagram.

[0058] Figure 7 A system 700 is shown, which is an example embodiment using generation of 75% LO duty cycle.

[0059] The system 700 includes an LO clock 402, a pulse generator 704, a pulse generator 706, a phase selector 708, and a phase selector 710. The phase selector 708 includes an XOR gate 712 and an XOR gate 714 and an AND gate 716. The phase selector 710 includes an XOR gate 718 and an XOR gate 720 and an AND gate 722.

[0060] In this example, the LO clock 402, the pulse generator 704, the pulse generator 706, the phase selector 708, the phase selector 710, the XOR gate 712 and the XOR gate 714, the AND gate 716, the XOR gate 718 and the XOR gate 720, the AND gate 722 are distinct components. However, in other examples, at least two of the LO clock 402, the pulse generator 704, the pulse generator 706, the phase selector 708, the phase selector 710, the XOR gate 712 and the XOR gate 714, the AND gate 716, the XOR gate 718 and the XOR gate 720, the AND gate 722 can be combined into a unified component. Furthermore, in some examples, at least one of the LO clock 402, the pulse generator 704, the pulse generator 706, the phase selector 708, the phase selector 710, the XOR gate 712 and the XOR gate 714, the AND gate 716, the XOR gate 718 and the XOR gate 720, the AND gate 722 can be implemented as a non-transitory, tangible computer readable medium that carries or has computer- executable instructions or data structures stored on it.

[0061] The LO clock 402 is arranged to output signals on line 412 to both the pulse generator 704 and the pulse generator 706. The pulse generator 704 is arranged to output signals on line 724 and line 726. The pulse generator 706 is arranged to output signals on line 728 and line 730. The "exclusive OR" gate 712 is arranged to input signals on line 422 and line 724 and output a signal on line 732 to the "AND" gate 716. The "exclusive OR" gate 714 is arranged to input signals on line 723 and line 726 and output a signal on line 734 to the "AND" gate 716. The "exclusive OR" gate 718 is arranged to input signals on line 725 and line 728 and output a signal on line 736 to the "AND" gate 722. The "exclusive OR" gate 720 is arranged to input signals on line 426 and line 730 and output a signal on line 738 to the "AND" gate 722. The "AND" gate 716 is arranged to input signals on line 732 and line 734 and output a signal on line 740. The "AND" gate 722 is arranged to input signals on line 736 and line 738 and output a signal on line 742.

[0062] The LO clock 402 generates a digital clock having a period T. The LO pulse generator 704 generates a 75% duty cycle pulse having a width of 3T / 4. The pulse generator 706 also generates a 75% duty cycle pulse having a width of 3T / 4. Both phase selectors 708 and 710 generate gating pulses based on the sign. Both "exclusive OR" gates 712 and 714 provide a Boolean "exclusive OR" function. The "AND" gate 716 provides a Boolean "AND" function. Both "exclusive OR" gates 718 and 720 provide a Boolean "exclusive OR" function. The "AND" gate 722 provides a Boolean "AND" function.

[0063] In operation, the system 700 performs similar functions as the system 400, although for different embodiments, where the amplitude data for I and Q are placed in separate 1 / 4 wave periods within the LO clock cycle. As with the system 400, Figure 4 In contrast to the system 400, the system 700 uses pulse generators (704 and 706) to generate pulses having a width of 3T / 4 (75% of the cycle) and separated in time by T / 4 (1 / 4 of the cycle) (i.e., starting at phase positions 0°, 90°, 180°, and 270°). On the other hand, Figure 4 The system 400 uses a pulse generator that generates pulses having a width of T / 4. Other differences are that the phase selectors (708 and 710) of the system 700 employ "exclusive OR" logic gates and "AND" logic gates to generate the gating pulses rather than Figure 4the system 400, the strobe pulses for I symbol positive, Q symbol positive, I symbol negative, Q symbol negative are assigned to the fourth, first, second, and third 1 / 4 cycle time slots, respectively. However, for operation in accordance with aspects of the present application, the order is not important as long as the amplitude data for I and Q are placed in separate 1 / 4 wave cycles within the LO clock cycle depending on the sign. Figure 4 Figure 4

[0064] It has been described how systems and methods in accordance with aspects of the present application can achieve the high efficiency properties of switched mode CMOS PAs by encoding the analog IQ signal into a single bit stream for amplification. It has been explained how all the required properties of the analog IQ information are represented by a single bit stream by initially converting the analog IQ signal into digital I and Q signs and digital I and Q amplitude data and then using the sign information about the cycles of the local oscillator to arrange and order the amplitude information in time.

[0065] It has also been described how a conventional system and method is prone to have bandwidth widening and performance limitation problems due to variations in PA response. For systems and methods in accordance with aspects of the present application, the bandwidth widening problem is eliminated since no Cartesian to polar conversion process is employed. Furthermore, the performance limitation due to variations in PA response is also eliminated since the PA supply voltage is not involved and variations in the supply bias will not cause variations in the PA switching time. It has also been described how another conventional system and method has the problem that it requires a more complex multi-stage power amplifier for operation and is prone to have data corruption problems related to I to Q leakage, which is due to the IQ combination being performed at the PA output after the post PA filtering network, such an arrangement cannot achieve low settling time. However, for systems and methods in accordance with aspects of the present application, no multi-stage PA is required. Since the IQ combination is fast digital processing performed at the input of the PA, data corruption due to I to Q leakage is also not a problem.

[0066] Systems and methods in accordance with aspects of the present application therefore have distinct and significant advantages over the prior art, which are the elimination of many performance problems and complex implementation problems associated with conventional systems and methods to encode analog IQ information for use with high efficiency CMOS switched mode PAs.

[0067] The foregoing description of various preferred embodiments of the present application has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the application to the precise form disclosed, and various modifications and variations are possible in light of the above teachings. The example embodiments described above have been chosen and described in order to best explain the principles of the application and its practical application to enable others skilled in the art to best utilize the application in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the application be defined by the claims appended hereto.

Claims

1. A circuit comprising: An I-converter configured to receive I-data, output I-symbol data based on the received I-data, and output I-value data based on the received I-data; A Q converter configured to receive Q data, output Q symbol data based on the received Q data, and output Q value data based on the received Q data, wherein the I value data and the Q value data are analog signals; Operable to generate an I-phase clock based on the I-symbol data, the I-phase having an I-duty cycle; Operable to generate a Q-phase clock based on the Q-symbol data, the Q-phase having a Q-duty cycle; An I modulator operable to generate an I-value pulse stream based on the I-value data; A Q modulator operable to generate a Q-value pulse stream based on the Q-value data; A digital logic component operable to generate a periodic data stream in response to obtaining the I symbol data, the I magnitude pulse stream, the Q symbol data, and the Q magnitude pulse stream in such a way as follows: When the I symbol data is positive, the I value pulse stream is encoded as the first part of the period of the data stream; When the Q symbol data is positive, the Q value pulse stream is encoded as the second part of the period of the data stream; When the I symbol data is negative, the I value pulse stream is encoded as the third part of the period of the data stream; as well as When the Q-symbol data is positive, the Q-value pulse stream is encoded as the fourth part of the period of the data stream; and A power amplifier operable to generate an amplified signal based on the data stream; The digital logic components mentioned above include I AND gates, Q AND gates, and OR gates. The I AND gate is operable to generate an I output based on a Boolean AND operation of the I symbol data and the I magnitude pulse stream. The Q AND gate is operable to generate a Q output based on a Boolean AND operation of the Q-symbol data and the Q-value pulse stream, and The OR gate is operable to generate the data stream based on a Boolean OR operation of the I output and the Q output.

2. The circuit according to claim 1, wherein 25% ≥ I duty cycle > 0%.

3. The circuit according to claim 2, wherein the I modulator includes a ΔΣ modulator.

4. The circuit according to claim 1, wherein the I modulator includes a ΔΣ modulator.

5. The circuit according to claim 1, wherein the I modulator includes a ΔΣ modulator.

6. The circuit according to claim 1, wherein 100% > I duty cycle ≥ 50%.

7. The circuit of claim 6, wherein the I modulator comprises a ΔΣ modulator.

8. The circuit of claim 1, wherein the I modulator comprises a ΔΣ modulator.

9. A method comprising: Receive I data via I converter; Based on the received I data, I symbol data is output via the I converter; Based on the received I data, the I value data is output via the I converter; Receive Q data via Q converter; Based on the received Q data, Q symbol data is output via the Q converter; Based on the received Q data, Q value data is output via the Q converter, wherein the I value data and the Q value data are analog signals; Based on the I symbol data, an I phase is generated via an I clock, and the I phase has an I duty cycle; Based on the Q symbol data, a Q phase is generated via a Q clock, and the Q phase has a Q duty cycle; Based on the I-value data, an I-value pulse stream is generated via an I-modulator; Based on the Q-value data, a Q-value pulse stream is generated via a Q modulator; In response to obtaining the I symbol data, the I magnitude pulse stream, the Q symbol data, and the Q magnitude pulse stream, a periodic data stream is generated by digital logic components in the following manner: When the I symbol data is positive, the I value pulse stream is encoded as the first part of the period of the data stream; When the Q symbol data is positive, the Q value pulse stream is encoded as the second part of the period of the data stream; When the I symbol data is negative, the I value pulse stream is encoded as the third part of the period of the data stream; as well as When the Q symbol data is positive, the Q value pulse stream is encoded as the fourth part of the period of the data stream; as well as The data stream is amplified by a power amplifier to generate an amplified signal. The generation of the data stream via the digital logic component includes: Based on the Boolean AND operation of the I symbol data and the I magnitude pulse stream, an I output is generated via an I AND gate; Based on the Boolean AND operation of the Q symbol data and the Q magnitude pulse stream, a Q output is generated via a Q AND gate; and A single-bit data stream is generated via an OR gate based on the Boolean OR operation of the I output and the Q output.

10. The method of claim 9, wherein 25% ≥ I duty cycle > 0%.

11. The method of claim 10, wherein generating the I-value pulse stream comprises generating the I-value pulse stream via a ΔΣ modulator.

12. The method of claim 9, wherein generating the I-value pulse stream comprises generating the I-value pulse stream via a ΔΣ modulator.

13. The method of claim 9, wherein generating the I-value pulse stream comprises generating the I-value pulse stream via a ΔΣ modulator.

14. The method of claim 9, wherein 100% > I duty cycle ≥ 50%.

15. The method of claim 14, wherein generating the I-value pulse stream comprises generating the I-value pulse stream via a ΔΣ modulator.

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