On-chip reconfigurable vector synthesis phase shifter for phased array system

Abstract

The invention belongs to the field of wireless communication, relates to a phase shifter in a phased array system, and particularly provides an on-chip reconfigurable vector synthesis phase shifter for the phased array system, which is used for meeting the application requirements of wide working bandwidth, high beam scanning precision and low cost of the phased array system in the future. The on-chip reconfigurable vector synthesis phase shifter comprises a reconfigurable IQ signal generation network, a VGA array and a vector synthesis network, the reconfigurable IQ signal generation network is formed by cascading an RC multi-phase filter and an RL multi-phase filter, transistor switches are arranged in the RC multi-phase filter and the RL multi-phase filter respectively, and the VGA array is connected with the VGA array. And mutual switching between the first reconstruction mode and the second reconstruction mode is realized through combination of the two paths of switching signals S1 and S2. By means of reconfigurable mode switching, 3.3 GHz-28.5 GHz orthogonal signal output can be achieved, the coverage bandwidth reaches 158%, and the circuit has the advantages of being small in chip area, low in cost, high in precision and the like.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication and relates to phase shifters in phased array systems. Specifically, it provides a low-cost, ultra-wideband, and high-precision on-chip reconfigurable vector synthesis phase shifter for phased array systems. Background Technology

[0002] In recent years, with the continuous development of wireless communication applications, the performance requirements of radio frequency microwave communication systems have become increasingly stringent. Phased array technology, with its advantages of high resolution, high anti-interference capability, and fast beam scanning, has become a research hotspot in fields such as 5G millimeter-wave communication, satellite communication, automotive radar, and aerospace exploration. A phased array system typically consists of hundreds of antenna array elements. By changing the phase and amplitude of each antenna, the electromagnetic waves from multiple transmitting or receiving units interfere and superimpose in space, coherently superimposing in specific directions and canceling out in others, ultimately enabling the entire antenna array to dynamically adjust its beam pointing, shape, and function. The phase shifter, as the core device for adjusting the phase in a phased array system, is crucial to the system's performance. The phase accuracy of the phase shifter affects the beam scanning accuracy and beam quality of the phased array system; its frequency bandwidth affects the operating frequency bandwidth; its power capacity and noise figure affect the sensitivity and dynamic range; and its layout area affects the integration cost. Therefore, researching a low-cost, ultra-wideband, and high-precision phase shifter is of significant importance and practical value.

[0003] Currently, on-chip phase shifters in silicon-based CMOS processes are divided into active and passive structures. Passive phase shifters mainly include reflective phase shifters, high-pass and low-pass phase shifters, and load-line phase shifters. They have advantages such as simple structure and high linearity, but they have large insertion loss and are difficult to achieve high phase resolution and high phase accuracy, making it difficult to meet the requirements of high-performance phased array systems for beam scanning accuracy and beam quality. Active phase shifters mainly include vector synthesis phase shifters, which have the advantage of high phase shift accuracy, making them the mainstream structure used in high-performance phased array systems. However, traditional vector synthesis phase shifters have narrow bandwidth, making it difficult to meet the broadband performance requirements of multi-band and multi-standard wireless communication systems.

[0004] To address the bandwidth issue of active phase shifters, two independent phase shifters are often connected in parallel and switched using a switch. While this method can extend the bandwidth, it results in a complex circuit structure, introduces additional parasitic effects and losses, and significantly increases the layout area, hindering large-scale phased array system integration and substantially increasing system cost. Alternatively, using multi-stage IQ (orthogonal) signal generation networks can also achieve broadband performance, but this leads to a significant increase in losses with each stage. Furthermore, while the increased bandwidth is wider than that of a single-stage IQ (orthogonal) signal generation network, it is still limited by the bandwidth performance of the IQ (orthogonal) signal generation network. This method also significantly increases chip area, further increasing the system cost of the phased array system.

[0005] Therefore, in order to meet the requirements of wide operating bandwidth, high beam scanning accuracy and low cost of future phased array systems, this invention proposes a small-area, low-cost, ultra-wideband, high-precision on-chip reconfigurable vector synthesis phase shifter based on silicon-based CMOS technology. Summary of the Invention

[0006] The purpose of this invention is to provide an on-chip reconfigurable vector synthesis phase shifter for phased array systems, aiming to meet the application requirements of wide operating bandwidth, high beam scanning accuracy, and low cost of future phased array systems.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] An on-chip reconfigurable vector synthesis phase shifter for a phased array system includes: a reconfigurable IQ signal generation network, a VGA array, and a vector synthesis network. An input differential signal is generated into four orthogonal signals by the reconfigurable IQ signal generation network, amplified by the VGA array, and then synthesized by the vector synthesis network into an output differential signal. The reconfigurable IQ signal generation network is composed of a cascaded RC polyphase filter and an RL polyphase filter. Transistor switches are respectively installed in the RC and RL polyphase filters, and the switching between a first reconstruction mode and a second reconstruction mode is achieved through the combination of two switch signals S1 and S2.

[0009] Furthermore, the RC multiphase filter is composed of 4 RC networks, each consisting of an R branch and a C branch. The R branch includes 2 resistors and 1 transistor switch, with the 2 resistors connected in parallel and one of the resistors connected to the transistor switch. The C branch includes 2 capacitors and 1 transistor switch, with the 2 capacitors connected in parallel and one of the capacitors connected to the transistor switch.

[0010] In each RC network, the input terminals of the R branch and the C branch are connected, and the first RC network inputs the Vin+ signal, and the third RC network inputs the Vin- signal.

[0011] The output of the R branch in the first RC network is connected to the output of the C branch in the fourth RC network, and the first output of the RC polyphase filter is drawn out.

[0012] The output of the C branch in the first RC network is connected to the output of the R branch in the second RC network, and the second output of the RC polyphase filter is drawn out.

[0013] The output of the C branch in the second RC network is connected to the output of the R branch in the third RC network, and the third output of the RC polyphase filter is brought out.

[0014] The output of the C branch in the third RC network is connected to the output of the R branch in the fourth RC network, and the fourth output of the RC polyphase filter is drawn out.

[0015] Furthermore, the RL multiphase filter is composed of 4 RL networks, each RL network consisting of an R branch and an L branch; the R branch includes: 2 resistors and 1 transistor switch, the 2 resistors are connected in parallel, and one of the resistors is connected to the transistor switch; the L branch is composed of 1 inductor.

[0016] In each RL network, the output terminals of the R branch and the L branch are connected, and the first to fourth RL networks output I+ signal, Q+ signal, I- signal and Q- signal respectively;

[0017] The input of the R branch in the first RL network is connected to the input of the L branch in the fourth RL network, and is correspondingly connected to the first output of the RC polyphase filter.

[0018] The input terminal of the L branch in the first RL network is connected to the input terminal of the R branch in the second RL network, and is correspondingly connected to the second output terminal of the RC polyphase filter;

[0019] The input of the L branch in the second RL network is connected to the input of the R branch in the third RL network, and is correspondingly connected to the third output of the RC polyphase filter.

[0020] The input of the L branch in the third RL network is connected to the input of the R branch in the fourth RL network, and is correspondingly connected to the fourth output of the RC polyphase filter.

[0021] Furthermore, in the RC multiphase filter, the transistor switch in the R branch is controlled by the switching signal S2, and the transistor switch in the C branch is controlled by the switching signal S1; in the RL multiphase filter, the transistor switch in the R branch is controlled by the switching signal S2; when the switching signal S1 is on and the switching signal S2 is off, the on-chip reconfigurable vector synthesis phase shifter operates in the first reconstruction mode, and when the switching signal S2 is on and the switching signal S1 is off, the on-chip reconfigurable vector synthesis phase shifter operates in the second reconstruction mode.

[0022] Furthermore, the VGA array adopts a numerically controlled circuit rudder structure, which is composed of six transistor array units connected in parallel. The transistor size ratio of the six transistor array units is 1, 2, 4, 8, 16, and 32.

[0023] Furthermore, the vector synthesis network is composed of a radio frequency transmission line connected to an output matching transformer.

[0024] Based on the above technical solution, the beneficial effects of the present invention are as follows:

[0025] This invention proposes a reconfigurable IQ (orthogonal) signal generation network. Through reconfigurable mode switching, it can achieve orthogonal signal output from 3.3GHz to 28.5GHz, covering a bandwidth of 158%. Furthermore, the reconfigurable IQ signal generation network is mainly composed of transistor switches, resistors, and capacitors, resulting in a very small layout area in silicon-based CMOS technology. This allows the reconfigurable IQ signal generation network to achieve ultra-wideband performance while maintaining the advantages of small chip area and low cost; its chip area is even smaller than that of many existing narrowband structures. Simultaneously, a reconfigurable vector synthesis phase shifter is constructed based on the reconfigurable IQ (orthogonal) signal generation network, exhibiting excellent phase shifting accuracy and amplitude accuracy, achieving industry-leading performance.

[0026] In summary, this invention provides an on-chip reconfigurable vector synthesis phase shifter for phased array systems, which has advantages such as small area, ultra-wide bandwidth, and high precision, significantly reducing the integration cost of phased array systems. For future phased array systems with ultra-large array numbers, it has a significant cost advantage. Attached Figure Description

[0027] Figure 1 This is a schematic diagram illustrating the working principle of the vector synthesis phase shifter in this invention.

[0028] Figure 2 This is a schematic diagram of the reconfigurable IQ (orthogonal) generator network in this invention.

[0029] Figure 3 This is a schematic diagram of the layout of the reconfigurable IQ (orthogonal) generator network in this invention.

[0030] Figure 4 The figure shows the simulation results of the input insertion loss of the reconfigurable IQ (orthogonal) generator network in this invention.

[0031] Figure 5 This is a simulation result of the phase of the reconfigurable IQ (orthogonal) generator network in this invention.

[0032] Figure 6 This is a schematic diagram of the on-chip reconfigurable vector synthesis phase shifter used in a phased array system in this invention.

[0033] Figure 7 This is a schematic diagram of the VGA (Variable Gain Amplifier) ​​array in this invention.

[0034] Figure 8 This is a graph showing the RMS amplitude accuracy of the on-chip reconfigurable vector synthesis phase shifter used in the phased array system of this invention.

[0035] Figure 9 This is a diagram showing the RMS phase accuracy of the on-chip reconfigurable vector synthesis phase shifter used in the phased array system of this invention.

[0036] The above Figure 2 In the diagram, 101 is an RC polyphase filter and 102 is an RL polyphase filter. Detailed Implementation

[0037] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0038] This embodiment proposes a small-area, ultra-wideband, high-precision on-chip reconfigurable vector synthesis phase shifter based on silicon-based CMOS technology, consisting of an IQ (quadrature) signal generation network, a VGA (variable gain amplifier) ​​unit, and a vector synthesis network; the working principle of the vector synthesis phase shifter is as follows: Figure 1 As shown, the input differential signals (Vin+ and Vin-) are processed by an IQ (quadrature) signal generation network to generate four quadrature signals. These four quadrature signals are then divided into I-channel and Q-channel signals. The I-channel signals have phases of 0° (I+) and 180° (I-), while the Q-channel signals have phases of 90° (Q+) and 270° (Q-). The I-channel and Q-channel signals are then amplified by a VGA unit. After amplification by the VGA unit, the I-channel signal becomes I'+ and I'-, and the Q-channel signal is amplified by the VGA unit. The signals are then converted into Q'+ and Q'- signals. These four signals are then vector-synthesized in a vector synthesis network. The Q'+ and I'+ signals are vector-synthesized to produce the Vout+ signal, and the Q'- and I'- signals are vector-synthesized to produce the Vout- signal. The synthesized Vout+ and Vout- are also differential signals. In this process, by adjusting the amplification factor of the VGA (Variable Gain Amplifier) ​​unit, the amplitude of the I and Q signals can be controlled. Finally, through the vector synthesis principle, an output signal of arbitrary phase is generated, achieving the phase shift function.

[0039] The IQ (orthogonal) signal generation network is the core component of the vector synthesis phase shifter. The wider the operating bandwidth of the IQ (orthogonal) signal generation network, the wider the operating frequency of the phase shifter. In conventional designs, three or more stages of IQ (orthogonal) generation networks are often used to achieve bandwidth performance, but this leads to a significant increase in losses with increasing stage number, and the bandwidth expansion is limited by the parasitic characteristics of inductors and capacitors, resulting in limited improvement. In addition, this structure significantly increases the chip area, which is unacceptable for the system integration cost of phased array systems with thousands of channels. Therefore, in order to achieve a low-cost, ultra-wideband vector synthesis phase shifter design, this embodiment creatively proposes a reconfigurable IQ (orthogonal) generation network with small area and ultra-wideband characteristics. Based on the orthogonal generation network of RC (resistor / capacitor) multiphase filter, it is improved into an RC-RL (resistor / capacitor-resistor / inductor) multiphase filter structure. By switching, the capacitance and resistance values ​​can be reconfigured, thereby widening the bandwidth.

[0040] In this embodiment, the reconfigurable IQ (orthogonal) generator network is as follows: Figure 2 As shown, a two-stage IQ (signal) generation network is formed using an RC-RL (resistor / capacitor-resistor / inductor) structure, consisting of an RC polyphase filter 101 and an RL polyphase filter 102.

[0041] The RC multiphase filter 101 is composed of 4 RC networks, each consisting of an R branch and a C branch. The R branch includes 2 resistors and 1 transistor switch, with the 2 resistors connected in parallel and one of the resistors connected to the transistor switch. The C branch includes 2 capacitors and 1 transistor switch, with the 2 capacitors connected in parallel and one of the capacitors connected to the transistor switch.

[0042] In each RC network, the input terminals of the R branch and the C branch are connected, and the first RC network inputs the Vin+ signal, and the third RC network inputs the Vin- signal.

[0043] The output of the R branch in the first RC network is connected to the output of the C branch in the fourth RC network, and the first output of the RC polyphase filter is drawn out.

[0044] The output of the C branch in the first RC network is connected to the output of the R branch in the second RC network, and the second output of the RC polyphase filter is drawn out.

[0045] The output of the C branch in the second RC network is connected to the output of the R branch in the third RC network, and the third output of the RC polyphase filter is brought out.

[0046] The output of the C branch in the third RC network is connected to the output of the R branch in the fourth RC network, and the fourth output of the RC polyphase filter is drawn out.

[0047] Specifically, the RC multiphase filter 101 is composed of resistors R11~R18, capacitors C11~C18, and transistor switches M11~M18. Among them, resistors R11, R12, C11, C12, and transistor switches M11 and M12 form the first RC network; resistors R13, R14, C13, C14, and transistor switches M13 and M14 form the second RC network; resistors R15, R16, C15, C16, and transistor switches M15 and M16 form the third RC network; and resistors R17, R18, C17, C18, and transistor switches M17 and M18 form the fourth RC network. Transistor switches M11, M13, M15, and M17 are controlled by switch signal S2, and transistor switches M12, M14, M16, and M18 are controlled by switch signal S1.

[0048] The RL multiphase filter 102 is composed of 4 RL networks, each consisting of an R branch and an L branch. The R branch includes 2 resistors and 1 transistor switch, with the 2 resistors connected in parallel and one of the resistors connected to the transistor switch. The L branch consists of 1 inductor.

[0049] In each RL network, the output terminals of the R branch and the L branch are connected, and the first to fourth RL networks output I+ signal, Q+ signal, I- signal and Q- signal respectively;

[0050] The input of the R branch in the first RL network is connected to the input of the L branch in the fourth RL network, and is correspondingly connected to the first output of the RC polyphase filter.

[0051] The input terminal of the L branch in the first RL network is connected to the input terminal of the R branch in the second RL network, and is correspondingly connected to the second output terminal of the RC polyphase filter;

[0052] The input of the L branch in the second RL network is connected to the input of the R branch in the third RL network, and is correspondingly connected to the third output of the RC polyphase filter.

[0053] The input of the L branch in the third RL network is connected to the input of the R branch in the fourth RL network, and is correspondingly connected to the fourth output of the RC polyphase filter.

[0054] Specifically, the RL multiphase filter 102 is composed of resistors R21~R28, inductors L21~L24, and transistor switches M21~M24. Among them, resistors R21, R22, inductors L21 and transistor switch M21 form the first RL network; resistors R23, R24, inductors L22 and transistor switch M22 form the second RL network; resistors R25, R26, inductors L23 and transistor switch M23 form the third RL network; and resistors R27, R28, inductors L24 and transistor switch M24 form the fourth RL network. Transistor switches M21~M24 are controlled by switching signal S2.

[0055] Depend on Figure 2 As can be seen, the reconfigurable IQ (orthogonal) generation network in this embodiment is mainly composed of resistors and capacitors, and the layout area of ​​resistors and capacitors is almost negligible in CMOS technology; therefore, by reasonably arranging the inductor positions, the reconfigurable IQ (orthogonal) generation network provided in this embodiment can achieve layout with a very small chip area, such as... Figure 3 As shown, a ring layout design is adopted, in which the first-stage RC multiphase filter 101 surrounds the second-stage RL multiphase filter 102. Since the layout area of ​​resistors and capacitors in CMOS technology is small, they are arranged in the center of the layout to reduce the layout area, while the inductor, which accounts for the largest proportion of the layout area in the circuit, is arranged in the center of the layout. Figure 4 This design optimizes the use of space in every corner, thereby increasing the utilization rate of the layout area; ultimately, the layout area designed using CMOS technology in this embodiment is as low as 0.023 mm². 2 (100um×230um), the layout area is reduced by at least half compared to conventionally designed IQ (orthogonal) signal generation networks.

[0056] The reconfigurable IQ (orthogonal) generation network has a first reconstruction mode and a second reconstruction mode, which are switched by switching signals S1 and S2; the first reconstruction mode is that switching signal S1 is on and switching signal S2 is off, and the second reconstruction mode is that switching signal S2 is on and switching signal S1 is off; for example Figure 4 and Figure 5 The figure shows the input insertion loss and phase of the reconfigurable IQ (orthogonal) generation network. S21 represents the insertion loss of the Q+ signal, S31 represents the insertion loss of the Q- signal, S41 represents the insertion loss of the I+ signal, and S51 represents the insertion loss of the I- signal. As can be seen from the figure, according to the orthogonal signal requirements of amplitude <0.5dB and phase <1°, the first reconstruction mode covers 3.3 GHz ~ 14 GHz, and the second reconstruction mode covers 13 GHz ~ 28.5 GHz. Therefore, the working bandwidth of the reconfigurable IQ (orthogonal) generation network is 3.3 GHz ~ 28.5 GHz, with a coverage bandwidth of up to 158% (25.2 GHz), achieving an ultra-wideband working bandwidth.

[0057] Based on the aforementioned reconfigurable IQ (orthogonal) generation network, this embodiment provides an on-chip reconfigurable vector synthesis phase shifter for a phased array system, the structure of which is as follows: Figure 6 As shown, it includes: a reconfigurable IQ (orthogonal) signal generation network, an I-channel VGA (variable gain amplifier) ​​array, a Q-channel VGA (variable gain amplifier) ​​array, and a vector synthesis network; the input differential signals (Vin+ and Vin- signals) are generated into four orthogonal signals by the reconfigurable IQ (orthogonal) signal generation network, including I-channel signals and Q-channel signals. The I-channel signals include I+ and I- signals, and the Q-channel signals include Q+ and Q- signals. The I-channel signals and Q-channel signals are respectively amplified by the VGA array. After amplification by the VGA unit, the I-channel signal becomes I'+ and I'- signals, and the Q-channel signal becomes Q'+ and Q'- signals. The four signals are finally vector synthesized in the vector synthesis network. The Q'+ signal and the I'+ signal are vector synthesized to generate the Vout+ signal, and the Q'- signal and the I'- signal are vector synthesized to generate the Vout- signal. The synthesized Vout+ and Vout- are also differential signals.

[0058] To improve phase accuracy, the VGA (Variable Gain Amplifier) ​​array in this embodiment adopts a digitally controlled circuit rudder structure. This structure achieves transistor array switching through control signals, realizing very fine gain control, thereby improving the phase accuracy of vector synthesis. Furthermore, under different control states, each pair of transistors always keeps one path conducting, thus keeping parameters such as input and output impedance and current consistent, which is beneficial for broadband circuit design.

[0059] The VGA (Variable Gain Amplifier) ​​array, as shown below Figure 7 As shown, it consists of six transistor array units connected in parallel. The transistor size ratios of the six transistor array units are 1, 2, 4, 8, 16, and 32. By switching transistors of different sizes through a digital module, the purpose of fine gain control is achieved, thereby realizing high-precision phase synthesis.

[0060] Each transistor array unit consists of transistors M31, M32, M33, M34, M35, and M36, resistors R31 and R32. The source of transistor M31 is connected to the drain of transistor M35 and the source of transistor M32. The drain of transistor M31 is connected to the drain of transistor M33 and outputs a Q'- / I'- signal. The gate of transistor M31 is connected to the gate of transistor M34 and inputs a digital control signal Qctrl<5:0> / Ictrl<5:0>. The source of transistor M32 is connected to the drain of transistor M35 and the source of transistor M31. The drain of transistor M32 is connected to the drain of transistor M34 and outputs a Q'+ / I'+ signal. The gate of transistor M32 is connected to the gate of transistor M33 and inputs a digital control signal. The source of transistor M33 is connected to the drain of transistor M36 and the source of transistor M34. The source of transistor M34 is connected to the drain of transistor M36 and the source of transistor M33. The source of transistor M35 is connected to the power supply ground, and the gate of transistor M35 receives Q+ / I- signals. The source of transistor M36 is connected to the power supply ground, and the gate of transistor M36 receives Q- / I+ signals. One end of resistor R31 is connected to the voltage bias VBIAS, and the other end is connected to the gate of transistor M35. One end of resistor R32 is connected to the voltage bias VBIAS, and the other end is connected to the gate of transistor M36. The transistor array unit ensures that the operating current of transistors M35 and M36 is constant through a fixed voltage bias VBIAS. The amplifier gain is varied through two sets of digitally controlled voltages Qctrl<5:0> / Ictrl<5:0> and This is achieved by having one transistor in low-voltage off mode and the other in high-voltage on mode. Therefore, there will always be one set of transistor arrays conducting between M31 and M34, and between M32 and M33. The amplifier current and input / output impedance will not change with the number of digitally controlled voltages on. At the same time, the two sets of digitally controlled voltages can reverse the polarity of the input differential signal, thereby generating IQ signals of different polarities. In addition, controlling the number of digitally controlled voltages on can change the number of conducting transistors in the entire transistor array, thereby changing the number of current rudders and achieving fine gain control.

[0061] The vector synthesis network consists of an RF transmission line and an output matching transformer. The four output quadrature signals of the VGA (Variable Gain Amplifier) ​​array are connected together through the RF transmission line to achieve current synthesis of the output signals. The output matching transformer achieves broadband output matching.

[0062] In summary, this embodiment provides a small-area, ultra-wideband, high-precision on-chip reconfigurable vector synthesis phase shifter based on silicon-based CMOS technology. Mode switching is achieved through transistor switching in the reconfigurable IQ (quadrature) signal generation network, thereby covering the ultra-wideband operating bandwidth. Furthermore, it exhibits low phase shift RMS and amplitude RMS, achieving industry-leading performance. Figure 8 and Figure 9 The figure shows the simulation results of the amplitude RMS and phase RMS of the on-chip reconfigurable vector synthesis phase shifter in this embodiment. In high-performance phased array systems, the phase RMS is often required to be <3° and the amplitude RMS to be less than 0.2dB. As can be seen from the figure, the first reconstruction mode in this invention can meet the application requirements of 3.3GHz~13GHz, and the second reconstruction mode can meet the application requirements of 11GHz~28.5GHz. Therefore, the phase shifter meets the operating bandwidth of 3.3 GHz~28.5GHz, covering an operating bandwidth of up to 158% (25.2GHz), and the phase shifter can fully meet the requirements of future wireless communication systems such as 5G communication, satellite communication, and military radar.

[0063] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.

Claims

1. An on-chip reconfigurable vector synthesis phase shifter for a phased array system, comprising: The system comprises a reconfigurable IQ signal generation network, a VGA array, and a vector synthesis network. An input differential signal is generated into four orthogonal signals by the reconfigurable IQ signal generation network, amplified by the VGA array, and then synthesized by the vector synthesis network into an output differential signal. The reconfigurable IQ signal generation network is characterized by being composed of a cascaded RC polyphase filter and an RL polyphase filter. Transistor switches are respectively installed in the RC and RL polyphase filters, and the switching between a first reconstruction mode and a second reconstruction mode is achieved through the combination of two switch signals, S1 and S2.

2. The on-chip reconfigurable vector synthesis phase shifter for a phased array system according to claim 1, characterized in that, The RC multiphase filter consists of four RC networks, each consisting of an R branch and a C branch. The R branch includes two resistors and one transistor switch, with the two resistors connected in parallel and one of the resistors connected to the transistor switch. The C branch includes two capacitors and one transistor switch, with the two capacitors connected in parallel and one of the capacitors connected to the transistor switch. In each RC network, the input terminals of the R branch and the C branch are connected, and the first RC network inputs the Vin+ signal, and the third RC network inputs the Vin- signal. The output of the R branch in the first RC network is connected to the output of the C branch in the fourth RC network, and the first output of the RC polyphase filter is drawn out. The output of the C branch in the first RC network is connected to the output of the R branch in the second RC network, and the second output of the RC polyphase filter is drawn out. The output of the C branch in the second RC network is connected to the output of the R branch in the third RC network, and the third output of the RC polyphase filter is brought out. The output of the C branch in the third RC network is connected to the output of the R branch in the fourth RC network, and the fourth output of the RC polyphase filter is drawn out.

3. The on-chip reconfigurable vector synthesis phase shifter for a phased array system according to claim 2, characterized in that, In the R branch of the RC multiphase filter, the transistor switch is controlled by the switching signal S2, and the transistor switch in the C branch is controlled by the switching signal S1.

4. The on-chip reconfigurable vector synthesis phase shifter for a phased array system according to claim 1, characterized in that, The RL multiphase filter consists of four RL networks, each consisting of an R branch and an L branch. The R branch includes two resistors and one transistor switch, with the two resistors connected in parallel and one of them connected to the transistor switch. The L branch consists of one inductor. In each RL network, the output terminals of the R branch and the L branch are connected, and the first to fourth RL networks output I+ signal, Q+ signal, I- signal and Q- signal respectively; The input of the R branch in the first RL network is connected to the input of the L branch in the fourth RL network, and is correspondingly connected to the first output of the RC polyphase filter. The input terminal of the L branch in the first RL network is connected to the input terminal of the R branch in the second RL network, and is correspondingly connected to the second output terminal of the RC polyphase filter; The input of the L branch in the second RL network is connected to the input of the R branch in the third RL network, and is correspondingly connected to the third output of the RC polyphase filter. The input of the L branch in the third RL network is connected to the input of the R branch in the fourth RL network, and is correspondingly connected to the fourth output of the RC polyphase filter.

5. The on-chip reconfigurable vector synthesis phase shifter for a phased array system according to claim 4, characterized in that, In the R branch of the RL multiphase filter, the transistor switch is controlled by the switching signal S2.

6. The on-chip reconfigurable vector synthesis phase shifter for a phased array system according to claim 1, characterized in that, When switch signal S1 is on and switch signal S2 is off, the on-chip reconfigurable vector synthesizer phase shifter operates in the first reconstruction mode. When switch signal S2 is on and switch signal S1 is off, the on-chip reconfigurable vector synthesizer phase shifter operates in the second reconstruction mode.

7. The on-chip reconfigurable vector synthesis phase shifter for a phased array system according to claim 1, characterized in that, The VGA array adopts a numerically controlled circuit rudder structure, which is composed of six transistor array units connected in parallel. The transistor size ratio of the six transistor array units is 1, 2, 4, 8, 16, and 32.

8. The on-chip reconfigurable vector synthesis phase shifter for a phased array system according to claim 1, characterized in that, The vector synthesis network consists of a radio frequency transmission line connected to an output matching transformer.

Images