Fractional frequency division phase-locked loop feedback circuit and phase noise optimization method

Abstract

The invention provides a fractional frequency division phase-locked loop feedback circuit and a phase noise optimization method. The circuit comprises a voltage-controlled oscillator, a feedback frequency division circuit, a double-phase discriminator and a charge pump which are electrically connected in sequence, the voltage-controlled oscillator generates a first clock; after receiving a first clock from the voltage-controlled oscillator, the feedback frequency dividing circuit carries out frequency dividing and delay processing on the first clock to obtain a feedback clock and a delayed feedback clock, the difference between the feedback clock and the delayed feedback clock is preset delay time, and after receiving the feedback clock and the delayed feedback clock from the feedback frequency dividing circuit, the double-phase discriminator carries out frequency dividing and delay processing on the first clock. Respectively generating a first signal and a second signal according to the reference clock, the feedback clock and the delay feedback clock, wherein the difference between the first signal and the second signal is preset delay time; and after receiving the first signal and the second signal from the two-phase discriminator, the charge pump outputs linearized current according to the first signal and the second signal. According to the invention, the performance of in-band phase noise can be improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of circuits, and particularly relates to a fractional-N phase-locked loop feedback circuit and a phase noise optimization method. BACKGROUND

[0002] At present, a Sigma-delta modulator is arranged in a traditional fractional-N phase-locked loop circuit, noise is pushed to a high frequency by the Sigma-delta modulator, low-pass filtering is performed on the noise by a loop filter, the high-frequency noise is filtered out, and then noise shaping is realized.

[0003] However, due to the action of the Sigma-delta modulator, when rising edges of different clock cycles arrive, the phase of the signal output after frequency division is advanced or lagged compared with the phase of the reference input signal, and the change range changes with the Sigma-delta modulator. In this case, when the charge pump is mismatched, the noise at the high frequency of the Sigma-delta modulator may be folded into the loop bandwidth, and the in-band phase noise performance is deteriorated. SUMMARY

[0004] The application embodiment provides a fractional-N phase-locked loop feedback circuit and a phase noise optimization method, and can solve the problem that the noise at the high frequency of the Sigma-delta modulator is folded into the loop bandwidth, and the in-band phase noise performance is deteriorated.

[0005] In a first aspect, the application embodiment provides a fractional-N phase-locked loop feedback circuit, comprising: a voltage-controlled oscillator, a feedback frequency division circuit, a dual-phase phase detector and a charge pump which are electrically connected in sequence. The voltage-controlled oscillator is configured to generate a first clock. The feedback frequency division circuit is configured to receive the first clock from the voltage-controlled oscillator, perform frequency division and delay processing on the first clock, and obtain a feedback clock and a delayed feedback clock, wherein the feedback clock and the delayed feedback clock are different by a preset delay time. The dual-phase phase detector is configured to receive the feedback clock and the delayed feedback clock from the feedback frequency division circuit, generate a first signal and a second signal according to a reference clock, the feedback clock and the delayed feedback clock, respectively, and the first signal and the second signal are different by the preset delay time. The charge pump is configured to receive the first signal and the second signal from the dual-phase phase detector, and output a linearized current according to the first signal and the second signal.

[0006] In one embodiment, the feedback frequency divider circuit comprises a K / K+1 prescaler, an N divider and a delay generation circuit, the K / K+1 prescaler is electrically connected with the voltage controlled oscillator, the N divider and the delay generation circuit respectively, the N divider is electrically connected with the delay generation circuit and the dual-phase phase detector respectively, and the delay generation circuit is electrically connected with the dual-phase phase detector; The K / K+1 prescaler is configured to receive a first clock from the voltage controlled oscillator; The K / K+1 prescaler is further configured to perform a division by K operation according to the first clock to obtain a second clock when no control signal is received from the delay generation circuit; The K / K+1 prescaler is further configured to perform a division by K+1 operation according to the first clock to obtain a third clock when the control signal is received from the delay generation circuit; The N divider is configured to receive the second clock or the third clock from the K / K+1 prescaler; The N divider is further configured to perform a frequency division operation according to the second clock and / or the third clock at an N division ratio to obtain the feedback clock and output the feedback clock to the dual-phase phase detector; The delay generation circuit is further configured to start according to the feedback clock; The delay generation circuit is configured to receive the second clock or the third clock from the K / K+1 prescaler after starting; The delay generation circuit is further configured to generate the delayed feedback clock according to one of the second clock and the third clock according to a delay configuration; The delay generation circuit is further configured to output the delayed feedback clock to the dual-phase phase detector; The delay generation circuit is further configured to generate the control signal according to a feedback frequency division ratio and output the control signal to the K / K+1 prescaler.

[0007] In one embodiment, the delay generation circuit comprises a delay counter and a flip-flop array, the delay counter is electrically connected with the K / K+1 prescaler, the N divider and the flip-flop array respectively, and the flip-flop array is electrically connected with the dual-phase phase detector; The delay counter is configured to receive the second clock or the third clock from the K / K+1 prescaler after starting; The delay counter is further configured to generate a to-be-processed clock according to the second clock or the third clock according to a first preset configuration; The delay counter is further configured to generate the control signal according to a feedback frequency division ratio and output the control signal to the K / K+1 prescaler; The trigger array is configured to, after receiving the to-be-processed clock from the delay counter, perform delay processing on the to-be-processed clock according to a second preset configuration to obtain the delay feedback clock, and the delay configuration includes the first preset configuration and the second preset configuration. The circuit is further configured to output the delay feedback clock to the bidirectional phase detector.

[0008] In an embodiment, the first preset configuration is determined according to an order of a Sigma-delta modulator and a value range of a target fractional division ratio.

[0009] In an embodiment, the second preset configuration is determined according to a timing convergence condition of the feedback division circuit.

[0010] In an embodiment, the first preset configuration includes a bit number of the delay counter, the second preset configuration includes a number of triggers, and the preset delay time is determined according to the bit number of the delay counter, the number of triggers, and a clock period of a K / K+1 prescaler.

[0011] In an embodiment, the bidirectional phase detector includes a UP phase detector and a DN phase detector. The UP phase detector is configured to, after receiving the reference clock and a feedback clock of the feedback division circuit, generate the first signal according to the reference clock and the feedback clock. The circuit is further configured to output the first signal to the charge pump. The DN phase detector is configured to, after receiving the reference clock and a delay feedback clock from the feedback division circuit, generate the second signal according to the reference clock and the delay feedback clock. The circuit is further configured to output the second signal to the charge pump.

[0012] In a second aspect, an embodiment of the present application provides a phase noise optimization method, applied to the circuit in any of the first aspect, and including: The voltage-controlled oscillator generates a first clock; The feedback division circuit is configured to, after receiving the first clock from the voltage-controlled oscillator, perform division and delay processing on the first clock to obtain a feedback clock and a delay feedback clock, and the feedback clock and the delay feedback clock are different by a preset delay time. The bidirectional phase detector is configured to, after receiving the feedback clock and the delay feedback clock from the feedback division circuit, generate a first signal and a second signal according to a reference clock, the feedback clock, and the delay feedback clock, respectively, and the first signal and the second signal are different by the preset delay time. The charge pump outputs a linearized current according to the first signal and the second signal after receiving the first signal and the second signal from the dual-phase phase detector.

[0013] In one embodiment, the feedback frequency divider receives a first clock from the voltage-controlled oscillator, divides and delays the first clock to obtain a feedback clock and a delayed feedback clock, and comprises: The K / K+1 pre-divider receives the first clock from the voltage-controlled oscillator, performs a division-by-K operation according to the first clock to obtain a second clock when no control signal is received from the delay generation circuit, and performs a division-by-K+1 operation according to the first clock to obtain a third clock when the control signal is received from the delay generation circuit; The N divider receives the second clock or the third clock from the K / K+1 pre-divider, performs a division operation according to the second clock and / or the third clock at an N division ratio to obtain the feedback clock, and outputs the feedback clock to the dual-phase phase detector; and starts the delay generation circuit according to the feedback clock; The delay generation circuit, after being started, receives the second clock or the third clock from the K / K+1 pre-divider, generates the delayed feedback clock according to one of the second clock and the third clock according to a delay configuration, outputs the delayed feedback clock to the dual-phase phase detector, and generates the control signal according to a feedback division ratio and outputs the control signal to the K / K+1 pre-divider.

[0014] In one embodiment, the dual-phase phase detector receives the feedback clock and the delayed feedback clock from the feedback frequency divider, and generates a first signal and a second signal according to a reference clock, the feedback clock and the delayed feedback clock, respectively, and comprises: The UP phase detector receives the reference clock and the feedback clock of the feedback frequency divider, generates the first signal according to the reference clock and the feedback clock, and outputs the first signal to the charge pump; The DN phase detector receives the reference clock and the delayed feedback clock from the feedback frequency divider, generates the second signal according to the reference clock and the delayed feedback clock, and outputs the second signal to the charge pump.

[0015] Compared with the prior art, the embodiments of the present application have the beneficial effects that: The application receives a first clock from a voltage-controlled oscillator through a feedback frequency division circuit, performs frequency division and delay processing on the first clock, obtains a feedback clock and a delayed feedback clock, the feedback clock and the delayed feedback clock are different by a preset delay time, and a dual-phase phase discriminator receives the feedback clock and the delayed feedback clock from the feedback frequency division circuit, generates a first signal and a second signal according to a reference clock, the feedback clock and the delayed feedback clock respectively, the first signal and the second signal are different by a preset delay time, the phase difference between the signals input into the circuit is increased, the charge pump outputs a linearized current according to the first signal and the second signal, the mismatch of the charge pump is reduced, and the performance of the in-band phase noise is improved.

[0016] It can be understood that the beneficial effects of the second aspect described above can be referred to the related description in the first aspect described above, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0018] Figure 1 is a schematic diagram of the charge pump transfer function under the existing circuit structure; Figure 2 is a first structure schematic diagram of the fractional-N phase-locked loop feedback clock provided by an embodiment of the present application; Figure 3 is a first example diagram of the frequency division of the feedback frequency division circuit provided by an embodiment of the present application; Figure 4 is a second example diagram of the frequency division of the feedback frequency division circuit provided by an embodiment of the present application; Figure 5 is a third example diagram of the frequency division of the feedback frequency division circuit provided by an embodiment of the present application; Figure 6 is a second structure schematic diagram of the fractional-N phase-locked loop feedback clock provided by an embodiment of the present application; Figure 7 is a schematic diagram of each clock and each signal provided by an embodiment of the present application; Figure 8 is a schematic diagram of the charge pump transfer function of the fractional-N phase-locked loop feedback clock provided by an embodiment of the present application; Figure 9 is a first schematic diagram of the optimization of the in-band phase noise provided by an embodiment of the present application; Figure 10is a second diagram of an in-band phase noise optimization case provided by an embodiment of the present application; Figure 11 is a diagram of a preset delay time selected too large provided by an embodiment of the present application; Figure 12 is a diagram of a preset delay time selected optimally provided by an embodiment of the present application; Figure 13 is a flow diagram of a phase noise optimization method provided by an embodiment of the present application. DETAILED DESCRIPTION

[0019] In the following description, for the purposes of explanation, numerous specific details are set forth in order to thoroughly describe certain embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known methods, devices, and apparatuses are omitted so as not to obscure the description of the present application.

[0020] It is to be understood that the terminology "includes", "has", "holds", "contains" and / or "comprising", when used in this specification and in the following claims, indicates the presence of the described features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0021] It is also to be understood that the terminology "and / or" when used in this specification and in the following claims, refers to at least one of the items, or any combination of one or more of the items, and includes any possible combination of the items.

[0022] As used in this specification and in the claims, the terms "if" and "when" can be interpreted to mean "upon" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [a described condition or event] is detected" can be interpreted to mean "upon determining" or "in response to determining" or "upon detecting [a described condition or event]" or "in response to detecting [a described condition or event]", depending on the context.

[0023] In addition, in the description of the application and in the claims, the terms "first", "second", "third", etc. are used merely to identify corresponding components, and cannot be interpreted as indicating or implying relative importance.

[0024] Reference within the specification of this application to "one embodiment" or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase "in one embodiment" or "in some embodiments" in various places within specified

[0025] In a conventional fractional-N phase-locked loop circuit, due to the action of the Sigma-delta modulator, the phase of the output signal after frequency division at the rising edge of different clock cycles is advanced or delayed compared with the phase of the reference input signal, and the variation range changes with the Sigma-delta modulator. In this case, when the charge pump is mismatched, the noise at the high frequency of the Sigma-delta modulator may be folded into the loop bandwidth, deteriorating the in-band phase noise performance.

[0026] Specifically, the maximum absolute value of the value of the k-order Sigma-delta modulator is 2 k-1 . Please refer to Figure 1 As Figure 1 shown, with the output of the Sigma-delta modulator sequence, the position falls on the transfer curve of the charge pump with different slopes. Due to the nonlinearity of the transfer curve, the charge pump is statically mismatched. If the charge pump is nonlinearly mismatched, the noise at the high frequency of the Sigma-delta modulator may be folded into the loop bandwidth, deteriorating the in-band noise performance of the phase-locked loop closed loop, and the deterioration is higher in the case of wide loop bandwidth.

[0027] For example, when the Sigma-delta modulator is 3-order, the value range is [-3, 4], and the delay range is [-3, 4] output clock cycles , if the charge pump is nonlinearly mismatched, the noise at the high frequency of the Sigma-delta modulator may be folded into the loop bandwidth.

[0028] In one embodiment, please refer to Figure 2 . As Figure 2 shown, the circuit comprises a voltage-controlled oscillator, a feedback frequency division circuit, a dual-phase phase detector and a charge pump connected in sequence.

[0029] The voltage-controlled oscillator is configured to generate a first clock.

[0030] The feedback frequency division circuit is configured to receive the first clock from the voltage-controlled oscillator, divide and delay the first clock, and obtain a feedback clock and a delayed feedback clock, wherein the feedback clock and the delayed feedback clock are different by a preset delay time.

[0031] In one possible implementation, the feedback frequency division circuit comprises a K / K+1 prescaler, an N divider, and a delay generation circuit, the K / K+1 prescaler is electrically connected to the voltage-controlled oscillator, the N divider, and the delay generation circuit, the N divider is electrically connected to the delay generation circuit and the dual-phase phase detector, and the delay generation circuit is electrically connected to the dual-phase phase detector.

[0032] In application, the K / K+1 prescaler selects a target frequency division mode based on a control signal of the delay generation circuit, the frequency division mode is a division by K mode or a division by K+1 mode. The N divider divides the clock output by the K / K+1 prescaler to generate a feedback clock, and starts the delay generation circuit according to the feedback clock. The delay generation circuit generates a delayed feedback clock different from the feedback clock by a preset delay time, and generates a control signal according to a feedback frequency division ratio to change the frequency division mode of the K / K+1 prescaler.

[0033] The K / K+1 prescaler is configured to receive the first clock from the voltage-controlled oscillator; The K / K+1 prescaler is further configured to perform a division by K operation according to the first clock to obtain a second clock when the control signal from the delay generation circuit is not received; The K / K+1 prescaler is further configured to perform a division by K+1 operation according to the first clock to obtain a third clock when the control signal from the delay generation circuit is received.

[0034] In application, the K / K+1 prescaler receives the clock output by the voltage-controlled oscillator, i.e., the first clock, after being started. When the control signal output by the delay generation circuit is not received, the frequency division mode of the K / K+1 prescaler is maintained in the division by K mode, K first clocks are received to generate one clock, i.e., the second clock. When the control signal output by the delay generation circuit is received, the frequency division mode of the K / K+1 prescaler is switched from the division by K mode to the division by K+1 mode, K+1 first clocks are received to generate one clock, i.e., the third clock. If the control signal is not received by the K / K+1 prescaler, the frequency division mode is switched back to the division by K mode in the next cycle. The K / K+1 prescaler outputs one clock to the N divider and the delay generation circuit.

[0035] The N divider is configured to receive the second clock or the third clock from the K / K+1 prescaler; The N divider is further configured to perform a frequency division operation according to the second clock and / or the third clock according to an N frequency division ratio to obtain a feedback clock, and output the feedback clock to the dual-phase phase detector; The N divider is further configured to start the delay generation circuit according to the feedback clock.

[0036] In application, the N divider starts to receive the clock outputted by the K / K+1 pre-divider. A preset number of the clock outputted by the K / K+1 pre-divider is received to generate a clock, i.e. the feedback clock. The preset number is set according to the N division ratio. When the feedback clock is generated, the rising edge of the feedback clock is used to start the delay generation circuit, so that the delay generation circuit generates the delayed feedback clock with a preset delay time from the feedback clock in the case of different division ratios set by the N divider.

[0037] The delay generation circuit is configured to, after starting, receive the second clock or the third clock from the K / K+1 pre-divider; and further configured to generate the delayed feedback clock according to one of the second clock and the third clock according to the delay configuration; and further configured to output the delayed feedback clock to the bidirectional phase detector; and further configured to generate the control signal according to the feedback division ratio and output the control signal to the K / K+1 pre-divider.

[0038] In application, the delay generation circuit is controlled to start by the N divider to receive the clock outputted by the K / K+1 pre-divider, so that the delay generation circuit generates the clock according to the delay configuration, which is the same as the clock of the K / K+1 pre-divider. Specifically, according to the delay configuration, the delay generation circuit receives the second clock to generate a delayed feedback clock with the same pulse width as the second clock and a preset delay time from the feedback clock, or the delay generation circuit receives the third clock to generate a delayed feedback clock with the same pulse width as the third clock and a preset delay time from the feedback clock.

[0039] and the delay generation circuit is controlled to start by the N divider to generate the control signal according to the feedback division ratio, so that the K / K+1 pre-divider performs the K+1 operation in the next cycle.

[0040] In a possible implementation, the delay generation circuit includes a delay counter and a flip-flop array, the delay counter is electrically connected to the K / K+1 pre-divider, the N divider and the flip-flop array respectively, and the flip-flop array is electrically connected to the bidirectional phase detector.

[0041] The delay counter is configured to, after starting, receive the second clock or the third clock from the K / K+1 pre-divider; and further configured to generate the to-be-processed clock according to the second clock or the third clock according to the first preset configuration; and further configured to generate the control signal according to the feedback division ratio and output the control signal to the K / K+1 pre-divider.

[0042] In application, the delay counter generates a to-be-processed clock with a pulse width same as that of the second clock if the second clock is received, and generates a to-be-processed clock with a pulse width same as that of the third clock if the third clock is received after delaying for a first preset delay time.

[0043] When the feedback division ratio is composed of the second clock and the third clock, the delay counter calculates the number of clocks according to the received clock, and generates and outputs the control signal when the number of clocks satisfies the condition of the control signal.

[0044] The flip-flop array delays the to-be-processed clock according to a second preset configuration to obtain a delay feedback clock after receiving the to-be-processed clock from the delay counter. The delay feedback clock is also output to the bidirectional phase discriminator.

[0045] In application, the flip-flop array physically delays the to-be-processed clock for a second preset delay time, and adjusts the timing constraint condition of the feedback division circuit through the physical delay to reduce the case that the modulation sequence changes when the division occurs, thereby reducing the stray energy affecting the output.

[0046] The delay configuration includes a first preset configuration and a second preset configuration. The delay counter is an M-bit register, the first preset configuration is a preset configuration of the M-bit register, the phase difference is 2 M The delay time of the delay counter can be adjusted within a certain range, and the phase difference between the to-be-processed clock generated by the delay counter and the feedback clock is 2 M The flip-flop array is composed of a plurality of flip-flops, and the second preset configuration is a preset flip-flop configuration of the flip-flop array.

[0047] Specifically, the first preset configuration includes the number of bits of the delay counter, the second preset configuration includes the number of flip-flops, and the preset delay time is determined according to the number of bits of the delay counter, the number of flip-flops, and the clock period of the K / K+1 prescaler.

[0048] The preset delay time of the delay feedback clock obtained through the delay of the delay counter and the flip-flop array is expressed as: Wherein, A is the number of flip-flops in the flip-flop array, B is the corresponding value of the M-bit delay counter, TK / K+1 is the clock period of the K / K+1 prescaler, and is the second clock or the third clock.

[0049] In order to better understand the frequency division of the feedback frequency division circuit, the following examples are used for illustration. In the examples, the K / K+1 pre- frequency divider is a 4 / 5 pre-frequency divider, the frequency division control word of the K / K+1 pre-frequency divider is 1, the corresponding frequency division mode is the division by 5 mode, the frequency division control word of the K / K+1 pre-frequency divider is 0, the corresponding frequency division mode is the division by 4 mode, the N frequency divider has an N frequency division ratio of 5, and the preset delay time is 2T4 / 5.

[0050] Example 1, please refer to Figure 3 As shown in Figure 3 , when the feedback frequency division ratio is 20 (4-4-4-4-4) and the 4 / 5 pre-frequency divider initially outputs the second clock, the N frequency divider generates a feedback clock. The rising edge of the feedback clock acts on the delay generation circuit to start the delay generation circuit. The delay generation circuit generates a delay feedback clock having a pulse width same as that of the second clock and being different from the feedback clock by 2T4. After the 4 / 5 pre-frequency divider outputs 5 clocks, the N frequency divider generates a feedback clock.

[0051] Example 2, please refer to Figure 4 As shown in Figure 4 , when the feedback frequency division ratio is 21 (4-4-5-4-4) and the 4 / 5 pre-frequency divider initially outputs the second clock, the N frequency divider generates a feedback clock. The rising edge of the feedback clock acts on the delay generation circuit to start the delay generation circuit. The delay generation circuit generates a control signal = 1 according to the preset frequency division ratio after 2T4, and outputs the control signal to the 4 / 5 pre-frequency divider to make the 4 / 5 pre-frequency divider output the third clock in the next cycle, and generates a delay feedback clock having a pulse width same as that of the third clock and being different from the feedback clock by 2T4. After the 4 / 5 pre-frequency divider outputs 5 clocks, the N frequency divider generates a feedback clock.

[0052] Example 3, please refer to Figure 5 As shown in Figure 5 , when the feedback frequency division ratio is 22 (4-4-5-5-4) and the 4 / 5 pre-frequency divider initially outputs the second clock, the N frequency divider generates a feedback clock. The rising edge of the feedback clock acts on the delay generation circuit to start the delay generation circuit. The delay generation circuit generates a control signal = 1 according to the preset frequency division ratio after 2T4, and outputs the control signal to the 4 / 5 pre-frequency divider to make the 4 / 5 pre-frequency divider output the third clock in the next cycle, and generates a delay feedback clock having a pulse width same as that of the third clock and being different from the feedback clock by 2T4. Then the delay generation circuit continues to generate a control signal = 1 according to the preset frequency division ratio after 2T4 and 1T5, and outputs the control signal to the 4 / 5 pre-frequency divider to make the 4 / 5 pre-frequency divider continue to output the third clock in the next cycle. After the 4 / 5 pre-frequency divider outputs 5 clocks, the N frequency divider generates a feedback clock.

[0053] The dual-phase phase detector is configured to generate a first signal and a second signal according to a reference clock, a feedback clock and a delayed feedback clock after receiving the feedback clock and the delayed feedback clock from the feedback frequency division circuit, and a preset delay time is between the first signal and the second signal.

[0054] In a possible implementation, referring to FIG. 6, as shown in the figure, the dual-phase phase detector includes a UP phase detector and a DN phase detector. Figure 6

[0055] The UP phase detector is configured to generate a first signal according to a reference clock and a feedback clock of a feedback frequency division circuit after receiving the reference clock and the feedback clock. The UP phase detector is further configured to output the first signal to a charge pump.

[0056] The first signal is a UP pulse signal.

[0057] The DN phase detector is configured to generate a second signal according to a reference clock and a delayed feedback clock from a feedback frequency division circuit after receiving the reference clock and the delayed feedback clock. The DN phase detector is further configured to output the second signal to the charge pump.

[0058] The second signal is a DN pulse signal.

[0059] For better understanding of the conditions of the clocks and the signals, referring to FIG. 6, as shown in the figure, Figure 7 when the circuit is stable, the reference clock is in a middle position between the feedback clock and the delayed feedback clock, a phase difference between the reference clock and the feedback clock is Figure 7 The UP2 pulse signal is generated by the reference clock and the feedback clock. The DN1 pulse signal is generated by the reference clock and the delayed feedback clock. A rising edge of the UP2 pulse signal and a rising edge of the DN1 pulse signal are different by a preset delay time. The charge pump is configured to output a linearization current according to the first signal and the second signal after receiving the first signal and the second signal from the dual-phase phase detector.

[0060] In application, because the feedback clock and the delayed feedback clock are different by a preset delay time, the first signal and the second signal are different by the preset delay time. The charge pump can linearize a transfer function according to the first signal and the second signal, and output the linearization current in a charging and discharging process.

[0061] Specifically, referring to FIG. 6, as shown in the figure,

[0062] when the charge pump is in a steady state, an expression of a charge quantity is Figure 8 Figure 8 ​​​, IDN is the current generated according to the DN pulse signal, IUP is the current generated according to the UP pulse signal, the slope is IDN+IUP, which is equivalent to increasing the gain of the charge pump, and improving the in-band phase noise performance of the feedback circuit.

[0063] For example, when the phase difference between the reference clock and the feedback clock is 0 to , the gain of the charge pump is increased to IDN+IUP. When IDN=IUP, it is equivalent to increasing the gain of the charge pump by 2 times, that is, linearizing the transfer function helps the charge pump to obtain a gain value of 2 times without changing the configuration.

[0064] The embodiment increases the phase difference between the signals of the input circuit by the feedback frequency division circuit, and then adjusts the timing and pulse width of the first signal and the second signal generated by the dual-phase phase discriminator, so that the first signal and the second signal have a preset delay time, so that the charge pump outputs a linearized current according to the first signal and the second signal, reduces the mismatch of the charge pump, and improves the in-band phase noise performance.

[0065] The optimization of the in-band phase noise can refer to Figure 9 and Figure 10 . As shown in Figure 9 , line 1 is the in-band phase noise of the circuit described in the embodiment, and line 2 is the in-band phase noise of the existing circuit. At the in-band 10kHz frequency offset, the in-band phase noise of line 1 is optimized by about 6dB of phase noise performance compared with line 2. As shown in Figure 10 , at 100kHz, the in-band phase noise of line 1 is optimized by about 3dB of phase noise performance compared with line 2.

[0066] It can be understood that the existing method for solving the mismatch of the non-ideal characteristics of the charge pump is to apply a bias current at the output end of the charge pump, optimize the non-linearity of the charge pump, and use the solution. A larger charge pump current is required, which improves the phase noise performance while increasing the reference spur. By increasing the phase difference between the signals of the input circuit through the feedback frequency division circuit and the dual-phase discriminator, the transfer function of the charge pump can be linearized, so that the charge pump can output a linearized current without additional current. It can better optimize the phase noise and not increase the reference spur.

[0067] In one embodiment, the first preset configuration is determined according to the order of the Sigma-delta modulator and the value range of the target fractional division ratio.

[0068] In application, please refer to Figure 11 . As Figure 11As shown, for different fractional division ratios of a certain order of the Sigma-delta, when the selected fractional division ratio corresponds to a value range of the Sigma-delta modulator sequence that is smaller than the preset delay time Δt range, if the value of the delay counter B is adjusted according to the theoretical maximum value range of the Sigma-delta modulator sequence, the increase of Δt may deteriorate the reference spur and charge pump performance, and the phase noise of the Sigma-delta modulator may not be continuously optimized, and thus a relatively optimal phase noise performance may be obtained.

[0069] Please refer to Figure 12 As shown, Figure 12 Therefore, the configuration of the delay counter needs to be dynamically adjusted in combination with the order of the specific Sigma-delta modulator and the value range of the current fractional division ratio, corresponding to dynamically adjusting the B of the delay counter, obtaining the optimal first preset configuration, obtaining the optimal preset delay time, and thus obtaining a better phase noise performance.

[0070] The embodiment can obtain a better configuration of the delay counter by determining the first preset configuration according to the order of the Sigma-delta modulator and the value range of the target fractional division ratio, providing a basis for obtaining a better delay configuration of the preset delay time, and better optimizing the in-band phase noise performance.

[0071] In one embodiment, the second preset configuration is determined according to the timing convergence of the feedback division circuit.

[0072] In application, the flip-flop array is determined according to the timing convergence of the circuit design, and is used for the timing constraint condition of the feedback division circuit.

[0073] The embodiment can obtain a better configuration of the flip-flop array by determining the second preset configuration according to the timing convergence of the feedback division circuit, and better optimize the in-band phase noise performance.

[0074] It should be noted that the information interaction, execution process and the like between the above-mentioned devices / units are based on the same concept as the method embodiments of the present application, and the specific functions and technical effects brought by them can be referred to the method embodiments part, which will not be repeated here.

[0075] Corresponding to the circuit described in the above embodiments, only the parts related to the embodiments of the present application are shown for ease of description.

[0076] In one embodiment, please refer to Figure 13 As shown, Figure 13 The method is applied to the circuit described in each of the above embodiments, and includes: S11: a voltage-controlled oscillator generates a first clock.

[0077] S12: a feedback frequency divider receives the first clock from the voltage-controlled oscillator, and performs frequency division and delay processing on the first clock to obtain a feedback clock and a delayed feedback clock.

[0078] wherein the feedback clock and the delayed feedback clock are different by a preset delay time; S13: a dual-phase phase detector receives the feedback clock and the delayed feedback clock from the feedback frequency divider, and generates a first signal and a second signal according to a reference clock, the feedback clock and the delayed feedback clock.

[0079] wherein the first signal and the second signal are different by a preset delay time; S14: a charge pump receives the first signal and the second signal from the dual-phase phase detector, and outputs a linearization current according to the first signal and the second signal.

[0080] In one embodiment, step S12 comprises: S121: a K / K+1 pre-divider receives the first clock from the voltage-controlled oscillator; when no control signal is received from a delay generation circuit, performs a division-by-K operation according to the first clock to obtain a second clock; and when the control signal is received from the delay generation circuit, performs a division-by-K+1 operation according to the first clock to obtain a third clock.

[0081] S122: an N divider receives the second clock or the third clock from the K / K+1 pre-divider; performs a frequency division operation according to the second clock and / or the third clock according to an N division ratio to obtain the feedback clock, and outputs the feedback clock to the dual-phase phase detector; and starts the delay generation circuit according to the feedback clock. S123: the delay generation circuit, after being started, receives the second clock or the third clock from the K / K+1 pre-divider; generates the delayed feedback clock according to one of the second clock and the third clock according to a delay configuration; outputs the delayed feedback clock to the dual-phase phase detector; and generates the control signal according to a feedback division ratio, and outputs the control signal to the K / K+1 pre-divider.

[0082] In one embodiment, step S123 comprises: S21: a delay counter, after being started, receives the second clock or the third clock from the K / K+1 pre-divider; generates a to-be-processed clock according to the second clock or the third clock according to a first preset configuration; and generates the control signal according to a feedback division ratio, and outputs the control signal to the K / K+1 pre-divider; S22: After the flip-flop array receives the clock to be processed from the delay counter, the clock to be processed is processed according to the second preset configuration, a delay feedback clock is obtained, and the delay feedback clock is output to the bidirectional phase detector.

[0083] The delay configuration includes the first preset configuration and the second preset configuration.

[0084] In one embodiment, step S13 includes: S131: After the UP phase detector receives the reference clock and the feedback clock from the feedback frequency division circuit, the UP phase detector generates a first signal according to the reference clock and the feedback clock, and outputs the first signal to the charge pump. S132: After the DN phase detector receives the reference clock and the delay feedback clock from the feedback frequency division circuit, the DN phase detector generates a second signal according to the reference clock and the delay feedback clock, and outputs the second signal to the charge pump.

[0085] It should be understood that the size of the serial number of each step in the above embodiment does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The collection of data in the above embodiment is in compliance, and its use or implementation does not involve the infringement of public interests.

[0086] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above functional units and modules is exemplified, and in actual application, the above functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit or module in the embodiment can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The above integrated unit can be realized in the form of hardware or in the form of software functional unit. In addition, the specific name of each functional unit or module is only for easy distinction, and does not limit the protection scope of the present application. The specific working process of the unit or module in the above system can be referred to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0087] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the present application can implement all or part of the processes in the above-mentioned embodiment methods through a computer program to instruct relevant hardware to complete, and the computer program can be stored in a computer readable storage medium. When the computer program is executed by a processor, the steps of each method embodiment described above can be implemented. The computer program includes computer program code, which can be in the form of source code, object code, executable files or some intermediate forms. The computer readable medium at least includes any entity or device capable of carrying the computer program code to the photographing device / terminal equipment, recording medium, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal and software distribution medium. For example, U disk, mobile hard disk, magnetic disk or optical disk, etc. In some cases, the computer readable medium can not be an electrical carrier signal and a telecommunication signal.

[0088] In the above embodiments, the description of each embodiment has its own focus, and the parts not described or recorded in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0089] Those skilled in the art can appreciate that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented in electronic hardware or a combination of computer software and electronic hardware. Whether the functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0090] In the embodiments provided in the present application, it should be understood that the disclosed apparatus / network device and method can be implemented in other ways. For example, the apparatus / network device embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection between each other can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other forms.

[0091] The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may also be distributed to multiple network units. Part or all of the units can be selected to achieve the purpose of the embodiment scheme according to actual needs.

[0092] The above embodiments are only used to illustrate the technical solutions of the present application, but not limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A fractional-frequency division phase-locked loop feedback circuit, characterized in that, include: A voltage-controlled oscillator, a feedback frequency divider circuit, a two-phase phase detector, and a charge pump are connected in sequence. The voltage-controlled oscillator is used to generate the first clock; The feedback frequency divider circuit is used to receive a first clock from the voltage-controlled oscillator, divide and delay the first clock to obtain a feedback clock and a delayed feedback clock, wherein the feedback clock and the delayed feedback clock differ by a preset delay time. The dual-phase detector is used to receive the feedback clock and the delayed feedback clock from the feedback frequency divider circuit, and then generate a first signal and a second signal according to the reference clock, the feedback clock and the delayed feedback clock, respectively, wherein the first signal and the second signal are separated by the preset delay time. The charge pump is used to receive a first signal and a second signal from the dual-phase detector, and then output a linearized current based on the first signal and the second signal.

2. The circuit according to claim 1, characterized in that, The feedback frequency division circuit includes a K / K+1 prescaler, an N-divider, and a delay generation circuit. The K / K+1 prescaler is electrically connected to the voltage-controlled oscillator, the N-divider, and the delay generation circuit, respectively. The N-divider is electrically connected to the delay generation circuit and the dual-phase phase detector, respectively. The delay generation circuit is electrically connected to the dual-phase phase detector. The K / K+1 prescaler is used to receive the first clock from the voltage-controlled oscillator; It is also used to perform a division by K operation based on the first clock to obtain a second clock when no control signal is received from the delay generation circuit; It is also used to perform a division by K+1 operation based on the first clock to obtain a third clock when a control signal is received from the delay generation circuit; The N divider is used to receive the second clock or the third clock from the K / K+1 prescaler; It is also used to perform a frequency division operation according to the second clock and / or the third clock according to the N-division ratio, obtain the feedback clock, and output the feedback clock to the bidirectional phase detector; It is also used to start the delay generation circuit according to the feedback clock; The delay generation circuit is used to receive a second clock or a third clock from the K / K+1 prescaler after startup. It is also used to generate the delay feedback clock according to one of the second clock and the third clock, based on the delay configuration; It is also used to output the delayed feedback clock to the bidirectional phase detector; It is also used to generate the control signal according to the feedback division ratio and output the control signal to the K / K+1 prescaler.

3. The circuit according to claim 2, characterized in that, The delay generation circuit includes a delay counter and a trigger array. The delay counter is electrically connected to the K / K+1 prescaler, the N divider, and the trigger array, respectively. The trigger array is electrically connected to the dual-phase detector. The delay counter is used to receive a second or third clock from the K / K+1 prescaler after startup; It is also used to generate a clock to be processed according to the second clock or the third clock, based on the first preset configuration; It is also used to generate the control signal according to the feedback division ratio, and output the control signal to the K / K+1 prescaler; The trigger array is used to receive the clock to be processed from the delay counter, and then perform delay processing on the clock to be processed according to the second preset configuration to obtain the delay feedback clock. The delay configuration includes the first preset configuration and the second preset configuration. It is also used to output the delayed feedback clock to the bidirectional phase detector.

4. The circuit according to claim 3, characterized in that, The first preset configuration is determined based on the order of the Sigma-delta modulator and the range of the target fractional division ratio.

5. The circuit according to claim 4, characterized in that, The second preset configuration is determined based on the timing convergence of the feedback frequency divider circuit.

6. The circuit according to claim 5, characterized in that, The first preset configuration includes the number of bits in the delay counter, the second preset configuration includes the number of triggers, and the preset delay time is determined based on the number of bits in the delay counter, the number of triggers, and the clock period of the K / K+1 prescaler.

7. The circuit according to any one of claims 1 to 6, characterized in that, The dual-phase detector includes a UP phase detector and a DN phase detector; The UP phase detector is used to receive the reference clock and the feedback clock of the feedback frequency divider circuit, and then generate the first signal based on the reference clock and the feedback clock. It is also used to output the first signal to the charge pump; The DN phase detector is used to receive the reference clock and the delayed feedback clock from the feedback frequency divider circuit, and then generate the second signal based on the reference clock and the delayed feedback clock. It is also used to output the second signal to the charge pump.

8. A phase noise optimization method, characterized in that, Applied to the circuit according to any one of claims 1 to 7, comprising: The voltage-controlled oscillator generates the first clock; After receiving the first clock from the voltage-controlled oscillator, the feedback frequency divider circuit divides and delays the first clock to obtain a feedback clock and a delayed feedback clock. The feedback clock and the delayed feedback clock differ by a preset delay time. After receiving the feedback clock and the delayed feedback clock from the feedback frequency divider circuit, the dual-phase phase detector generates a first signal and a second signal according to the reference clock, the feedback clock and the delayed feedback clock, respectively, with the first signal and the second signal differing by the preset delay time. After receiving the first and second signals from the dual-phase detector, the charge pump outputs a linearized current based on the first and second signals.

9. The method according to claim 8, characterized in that, After receiving a first clock from the voltage-controlled oscillator, the feedback frequency divider circuit performs frequency division and delay processing on the first clock to obtain a feedback clock and a delayed feedback clock, including: The K / K+1 prescaler receives a first clock from the voltage-controlled oscillator; when no control signal is received from the delay generation circuit, it performs a division by K operation based on the first clock to obtain a second clock; and when a control signal is received from the delay generation circuit, it performs a division by K+1 operation based on the first clock to obtain a third clock. The N-divider receives the second clock or the third clock from the K / K+1 prescaler; performs a division operation according to the N-division ratio based on the second clock and / or the third clock to obtain the feedback clock, and outputs the feedback clock to the bidirectional phase detector; and starts the delay generation circuit according to the feedback clock. After startup, the delay generation circuit receives a second clock or a third clock from the K / K+1 prescaler; generates the delay feedback clock according to the delay configuration and one of the second clock and the third clock; outputs the delay feedback clock to the bidirectional phase detector; and generates the control signal according to the feedback division ratio and outputs the control signal to the K / K+1 prescaler.

10. The method according to claim 8, characterized in that, After receiving the feedback clock and delayed feedback clock from the feedback frequency divider circuit, the dual-phase phase detector generates a first signal and a second signal according to the reference clock, the feedback clock, and the delayed feedback clock, respectively, including: After receiving the reference clock and the feedback clock from the feedback divider circuit, the UP phase detector generates the first signal based on the reference clock and the feedback clock, and outputs the first signal to the charge pump. After receiving the reference clock and the delayed feedback clock from the feedback divider circuit, the DN phase detector generates the second signal based on the reference clock and the delayed feedback clock, and outputs the second signal to the charge pump.

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