Phase-locked loop and chip

Abstract

The invention relates to the technical field of electronic circuits, and provides a phase-locked loop and a chip. According to the phase-locked loop, a charging control module is arranged between the input end of the phase-locked loop and a loop filter, and the charging control module receives a reference clock signal of the input end of the phase-locked loop and a feedback clock signal output by the phase-locked loop; the charging control module is used for charging the loop filter under the action of the reference clock signal and the feedback clock signal when the feedback clock signal meets a preset charging condition; wherein the locking time of the phase-locked loop is related to the charging time of the loop filter by the charging control module. According to the phase-locked loop, the loop characteristics of the rapidly locked phase-locked loop can be ensured, and the complexity of the circuit structure is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuits, and particularly relates to a phase-locked loop and a chip. BACKGROUND

[0002] With the continuous development of electronic technology, a phase-locked loop (PLL) is widely applied in various electronic systems to stabilize and control the frequency and phase of a signal, so as to meet various communication, data transmission and signal processing requirements. In electronic systems such as fast mobile devices and Bluetooth transceiver technology, the locking speed of the phase-locked loop has a significant influence on the start-up time of the system, and therefore it is particularly important to study a phase-locked loop with a fast locking function.

[0003] At present, mainstream fast locking designs focus on regulating the output current of a charge pump or the resistance and capacitance in a loop filter, but the circuit structure of such designs is usually complex and has a large area overhead. In addition, the loop characteristics of the phase-locked loop such as bandwidth, accuracy and stability are affected, and meanwhile, the locking of the mainstream phase-locked loop depends on the charge pump, but the charging of the charge pump is slow, and the locking time of the phase-locked loop is long, resulting in poor loop characteristics, long locking time and complex structure of the phase-locked loop with fast locking. SUMMARY

[0004] Embodiments of the present application provide a phase-locked loop and a chip, which can solve the problems of poor loop characteristics, long locking time and complex structure of the phase-locked loop with fast locking.

[0005] In a first aspect, the embodiments of the present application provide a phase-locked loop, a charge control module is arranged between an input end of the phase-locked loop and a loop filter, the charge control module receives a reference clock signal at the input end of the phase-locked loop and a feedback clock signal output by the phase-locked loop. The charge control module is configured to charge the loop filter under the action of the reference clock signal and the feedback clock signal when the feedback clock signal meets a preset charging condition, and the locking time of the phase-locked loop is related to the charging time of the charge control module to the loop filter.

[0006] Optionally, the charge control module comprises a frequency comparison unit and a charging unit. A first input end of the frequency comparison unit is connected with the input end of the phase-locked loop and configured to receive the reference clock signal, and a second input end of the frequency comparison unit is connected with a feedback output end of the phase-locked loop and configured to receive the feedback clock signal. A first control end of the charging unit is connected with a first output end of the frequency comparison unit, a second control end of the charging unit is connected with a second output end of the frequency comparison unit, a first output end of the charging unit is connected with a first end of the loop filter, and a second output end of the charging unit is connected with a second end of the loop filter. The frequency comparison unit is configured to generate a control signal according to the reference clock signal and the feedback clock signal, so as to control the charge-discharge state of the charging unit. The charging unit is configured to charge the loop filter under the action of the control signal, so as to increase the output voltage of the loop filter; wherein the amplitude variation rate of the output voltage is proportional to the charging rate of the loop filter.

[0007] Optionally, the frequency comparison unit comprises a frequency comparator. The first input end of the frequency comparator is connected with the input end of the phase-locked loop, the second input end of the frequency comparator is connected with the feedback output end of the phase-locked loop, the first output end of the frequency comparator is connected with the first control end of the charging unit, and the second output end of the frequency comparator is connected with the second control end of the charging unit. The frequency comparator is configured to generate a first control signal and a second control signal according to the reference clock signal and the feedback clock signal, so as to control the charge-discharge state of the charging unit. When the feedback clock signal meets a preset charging condition, the frequency comparator switches the control state of the first control signal and the second control signal according to the reference clock signal and the feedback clock signal.

[0008] Optionally, the charging unit comprises a first charging unit and a second charging unit. The control end of the first charging unit is connected with the first output end of the frequency comparator, and the output end of the first charging unit is connected with the first end of the second charging unit. The control end of the second charging unit is connected with the second output end of the frequency comparator, the second end of the second charging unit is connected with the first end of the loop filter, and the third end of the second charging unit is connected with the second end of the loop filter. The first charging unit is configured to charge the second charging unit according to the first control signal. The second charging unit is configured to charge the loop filter under the action of the second control signal and the first charging unit; wherein the first control signal and the second control signal are opposite.

[0009] Optionally, the first charging unit comprises a first power supply and a first switch. The control end of the first switch is connected with the first output end of the frequency comparator, the first end of the first switch is connected with the first end of the second charging unit, and the second end of the first switch is connected with the first power supply. When the first switch is turned on, the first power supply charges the second charging unit.

[0010] Optionally, the second charging unit comprises a second switch and a first capacitor. The control end of the second switch is connected with the second output end of the frequency comparator, the first end of the second switch is commonly connected with the output end of the first charging unit and the first end of the first capacitor, the second end of the second switch is connected with the first end of the loop filter, and the second end of the first capacitor is connected with the second end of the loop filter. When the second switch is turned on, the first capacitor charges the loop filter at a preset rate; wherein the closed state of the second switch is opposite to the closed state of the first switch, and the preset rate and the locking time of the phase-locked loop are related to the capacitance value of the first capacitor.

[0011] Optionally, the loop filter comprises a second capacitor, a third capacitor, a load and a second power supply. The first end of the second capacitor, the second end of the second switch and the second end of the load are commonly connected, the second end of the second capacitor, the second end of the first capacitor, the second power supply and the second end of the third capacitor are commonly connected, the first end of the load is connected with the first end of the third capacitor, and the commonly connected public end is commonly connected with the output end of the charge pump of the phase-locked loop and the input end of the voltage-controlled oscillator. Wherein, the total capacitance value of the first capacitor and the second capacitor after adding the capacitance values is a first preset value, the ratio of the capacitance value of the first capacitor to the total capacitance value is a second preset value, the preset rate and the locking time of the phase-locked loop are related to the second preset value, and the voltage of the first power supply is higher than the voltage of the second power supply.

[0012] Optionally, when the feedback clock signal does not satisfy the preset charging condition, the first control signal is low, and the level state of the first control signal and the second control signal is no longer switched.

[0013] Optionally, the preset charging condition is that the frequency of the feedback clock signal is less than a preset multiple of the frequency of the reference clock signal.

[0014] In a second aspect, an embodiment of the present application provides a chip comprising the phase-locked loop.

[0015] The above scheme of the present application has the following advantages: In the embodiment of the present application, the charging control module is arranged between the input end of the phase-locked loop and the loop filter, the charging control module receives the reference clock signal of the input end of the phase-locked loop and the feedback clock signal of the output of the phase-locked loop; the charging control module is used for charging the loop filter under the action of the reference clock signal and the feedback clock signal when the feedback clock signal satisfies the preset charging condition; wherein the locking time of the phase-locked loop is related to the time of the charging control module charging the loop filter. The charging control module can charge the loop filter, accelerate the locking of the phase-locked loop, has no influence on the loop characteristic after the fast start process is completed, and has simple circuit structure, easy realization and small circuit area cost. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings described below only illustrate some of the embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0017] Figure 1 A structure schematic diagram of a phase-locked loop provided by an embodiment of the present application is shown in the following figure. Figure 2 A level switching schematic diagram of a first control signal and a second control signal provided by an embodiment of the present application is shown in the following figure. Figure 3 A charging process schematic diagram provided by an embodiment of the present application is shown in the following figure. DETAILED DESCRIPTION

[0018] In the following description, specific details are set forth in order to provide a thorough understanding of embodiments of the present application. However, persons skilled in the art will understand that the present application can be practiced without these specific details, other embodiments can be used, and that the present application is not limited to the specifics described. In other instances, well-known systems, devices, circuits, and methods have not been described in detail so as not to unnecessarily obscure aspects of the present application.

[0019] It should be understood that the term "comprising" as used in the specification and the appended claims indicates the presence of the recited features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0020] It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items, and that the term "at least one of" follows a like meaning.

[0021] As used in the description of the application and the appended claims, the term "if' can be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting" depending on the context. Similarly, the phrase "if it is determined" or "if [a described condition or event] is detected" can be interpreted to mean "upon determining" or "in response to determining" or "upon [the described condition or event] being detected" or "in response to [the described condition or event] being detected", depending on the context.

[0022] In addition, in the description of the present application and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0023] Reference within the specification to "one embodiment" or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in one embodiment" or "in some embodiments" in various places within specifications are not necessarily all referring to the same embodiment, however, are meant to signify that "one or more, but not all embodiments" have the feature, structure or characteristic. The terms "including," "comprising," "having," and variations thereof are meant to encompass the items listed thereafter, but do not exclude additional, unrecited items. The terms "a" or "an," as used herein, mean "one or more" unless otherwise indicated.

[0024] In order to solve the problems of poor loop characteristics, long locking time and complex structure of the existing phase-locked loop, the phase-locked loop provided in the embodiments of the present application is provided with a charging control module between the input end of the phase-locked loop and the loop filter, the charging control module receives a reference clock signal at the input end of the phase-locked loop and a feedback clock signal output by the phase-locked loop; the charging control module is configured to charge the loop filter under the action of the reference clock signal and the feedback clock signal when the feedback clock signal meets a preset charging condition; and the locking time of the phase-locked loop is related to the time when the charging control module charges the loop filter. The charging control module can charge the loop filter, accelerate the locking of the phase-locked loop, and has no influence on the loop characteristics after the fast start process is completed, and the circuit structure is simple and easy to implement, and the circuit area overhead is small.

[0025] Next, the phase-locked loop provided in the present application is exemplarily described.

[0026] As shown in Figure 1 , the phase-locked loop provided in the present application includes a phase-frequency detector PFD, a charge pump CP, a loop filter LPF, a voltage-controlled oscillator VCO, and a frequency divider DIV, and a charging control module is arranged between the input end of the phase-frequency detector PFD (the input end of the phase-locked loop) and the loop filter. Figure 1 The charging control module receives a reference clock signal (CLKref in Figure 1 ) at the input end of the phase-locked loop and a feedback clock signal (CLKfb output by the frequency divider DIV in Figure 1 ) output by the phase-locked loop.

[0027] The charging control module is configured to charge the loop filter under the action of the reference clock signal and the feedback clock signal when the feedback clock signal meets a preset charging condition; and the locking time of the phase-locked loop is related to the time when the charging control module charges the loop filter.

[0028] It should be noted that the preset charging condition is that the frequency of the feedback clock signal is less than a preset multiple of the frequency of the reference clock signal, the preset multiple can be any number between 0 and 1, which is preset according to needs and application scenarios, and can be an optimal value after testing, or can be obtained according to the frequency division ratio of the reference clock signal and the feedback clock signal, the value of the preset multiple is set to be less than or equal to 1, so that the frequency of the feedback clock signal is equal to the reference clock signal when the phase-locked loop is locked, and no new disturbance is introduced, if the preset multiple is greater than 1, when the frequency of the feedback clock signal is equal to the frequency of the reference clock signal, the phase-locked loop is still in the locking process, and the level switching of the output signal of the frequency comparison module will increase additional disturbance.

[0029] When the frequencies of the reference clock signal and the feedback clock signal are not equal, the frequency discriminator compares the frequency difference and the phase difference between the reference clock signal and the feedback clock signal, and outputs a control voltage according to the frequency difference and the phase difference to drive the charge pump, the charge pump charges the loop filter to increase the voltage of the output signal of the loop filter, and the voltage-controlled oscillator generates a clock signal according to the output voltage of the loop filter, the frequency divider divides the clock signal output by the voltage-controlled oscillator by a specified frequency division multiple and outputs the feedback clock signal, and the feedback clock signal output at this time is fed back to the frequency discriminator to be compared with the reference clock signal, until the frequencies of the reference clock signal and the feedback clock signal are equal and the phase difference is a constant, and the phase-locked loop reaches a locked state.

[0030] In the prior art, the loop filter is generally charged by a charge pump to increase the output voltage to the voltage-controlled oscillator, but the charging speed of the charge pump is slow and is easily affected by the original phase error of the phase-locked loop, in the case of a large phase error, the charge pump needs a longer time to provide sufficient current to charge the loop filter, in some embodiments of the present application, a charging control module is arranged between the input end of the phase-locked loop and the loop filter to provide additional charging to the loop filter in addition to the charge pump, and the loop filter can be directly charged by bypassing the charge pump, the charging rate of the loop filter is improved, the amplitude of the output voltage of the loop filter can rise at a faster speed, the charging time of the loop filter is reduced, and the locking time of the phase-locked loop is further reduced.

[0031] The charging control module of the present application will be described below in conjunction with a specific example.

[0032] The charging control module described above includes a frequency comparison unit and a charging unit.

[0033] The first input end of the frequency comparison unit is connected with the input end of the phase-locked loop for receiving the reference clock signal, and the second input end of the frequency comparison unit is connected with the feedback output end of the phase-locked loop for receiving the feedback clock signal.

[0034] The first control end of the charging unit is connected with the first output end of the frequency comparison unit, the second control end of the charging unit is connected with the second output end of the frequency comparison unit, the first output end of the charging unit is connected with the first end of the loop filter, and the second output end of the charging unit is connected with the second end of the loop filter.

[0035] The frequency comparison unit is configured to generate a control signal according to the reference clock signal and the feedback clock signal, so as to control the charging and discharging state of the charging unit.

[0036] The charging unit is configured to charge the loop filter under the action of the control signal, so as to increase the output voltage (Vc) of the loop filter. Figure 1 The amplitude variation rate of the output voltage is proportional to the charging rate of the loop filter, the control signal output by the frequency comparison unit controls the charging state of the charging unit, and the charging control of the loop filter is realized.

[0037] For example, the charging unit for charging the loop filter can be a circuit composed of a power supply device (such as a power supply, a capacitor, etc.), a switch and the like.

[0038] The frequency comparison unit (the frequency comparison module in the above formula) comprises a frequency comparator. Figure 1

[0039] The first input end of the frequency comparator is connected with the input end of the phase-locked loop, the second input end of the frequency comparator is connected with the feedback output end of the phase-locked loop, the first output end of the frequency comparator is connected with the first control end of the charging unit, and the second output end of the frequency comparator is connected with the second control end of the charging unit.

[0040] The frequency comparator is configured to generate a first control signal and a second control signal according to the reference clock signal and the feedback clock signal, so as to control the charging and discharging state of the charging unit.

[0041] Specifically, the first control signal and the second control signal are used for on-off control of the switch in the charging unit, so as to control the charging and discharging state of the charging unit.

[0042] When the feedback clock signal satisfies a preset charging condition, the frequency comparator switches the control state of the first control signal and the second control signal according to the reference clock signal and the feedback clock signal. The control state of the first control signal is the level state (high level or low level) of the first control signal, and the control state of the second control signal is the level state of the second control signal.

[0043] ​It should be noted that when the feedback clock signal does not satisfy the preset charging condition, the level states of the first control signal and the second control signal remain constant, the first control signal is at a low level, the second control signal is at a high level, and the level states of the first control signal and the second control signal are not switched. The switching frequency of the level states of the first control signal and the second control signal is related to the reference clock signal and the feedback clock signal. Specifically, when the level of the reference clock signal is switched, whether the level states of the first control signal and the second control signal need to be switched is determined according to the phases of the reference clock signal and the feedback clock signal. The closer the frequencies of the reference clock signal and the feedback clock signal, the smaller the probability that the level of the first control signal is switched from a low level to a high level. The feedback clock signal and the reference clock signal are detected and compared, and when the frequency of the feedback clock signal is less than the frequency of the reference clock signal, the level state of the first control signal is determined according to the phases and frequencies of the reference clock signal and the feedback clock signal, that is, whether the first control signal should be switched to a high level or a low level. For example, the reference clock signal and the feedback clock signal can be frequency-divided to obtain frequency-divided reference clock signals and feedback clock signals, and the level state of the first control signal is determined according to the frequency-divided reference clock signals and the feedback clock signals. After detecting the frequency-divided reference clock signal, if the rising edge of the frequency-divided reference clock signal is detected first at the next detection, it indicates that the charging unit needs to be charged at this time, the first control signal is switched to a high level, and if the rising edge of the frequency-divided feedback clock signal is detected first at the next detection, the first control signal is at a low level. Therefore, the actual frequencies of the first control signal and the second control signal are related to the reference clock signal and the feedback clock signal. When the level of the reference clock signal is switched, the level state of the first control signal is determined according to the phases and frequencies of the feedback clock signal and the reference clock signal at this time, that is, the first control signal and the second control signal remain at the original level state or are flipped.

[0044] The charging unit includes a first charging unit and a second charging unit.

[0045] The control end of the first charging unit is connected with the first output end of the frequency comparator, and the output end of the first charging unit is connected with the first end of the second charging unit.

[0046] The control end of the second charging unit is connected with the second output end of the frequency comparator, the second end of the second charging unit is connected with the first end of the loop filter, and the third end of the second charging unit is connected with the second end of the loop filter.

[0047] The first charging unit is configured to charge the second charging unit according to the first control signal.

[0048] The second charging unit is used to charge the loop filter under the action of the second control signal and the first charging unit; wherein the first control signal is out of phase with the second control signal.

[0049] When the first control signal is high, the second control signal is low, and the first charging unit charges the second charging unit. When the first control signal is low, the second control signal is high, the first charging unit does not charge the second charging unit, and the second charging unit charges the loop filter. In other words, the charging states of the first and second charging units are controlled and switched through the first and second control signals, allowing for gradual and rapid charging of the loop filter.

[0050] The first charging unit includes a first power source ( Figure 1 VDD in the middle) and the first switch ( Figure 1 S in (the part).

[0051] The control terminal of the first switch is connected to the first output terminal of the frequency comparator, the first terminal of the first switch is connected to the first terminal of the second charging unit, and the second terminal of the first switch is connected to the first power supply. The first control signal is used to control the on / off state of the first switch.

[0052] When the first switch is turned on, the first power source charges the second charging unit.

[0053] For example, the first charging unit can be a combination circuit of power supply devices (such as current sources, capacitors, etc.) and control circuit devices that switch on and off (such as switches, MOSFETs, etc.), as long as it can charge itself and charge the second charging unit. The specific implementation method is not limited in this embodiment.

[0054] The second charging unit includes a second switch ( Figure 1 Sb in the first capacitor and the first capacitor ( Figure 1 (C1 in the middle).

[0055] The control terminal of the second switch is connected to the second output terminal of the frequency comparator. The first terminal of the second switch is connected to the output terminal of the first charging unit and the first terminal of the first capacitor. The second terminal of the second switch is connected to the first terminal of the loop filter. The second terminal of the first capacitor is connected to the second terminal of the loop filter. The second terminal of the first switch is connected to the first terminal of the second switch. The second control signal is used to control the on / off state of the second switch.

[0056] When the second switch is turned on, the first capacitor charges the loop filter at a preset rate; wherein, the closed state of the second switch is opposite to the closed state of the first switch, and the preset rate and the locking time of the phase-locked loop are related to the capacitance value of the first capacitor.

[0057] For example, the second charging unit can be a combination of a device that stores electric charge (such as a capacitor, an inductor, a battery that can be charged) and a device that controls the on-off switching (such as a switch, a MOS tube, etc.).

[0058] It should be noted that when the first control signal is high, the first switch is turned on, and when the first control signal is low, the first switch is turned off. When the second control signal is high, the second switch is turned on, and when the second control signal is low, the second switch is turned off. When the first switch is turned on and the second switch is turned off, the first capacitor is charged by the first power supply. When the first switch is turned off and the second switch is turned on, the loop filter is charged by the first capacitor after charging, thereby increasing the amplitude of the output voltage of the loop filter.

[0059] When the first control signal output by the frequency comparison module according to the reference clock signal and the feedback clock signal is high, the second control signal is opposite to the first control signal and is low. The first control signal controls the first switch to be turned on, and the second control signal controls the second switch to be turned off. The first power supply VDD charges the first capacitor C1. When the first control signal output by the frequency comparison module according to the reference clock signal and the feedback clock signal is low, the second control signal is opposite to the first control signal and is high. The first control signal controls the first switch to be turned off, and the second control signal controls the second switch to be turned on. The voltage across the first capacitor C1 is higher than the voltage between the first end and the second end of the loop filter. The charge on the first capacitor C1 moves to the loop filter, thereby charging the loop filter LPF.

[0060] The loop filter includes a second capacitor (C2) in the formula, Figure 1 a third capacitor (C3) in the formula, Figure 1 a load (R2) in the formula, Figure 1 and a second power supply (such as a ground terminal).

[0061] The first end of the second capacitor, the second end of the second switch, and the second end of the load are commonly connected. The second end of the second capacitor, the second end of the first capacitor, the second power supply, and the second end of the third capacitor are commonly connected. The first end of the load and the first end of the third capacitor are connected, and the common connection is commonly connected with the output end of the charge pump of the phase-locked loop and the input end of the voltage-controlled oscillator.

[0062] The total value of the capacitances of the first capacitor and the second capacitor after being added is a first preset value. The ratio of the capacitance value of the first capacitor to the total value of the capacitances is a second preset value. The preset rate and the locking time of the phase-locked loop are related to the second preset value. The voltage of the first power supply is higher than the voltage of the second power supply. The first preset value and the second preset value are optimal preset values obtained by testing in advance.

[0063] The greater the proportion of the capacitance value of the first capacitor compared to the second capacitor in the total capacitance value, the more charge the first capacitor can store (at the same time, in order to ensure the amount of charge of the second capacitor, the second preset value cannot exceed the maximum value obtained by pre-test), that is, the greater the proportion of the first capacitor in the total capacitance value, the faster the preset rate of charging the loop filter, the greater the amount of charge to the loop filter each time, the greater the amplitude change of the output voltage of the loop filter, and the shorter the locking time of the phase-locked loop. However, too high a proportion of the capacitance value of the first capacitor will cause an overshoot, causing the output Vc of the loop filter to be charged higher than the voltage equilibrium point. The smaller the proportion of the capacitance value of the first capacitor compared to the second capacitor, the less charge the first capacitor can store, the smaller the preset rate of charging the loop filter, the smaller the amount of charge to the loop filter each time, the smaller the amplitude change of the output voltage of the loop filter, and the longer the locking time of the phase-locked loop.

[0064] In the embodiment, when the first control signal is high and the second control signal is low, the first control signal controls the first switch to be turned on, and the second control signal controls the second switch to be turned off, so that the first capacitor C1 is charged by the first power supply. Since the upper plates of the second capacitor and the third capacitor are disconnected from the first power supply, the second capacitor and the third capacitor remain unchanged. When the first control signal is low and the second control signal is opposite to the first control signal, the second control signal is high. At this time, the first control signal controls the first switch to be turned off, and the second control signal controls the second switch to be turned on. At this time, the first capacitor and the second capacitor are connected in parallel and connected in series with the load, and the third capacitor is connected in parallel with the first capacitor and the second capacitor connected in parallel. At this time, the voltage across the first capacitor C1 is higher than the voltage between the first end and the second end of the loop filter. In order to equalize the voltages across the three capacitors, the charge on the first capacitor C1 moves to the capacitors in the loop filter, and the charge is redistributed to charge the loop filter LPF.

[0065] As shown in Figure 1 The phase-locked loop further includes a charge pump CP and a voltage-controlled oscillator VCO, Figure 2 UP indicates that the phase of the feedback clock signal lags behind the reference clock signal, DN indicates that the phase of the feedback clock signal leads the reference clock signal, Icp indicates the output current of the charge pump, and CLKout indicates the output clock signal of the phase-locked loop.

[0066] It should be noted that at the beginning of the locking process, the frequency of the reference clock signal is greater than the frequency of the feedback clock signal, the preset charging condition is met, and the levels of the first control signal and the second control signal are switched multiple times. When the first control signal is high, the first switch is connected, and at this time the second control signal is low, the second switch is disconnected, and the first power supply charges the first capacitor. At this time, since the second switch is disconnected, the second capacitor and the third capacitor are not charged; when the first control signal is low, the first switch is disconnected, and at this time the second control signal is high, the second switch is connected, C1 and C2, C3 perform charge redistribution, and C2 and C3 are charged through C1, so that the voltages across the three capacitors are eventually equal. After the first switching process, the change amount of Vc can be expressed as: ; Wherein is the voltage of the first power supply, Vc represents the voltage of Vc after the first charging, Vc represents the voltage of Vc after the first charging. Solving the above formula, we get After conversion, the expression of Vc is: ; The voltage-controlled oscillator outputs a clock signal according to Vc, and the clock signal is processed by the frequency divider and input into the frequency discriminator and the frequency comparator as the feedback clock signal.

[0067] When the feedback clock signal does not meet the preset charging condition (i.e. the frequency of the feedback clock signal is greater than or equal to the frequency of the reference clock signal), the first control signal is low, the second control signal is high, and the level state is not switched. At this time, the circuit is equivalent to, the load R2 and the capacitor composed of C1 and C2 (the capacitance is C1+C2) in parallel are connected in series, and C3 is connected in parallel, and they are connected together between the phase-locked loop loop and the ground. At the same time, the locking of the phase-locked loop is realized by the charge and discharge of the charge pump in the phase-locked loop loop, which is the same as the traditional structure.

[0068] It should be noted that the first capacitor C1 charges the loop filter when the level of the first control signal switches, that is, when the level of the first control signal switches from high to low, the level of the second control signal switches from low to high, the first switch switches from on to off, and the second switch switches from off to on, at this time the first capacitor is connected in parallel with the second capacitor and the third capacitor, and the charge of the first capacitor is transferred to the second capacitor and the third capacitor, that is, if the level state of the first control signal output by the frequency comparator no longer switches, that is, the first control signal is always high, and the second control signal is always low, the fast start process ends, and locking is completed, at this time the charging of the first capacitor C1 or the charging of the loop filter cannot be triggered.

[0069] The phase-locked loop of the present application will be exemplarily described below in combination with a specific example.

[0070] The level change diagrams of the first control signal and the second control signal are as shown in Figure 2 Figure 3 wherein S represents the level change diagram of the first control signal, Sb represents the level change diagram of the second control signal, and Vc represents the amplitude change diagram of the output voltage of the loop filter.

[0071] The charging process is as shown in Figure 3 Figure 3 a is a schematic diagram of charging the first capacitor when the first control signal S is high, the first switch S is connected, the second switch Sb is disconnected, VDD outputs a current I, and the first capacitor C1 is charged, since Sb is disconnected, the second capacitor C2 and the third capacitor C3 are not charged at this time, Figure 3 wherein R2 represents a load, Vc is the output voltage of the loop filter, and the arrow represents the charge transfer direction; ​ b is a schematic diagram of charging C2 and C3 when the first control signal is low, at this time the first switch is disconnected, the second switch is connected, the charge on C1 is transferred to C2 and C3, and charging of C2 and C3 is realized.

[0072] It is worth mentioning that the charging control module is arranged, which can realize charging of the loop filter, speed up locking of the phase-locked loop, has no influence on the loop characteristic after the fast start process ends, and has a simple circuit structure, is easy to realize, and has small circuit area overhead.

[0073] The embodiment of the present application provides a chip comprising the phase-locked loop.

[0074] The above is the preferred embodiment of the present application, and it should be pointed out that, for ordinary skilled persons in the technical field, a number of improvements and refinements can be made without departing from the principles of the present application, and these improvements and refinements should also be regarded as the protection scope of the present application.​​

Claims

1. A phase-locked loop, characterized in that, A charging control module is provided between the input terminal of the phase-locked loop and the loop filter. The charging control module receives the reference clock signal from the input terminal of the phase-locked loop and the feedback clock signal from the output terminal of the phase-locked loop. The charging control module is used to charge the loop filter under the action of the reference clock signal and the feedback clock signal when the feedback clock signal meets the preset charging conditions; wherein, the locking time of the phase-locked loop is related to the charging time of the loop filter by the charging control module.

2. The phase-locked loop according to claim 1, characterized in that, The charging control module includes a frequency comparison unit and a charging unit; The first input terminal of the frequency comparison unit is connected to the input terminal of the phase-locked loop (PLL) for receiving the reference clock signal, and the second input terminal of the frequency comparison unit is connected to the feedback output terminal of the PLL for receiving the feedback clock signal. The first control terminal of the charging unit is connected to the first output terminal of the frequency comparison unit, the second control terminal of the charging unit is connected to the second output terminal of the frequency comparison unit, the first output terminal of the charging unit is connected to the first terminal of the loop filter, and the second output terminal of the charging unit is connected to the second terminal of the loop filter. The frequency comparison unit is used to generate a control signal based on the reference clock signal and the feedback clock signal to control the charging and discharging state of the charging unit. The charging unit is used to charge the loop filter under the action of the control signal to increase the output voltage of the loop filter; wherein the rate of change of the amplitude of the output voltage is proportional to the charging rate of the loop filter.

3. The phase-locked loop according to claim 2, characterized in that, The frequency comparison unit includes a frequency comparator; The first input terminal of the frequency comparator is connected to the input terminal of the phase-locked loop, the second input terminal of the frequency comparator is connected to the feedback output terminal of the phase-locked loop, the first output terminal of the frequency comparator is connected to the first control terminal of the charging unit, and the second output terminal of the frequency comparator is connected to the second control terminal of the charging unit. The frequency comparator is used to generate a first control signal and a second control signal based on the reference clock signal and the feedback clock signal, so as to control the charging and discharging state of the charging unit. When the feedback clock signal meets the preset charging conditions, the frequency comparator switches the control states of the first control signal and the second control signal according to the reference clock signal and the feedback clock signal.

4. The phase-locked loop according to claim 3, characterized in that, The charging unit includes a first charging unit and a second charging unit; The control terminal of the first charging unit is connected to the first output terminal of the frequency comparator, and the output terminal of the first charging unit is connected to the first terminal of the second charging unit. The control terminal of the second charging unit is connected to the second output terminal of the frequency comparator, the second terminal of the second charging unit is connected to the first terminal of the loop filter, and the third terminal of the second charging unit is connected to the second terminal of the loop filter. The first charging unit is used to charge the second charging unit according to the first control signal; The second charging unit is used to charge the loop filter under the action of the second control signal and the first charging unit; wherein the first control signal is out of phase with the second control signal.

5. The phase-locked loop according to claim 4, characterized in that, The first charging unit includes a first power supply and a first switch; The control terminal of the first switch is connected to the first output terminal of the frequency comparator, the first terminal of the first switch is connected to the first terminal of the second charging unit, and the second terminal of the first switch is connected to the first power supply. When the first switch is turned on, the first power source charges the second charging unit.

6. The phase-locked loop according to claim 4, characterized in that, The second charging unit includes a second switch and a first capacitor; The control terminal of the second switch is connected to the second output terminal of the frequency comparator, the first terminal of the second switch is connected to the output terminal of the first charging unit and the first terminal of the first capacitor, the second terminal of the second switch is connected to the first terminal of the loop filter, and the second terminal of the first capacitor is connected to the second terminal of the loop filter. When the second switch is turned on, the first capacitor charges the loop filter at a preset rate; wherein the closed state of the second switch is opposite to the closed state of the first switch, and the preset rate and the locking time of the phase-locked loop are related to the capacitance value of the first capacitor.

7. The phase-locked loop according to claim 6, characterized in that, The loop filter includes a second capacitor, a third capacitor, a load, and a second power supply; The first terminal of the second capacitor, the second terminal of the second switch, and the second terminal of the load are connected together. The second terminal of the second capacitor, the second terminal of the first capacitor, the second power supply, and the second terminal of the third capacitor are connected together. The first terminal of the load and the first terminal of the third capacitor are connected together, and the common terminal of the connection is connected to the output terminal of the charge pump of the phase-locked loop and the input terminal of the voltage-controlled oscillator. Wherein, the total capacitance value after adding the capacitance values ​​of the first capacitor and the second capacitor is a first preset value, the ratio of the capacitance value of the first capacitor to the total capacitance value is a second preset value, the preset rate and the locking time of the phase-locked loop are related to the second preset value, and the voltage of the first power supply is higher than the voltage of the second power supply.

8. The phase-locked loop according to claim 3, characterized in that, When the feedback clock signal does not meet the preset charging condition, the first control signal is at a low level, and the level states of both the first control signal and the second control signal no longer switch.

9. The phase-locked loop according to claim 1, characterized in that, The preset charging condition is that the frequency of the feedback clock signal is less than a preset multiple of the frequency of the reference clock signal.

10. A chip, characterized in that, Includes the phase-locked loop as described in any one of claims 1-9.

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