Clock generation circuit for time-interleaved ADC

Abstract

The invention discloses a clock generation circuit for a time-interleaved ADC, and belongs to the technical field of integrated circuits. Comprising a delay circuit Delay, a frequency division module and a pulse width adjusting circuit CLKsample, the pulse width adjusting circuit CLKsample is used for generating a sampling clock signal CLKS with adjustable pulse width and inputting the sampling clock signal CLKS into the second AND gate group; the frequency division module performs frequency division on an external clock signal CLK into multiple paths, inputs the multiple paths of signals into the first AND gate group to obtain multiple intermediate clock signals, and inputs the multiple intermediate clock signals into the second AND gate group; the second AND gate group performs AND operation on the sampling clock signal CLKS and each intermediate clock signal to obtain a plurality of multi-phase clock sampling signals, and inputs the multi-phase clock sampling signals into each sub-ADC module for time-interleaved sampling and analog-to-digital conversion; and combining and synchronizing to obtain a final signal. The circuit is simple in structure, smaller in area and lower in power consumption, extremely small phase deviation exists between interleaved sampling clock signals, and meanwhile the pulse width of the sampling clock signals can be freely adjusted.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, and in particular to a clock generation circuit for time-interleaved ADC. BACKGROUND

[0002] In order to meet the requirements of the communication industry to deliver higher rate and higher quality information, the bandwidth of wired and wireless transmission systems is growing, which greatly stimulates the demand for high-speed ADCs with ultra-high bandwidth, medium resolution and low power consumption, and GHz sampling rate. The existing architecture of ADC has the advantages of high precision, low power consumption and small area, but the conversion speed of a single ADC is difficult to further improve. Higher sampling rate ADCs need to be implemented through time interleaving, and when the speed of a single channel ADC approaches the design bottleneck, it is particularly important to use time interleaving to achieve ultra-high sampling rate. The time interleaving circuit is located at the front end of the ADC and is a key component that determines the input bandwidth and sampling rate of the ADC, which is of great significance to the implementation of high-speed ADCs.

[0003] In the prior art, the pulse width of the interleaved sampling clock signal is not adjusted, and the sampling pulse width is fixed at 50% duty cycle. In high-speed ADC applications, due to the very high speed of the sampling clock, the 50% pulse width sampling time will cause the highest sampling rate of the ADC to decrease. In order to further improve the sampling rate of the ADC, a clock signal with a duty cycle of 20% or even 10% is usually required. SUMMARY

[0004] The purpose of the present application is to overcome the shortcomings of the prior art and provide a clock generation circuit for time-interleaved ADC.

[0005] The purpose of the present application is achieved by the following technical solution: a clock generation circuit for time-interleaved ADC, comprising a delay circuit Delay, a frequency division module and a first D flip-flop, the input end of the delay circuit Delay, the frequency division module and the first D flip-flop receiving an external clock signal CLK; The delay circuit Delay is used to generate an adjusted timing external clock signal CLK and input to a pulse width adjustment circuit CLK_sample; the pulse width adjustment circuit CLK_sample is used to generate a sampling clock signal CLKS with adjustable pulse width and input to a second AND gate group; The frequency division module divides the external clock signal CLK into multiple input signals to the first AND gate group to obtain multiple intermediate clock signals, and inputs the multiple intermediate clock signals to the second AND gate group; the second AND gate group obtains multiple multi-phase clock sampling signals by performing AND operation on the sampling clock signal CLKS and each intermediate clock signal, and inputs the multiple multi-phase clock sampling signals to each sub-ADC module of the time-interleaved ADC to perform time-interleaved sampling and analog-to-digital conversion; Each sub-ADC module outputs a digital signal to the multiplexer MUX circuit to combine the digital signals into one data output signal, and inputs the data output signal to the first D flip-flop driven by the external clock signal CLK to output a final signal after synchronization.

[0006] Preferably, the frequency division module comprises at least one frequency divider; the first AND gate group comprises multiple AND gates, and the second AND gate group also comprises multiple AND gates.

[0007] Preferably, the duty cycle of the intermediate clock signal is 25%, and the duty cycle of the multiple frequency division signals output by the frequency division module is 50%.

[0008] Preferably, the multiplexer MUX circuit is driven by the intermediate clock signal.

[0009] Preferably, the frequency divider is a D flip-flop with the output end connected to the input end in an inverting manner.

[0010] Preferably, the pulse width adjustment circuit CLK_sample comprises a second D flip-flop with a reset function, the input end of the second D flip-flop is connected to a high potential VDD, the clock port of the second D flip-flop receives the external clock signal CLK after passing through the delay circuit Delay, the output end of the second D flip-flop is connected to the input end of each AND gate in the second AND gate group and the inverter, the output end of the inverter is connected to multiple series-connected delay units DELAY cell, the output signal of each delay unit DELAY cell is output to the input end of the multiplexer MUX, and the multiplexer MUX outputs the output signal of the delay unit DELAY cell according to the multi-bit control signal PULSE <n:0>A delay signal is selected to output to a first input end of a first AND gate, so as to adjust the pulse width of the sampling clock signal CLKS; a second input end of the first AND gate receives an external reset control signal RST, and an output end of the first AND gate is connected to a reset control port of a second D flip-flop.

[0011] The present application has the following advantages: The circuit of the present application has simple structure, smaller area, lower power consumption, small phase deviation between the interleaved sampling clock signals, and adjustable pulse width of the sampling clock signal. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 The clock generation circuit is taken as an example of a four-sampling time interleaved ADC; Figure 2 The circuit principle diagram of the pulse width adjustment circuit CLK_sample; Figure 3 The circuit principle diagram of the frequency divider; Figure 4 The timing waveform diagram of the clock generation circuit taken as an example of a four-sampling time interleaved ADC; Figure 5 The two-channel time interleaved clock generation circuit principle diagram based on the extension of the present application. DETAILED DESCRIPTION

[0013] The technical solutions of the present application will be described clearly and completely in combination with the embodiments. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0014] Referring to Figures 1-5 The present application provides a technical solution: a clock generation circuit for a time interleaved ADC, comprising a delay circuit Delay, a frequency divider module and a first D flip-flop, the input ends of the delay circuit Delay, the frequency divider module and the first D flip-flop receiving an external clock signal CLK; The delay circuit Delay is used to generate an adjusted timing external clock signal CLK and input to a pulse width adjustment circuit CLK_sample; the pulse width adjustment circuit CLK_sample is used to generate a sampling clock signal CLKS with adjustable pulse width and input to a second AND gate group; The frequency division module divides the external clock signal CLK into multiple input paths to a first AND gate group for two-by-two combination to obtain multiple intermediate clock signals, and inputs the multiple intermediate clock signals to a second AND gate group; the second AND gate group performs AND operation on the sampling clock signal CLKS and each intermediate clock signal to obtain multiple multi-phase clock sampling signals, and inputs the multiple multi-phase clock sampling signals to each sub-ADC module of the time-interleaved ADC for time-interleaved sampling and analog-to-digital conversion; Each sub-ADC module outputs a digital signal to a multiplexer MUX circuit to combine into one data output signal, and inputs the data output signal to a first D flip-flop driven by the external clock signal CLK for synchronization and then outputs a final signal.

[0015] In this embodiment, as shown in Figure 1 Fig. 4, a four-sampling time-interleaved ADC is taken as an example, and includes delay circuit (Delay), pulse width adjustment circuit (CLK_sample), frequency divider (Divider) and logic AND gate (AND) and other components, to generate the multi-phase sampling clock signals CLKS_1, CLKS_2, CLKS_3 and CLKS_4 required by the four-sampling time-interleaved ADC.

[0016] The input clock signal CLK is simultaneously input to the delay circuit (Delay), the frequency division module and the first D flip-flop; the delay circuit (Delay) is a clock delay generating driving buffer, used for adjusting the signal timing to ensure that the rising edge time of the CLKS signal is later than the rising edge time of the signals CK_1, CK_2, CK_3 and CK_4, so as to ensure sufficient setup time when the two signals are operated by the AND gate (AND), and to make the rising edge time of the output clock signals CLKS_1, CLKS_2, CLKS_3 and CLKS_4 completely consistent with the rising edge time of the CLKS signal, so as to reduce the phase deviation between the sampling clock signals.

[0017] The output of the delay circuit is connected to the pulse width adjustment circuit (CLK_sample), and the pulse width adjustment circuit outputs the sampling clock signal CLKS, which is input to the frequency division module through the input control signal PULSE <n:0>The pulse width w1 of the CLKS signal can be freely adjusted, and in high-speed time-interleaved ADC applications, the time length of w1 can be appropriately shortened to meet the requirements of high-speed sampling and analog-digital conversion.

[0018] The CLK signal is input to a divider of a frequency division module, which outputs two clock signals with opposite phases and a 50% duty cycle. The two clock signals are connected to two identical dividers, respectively, and each divider outputs two clock signals with opposite phases and a 50% duty cycle, i.e., CLK_1 and CLK_3 signals and CLK_2 and CLK_4 signals. The CLK_1, CLK_2, CLK_3, and CLK_4 signals (frequency division signals) are combined by each AND gate in the first AND gate group to output intermediate clock signals CK_1, CK_2, CK_3, and CK_4 with a 25% duty cycle. Specifically, CK_1 is generated by the AND gate of CLK_1 and CLK_4, CK_2 is generated by the AND gate of CLK_1 and CLK_2, CK_3 is generated by the AND gate of CLK_2 and CLK_3, and CK_4 is generated by the AND gate of CLK_3 and CLK_4.

[0019] The CK_1, CK_2, CK_3, and CK_4 signals are ANDed with the CLKS signal output by the pulse width adjustment circuit in each AND gate in the second AND gate group to output final multi-phase clock sampling signals CLKS_1, CLKS_2, CLKS_3, and CLKS_4. Therefore, the final multi-phase clock sampling signals have the same pulse width w1 as the CLKS signal, and the rising edges of all multi-phase clock sampling signals are completely consistent with the CLKS signal, which ensures that the phase deviation between the sampling clock signals is extremely small, thereby reducing the harmonic distortion of the time-interleaved ADC. Finally, all multi-phase clock sampling signals are connected to each sub-ADC module (ADC1, ADC2, ADC3, ADC4) of the time-interleaved ADC for time-interleaved sampling and analog-digital conversion.

[0020] The digital signals Data_1 <n:0>Data_2 <n:0>Data_3 <n:0>Data_4 <n:0>The data output signal is combined into one data output signal after multiplexing by a MUX circuit, and then outputted by a D flip-flop driven by a CLK clock <n:0>The multiplexer (MUX) circuit is driven by clock signals CK_1, CK_2, CK_3 and CK_4 with a 25% duty cycle, and sequentially selects one of the input signals to output.

[0021] The CLKs_1, CLKs_2, CLKs_3 and CLKs_4 have a very small phase deviation, because all the multi-phase clock sampling signals are generated by the same CLKs signal, and the clock edges are completely consistent with the CLKs signal, and the only possible phase deviation is caused by the delay difference between the multiple AND gates for generating the multi-phase clock sampling signals, and the delay deviation between multiple AND gates that are adjacent on the layout of the same chip is very small. In the application of time-interleaved ADC, the phase deviation between the multi-phase sampling clock signals will seriously affect the harmonic distortion index of the overall ADC. Meanwhile, due to the pulse width adjustment circuit (CLK_sample), the pulse width of the multi-phase clock sampling signal can be freely adjusted, so that the demand of the high-speed time-interleaved ADC for narrow pulse width of the clock sampling signal can be better met.

[0022] The timing waveform of the clock generation circuit taking a four-sampling time-interleaved ADC as an example is shown in Figure 4 The delay time d1 of the CLKs signal relative to the input CLK signal includes the delay of the Delay unit and the total delay of the pulse width adjustment circuit (CLK_sample). The purpose of adding the delay time d1 to the CLKs signal is to ensure that the rising edge time of the CLKs signal is later than that of the signals CK_1, CK_2, CK_3 and CK_4, so as to ensure that there is enough setup time when the two are operated with AND, and to make the rising edge time of the output clock signals CLKs_1, CLKs_2, CLKs_3 and CLKs_4 completely consistent with that of the CLKs signal, so as to reduce the phase deviation between the multi-phase clock sampling signals. Figure 4 The high-level pulse width w1 of the CLKs signal is controlled and adjusted by the pulse width adjustment circuit (CLK_sample), and in the application of high-speed time-interleaved ADC, the time length of w1 can be appropriately shortened to meet the requirements of high-speed sampling and analog-digital conversion.

[0023] According to the technical scheme provided by the present application, the number of sampling clock can be easily expanded to 2 (two-channel time-interleaved clock generation circuit as shown in Figure 5 ), 8, 16, etc.

[0024] In some embodiments, the frequency division module includes at least one frequency divider; the first AND gate group includes multiple AND gates, and the second AND gate group also includes multiple AND gates.

[0025] In some embodiments, the intermediate clock signal has a duty cycle of 25%; the multiple frequency division signals outputted by the frequency division module have a duty cycle of 50%.

[0026] In some embodiments, the multiple selection MUX circuit is driven by the intermediate clock signal.

[0027] In some embodiments, the frequency divider is a D flip-flop with the inverting output connected to the D input.

[0028] In the present embodiment, the circuit structure of the frequency divider can adopt various designs. One simple frequency divider circuit structure is shown in FIG. 2, in which the inverting output of the D flip-flop is connected to the D input, and the frequency division function is realized under the drive of the clock CLK. The frequency divider needs to output both the in-phase frequency division signal DIV CLKp and the inverting frequency division signal DIV CLKn. Figure 3

[0029] In some embodiments, the pulse width adjustment circuit CLK_sample includes a second D flip-flop with a reset function, the input of the second D flip-flop is connected to the high potential VDD, the clock port of the second D flip-flop receives the external clock signal CLK through the delay circuit Delay, the output of the second D flip-flop is connected to the input of each AND gate in the second inverter and second AND gate group; the output of the inverter is connected to a plurality of series-connected delay units DELAY cell; the output signal of each delay unit DELAY cell is outputted to the input of the multiplexer MUX; the multiplexer MUX outputs the signal according to the multiple bit control signal PULSE <n:0>The first input end of the first AND gate is connected with a delay signal output, so as to adjust the pulse width of the sampling clock signal CLKS; the second input end of the first AND gate is connected with an external reset control signal RST, and the output end of the first AND gate is connected with the reset control port of the second D flip-flop.

[0030] In the embodiment, as shown in Figure 2 The function is to convert the input clock signal (CLK) with 50% duty cycle into the sampling signal (CLKS) with adjustable pulse width. The pulse width adjusting circuit (CLK_sample) comprises a second D flip-flop (DFF) with reset function, an inverter (INV), delay units (DELAY cell) connected in sequence, a multiplexer (MUX) and a first AND gate (AND); the input end of the second D flip-flop is connected with a high potential VDD, the clock port is connected with the input clock signal CLK, the output port of the second D flip-flop generates the output signal CLKS with adjusted pulse width, and simultaneously connects the input end of the inverter (INV); the output end of the inverter (INV) is connected with the delay units (DELAY cell) in sequence, the output signal of each delay unit is connected with the input end of the multiplexer (MUX), the multiplexer (MUX) is connected with a plurality of bit control signals PULSE <n:0>The output of the multiplexer (MUX) is connected to one input of a first AND gate, and the other input of the first AND gate is connected to an external reset control signal RST. The output of the first AND gate is connected to a reset control port of a second D flip-flop.

[0031] When the reset control signal RST is a 0 signal, the second D flip-flop is in a reset state, and the output CLKS is at a 0 level. When the RST signal is a high level 1, the pulse width adjustment circuit enters a normal working mode. At each rising edge of the input clock signal CLK, a high level 1 is output to the CLKS port, and a 0 level signal is obtained after the CLK signal passes through an inverter. After the 0 level signal passes through a plurality of delay units, one of the delay signals is selected by a multiplexer as an output. The output signal of the multiplexer and the RST signal pass through the first AND gate and are connected to the reset port of the second D flip-flop, so as to reset the output of the second D flip-flop. After the reset, the output of the second D flip-flop is at a 0 level, that is, the CLKS signal is at a 0 level. Thus, a narrow pulse signal of the CLKS sampling signal is obtained, and the width of the high level pulse is controlled by the total delay time of the delay units. By selecting different output signals of the delay units through the multiplexer, the pulse width of the CLKS pulse signal can be freely adjusted.

[0032] The above description is only the preferred embodiments of the present application. It should be understood that the present application is not limited to the forms disclosed herein, and should not be considered as excluding other embodiments. The present application can be used in various other combinations, modifications and environments, and can be modified within the scope of the concepts described herein, by the above teachings or related art or knowledge. Any modification and change made by those skilled in the art without departing from the spirit and scope of the present application shall be within the protection scope of the appended claims of the present application. ​

Claims

1. A clock generation circuit for a time-interleaved ADC, characterized by: The delay circuit Delay, the frequency division module and the first D flip-flop, an input end of the delay circuit Delay, the frequency division module and the first D flip-flop receives an external clock signal CLK; The delay circuit Delay is used for generating an external clock signal CLK after timing adjustment and inputting to a pulse width adjustment circuit CLK_sample; the pulse width adjustment circuit CLK_sample is used for generating a sampling clock signal CLKS with adjustable pulse width and inputting to a second AND gate group; The frequency division module divides the external clock signal CLK into multiple input paths to the first AND gate group for two-by-two combination to obtain multiple intermediate clock signals, and inputs the multiple intermediate clock signals to the second AND gate group; the second AND gate group performs AND operation on the sampling clock signal CLKS and each intermediate clock signal to obtain multiple multi-phase clock sampling signals, and inputs the multiple multi-phase clock sampling signals to each sub-ADC module of the time-interleaved ADC for time-interleaved sampling and analog-to-digital conversion; Each sub-ADC module outputs a digital signal to a multiplexer MUX circuit to combine into one data output signal, and inputs the data output signal to a first D flip-flop driven by the external clock signal CLK for synchronization and then outputs a final signal.

2. The clock generation circuit for a time-interleaved ADC of claim 1, wherein: The frequency division module includes at least one frequency divider; the first AND gate group includes multiple AND gates, and the second AND gate group also includes multiple AND gates.

3. The clock generation circuit for a time-interleaved ADC of claim 1, wherein: The duty cycle of the intermediate clock signal is 25%, and the duty cycle of the multiple frequency division signals output by the frequency division module is 50%.

4. The clock generation circuit for a time-interleaved ADC of claim 1, wherein: The multiplexer MUX circuit is driven by the intermediate clock signal.

5. The clock generation circuit for a time-interleaved ADC of claim 2, wherein: The frequency divider is a D flip-flop with an inverting output end feedback connected to a D input end.

6. The clock generation circuit for a time-interleaved ADC of any of claims 1-5, wherein: The pulse width adjusting circuit CLK_sample comprises a second D flip-flop with a reset function, an input end of the second D flip-flop is connected to a high potential VDD, a clock port of the second D flip-flop receives an external clock signal CLK through a delay circuit Delay, an output end of the second D flip-flop is connected to an input end of each AND gate in a second inverter and second AND gate group; an output end of the inverter is connected to a plurality of series-connected delay units DELAY cell; an output signal of each delay unit DELAY cell is output to an input end of a multiplexer MUX; the multiplexer MUX outputs a signal according to a plurality of bit control signals PULSE <n:0>One path of delay signal is selected to be output to a first input end of the first AND gate to adjust the pulse width of the sampling clock signal CLKS; a second input end of the first AND gate receives an external reset control signal RST, and an output end of the first AND gate is connected to a reset control port of the second D flip-flop.< / n:0>

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