Multi-channel comparator multiplexing circuit of high-speed and high-energy-efficiency time sequence interleaving architecture
By introducing a high-speed, high-efficiency, timing-interleaved multi-channel comparator multiplexing circuit into the SAR ADC, and utilizing the alternating operation of the preamplifier and latch, the problems of slow conversion speed and high power consumption of traditional SAR ADCs are solved, achieving the effect of low-power and fast conversion.
Patent Information
- Application Number
- CN202511059894.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-30
- Publication Date
- 2025-11-18
AI Technical Summary
Traditional SAR ADCs have slow conversion speeds and high power consumption, mainly due to the serial operation of traditional dynamic comparators and unnecessary power dissipation.
A multi-channel comparator multiplexing circuit with a high-speed, high-efficiency, timing interleaved architecture is used to amplify the signal by alternating charging and discharging of a preamplifier and multiple latches. After reaching the preset gain, the latches are triggered to work, and the working timing is cyclically expanded to achieve resetless operation of the multi-channel comparator.
This improved the conversion speed of the ADC, reduced system power consumption, and enabled low power consumption and fast conversion of the multi-channel comparator.
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Figure CN120979453A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of digital signal processing system, and particularly relates to a multi-channel comparator multiplexing circuit of high-speed and high-energy efficiency time interleaving architecture. BACKGROUND
[0002] Under the driving of the explosive growth of Internet of Things devices and the development of ultra-high-speed communication links, the demand for high-speed and high-energy efficiency analog-to-digital converters (ADCs) of digital signal processing systems presents a multi-dimensional upgrading trend. As a bridge between the analog and digital domains, the dynamic performance of ADCs directly determines the signal quality of the system. Successive approximation register analog-to-digital converters (SAR ADCs) have become a research hotspot due to their high speed, low power consumption and high digitalization. The speed, accuracy and power consumption of the dynamic comparator are the key to determining the overall performance of the system.
[0003] At present, the sampling rate of the traditional SAR ADC is limited by the serial working process of the quantization stage. The traditional dynamic comparator in the traditional SAR ADC is composed of a preamplifier and a single latch. However, the working timing of the SAR ADC based on a single comparator needs to strictly follow the serial working process of comparison, latching and resetting, which makes the conversion speed of the ADC slow. Moreover, the voltage establishment of the capacitor digital-to-analog converter (CDAC) cannot start until the latching of the current comparison result is completed, which also causes a series of unnecessary power dissipation, resulting in high power consumption of the system. SUMMARY
[0004] The purpose of the embodiments of the present application is to provide a multi-channel comparator multiplexing circuit of high-speed and high-energy efficiency time interleaving architecture, which solves the problems of high power consumption of the system and slow conversion speed of the ADC in the prior art.
[0005] To solve the above technical problems, the embodiments of the present application provide the following technical solutions: The first aspect of the present application provides a multi-channel comparator multiplexing circuit of high-speed and high-energy efficiency time interleaving architecture, comprising a preamplifier, a plurality of latches, a node VIPS and a node VINS. A preamplifier, connected with the node VIPS and the node VINS, is used for amplifying the voltage of the node VIPS and the voltage of the node VINS in the multiple comparison operation in the form of charging and discharging alternation, generating the amplified voltage difference corresponding to each comparison operation, and triggering the corresponding latch operation after reaching the preset amplification gain. A plurality of latches, connected with the preamplifier, are used for latching the amplified voltage difference to obtain the corresponding comparison result.
[0006] The second aspect of the application provides a successive approximation type analog-to-digital converter, comprising a multi-channel comparator multiplexing circuit of a high-speed high-energy efficiency time interleaving architecture, and the successive approximation type analog-to-digital converter further comprises: a switch S1, a switch S2, a sampling clock, a first differential input signal VIP, a second differential input signal VIN, a first capacitive digital-to-analog converter, a second capacitive digital-to-analog converter, and a successive approximation control logic, a first reference voltage, a second reference voltage, and a digital output terminal. One end of the switch S1 is connected with the first differential input signal VIP, the control end of the switch S1 is connected with the sampling clock, and the other end of the switch S1, the non-inverting input end of the multi-channel comparator multiplexing circuit, and one end of the first capacitive digital-to-analog converter are commonly connected to the node VIPS; one end of the switch S2 is connected with the second differential input signal VIN, the control end of the switch S2 is connected with the sampling clock, and the other end of the switch S2, the inverting input end of the multi-channel comparator multiplexing circuit, and one end of the second capacitive digital-to-analog converter are commonly connected to the node VINS; the output end of the multi-channel comparator multiplexing circuit, the other end of the first capacitive digital-to-analog converter, the other end of the second capacitive digital-to-analog converter, and the digital output terminal are all connected with the successive approximation control logic. The first capacitive digital-to-analog converter and the second capacitive digital-to-analog converter are both connected with the first reference voltage and the second reference voltage. The successive approximation control logic is used for generating the control signal of the first capacitive digital-to-analog converter and the second capacitive digital-to-analog converter according to the comparison result, and generating the signal of the first comparator clock and the signal of the second comparator clock. The first capacitive digital-to-analog converter and the second capacitive digital-to-analog converter are both used for generating the corresponding reference voltage according to the comparison result when the successive approximation control logic generates the control signal, and changing the voltage of the node VIPS and the voltage of the node VINS according to the reference voltage.
[0007] Compared with the prior art, the multi-channel comparator multiplexing circuit of the high-speed high-energy efficiency time interleaving architecture provided by the application comprises a preamplifier, a plurality of latches, a node VIPS and a node VINS; the preamplifier is connected with the node VIPS and the node VINS, and is used for amplifying the voltage of the node VIPS and the voltage of the node VINS in multiple comparison operations in the form of charging and discharging alternation, generating an amplified voltage difference corresponding to each comparison operation, and triggering the corresponding latch to work after reaching a preset amplification gain; the plurality of latches are connected with the preamplifier, and are used for latching the amplified voltage difference to obtain a corresponding comparison result. In this way, the preamplifier amplifies the voltage of the node VIPS and the voltage of the node VINS in multiple comparison operations in the form of charging and discharging alternation, that is, the preamplifier amplifies through the complementary working process of adjacent two comparisons, generates a plurality of amplified voltage differences corresponding to multiple comparison operations through the preamplifier, and activates the corresponding latch in a cyclic expansion working time sequence, so as to realize the reset-free operation of the multi-channel comparator multiplexing, save the time sequence overhead, allow the voltage establishment and the next comparison trigger to be performed synchronously, make the power consumption of the multi-channel comparator multiplexing circuit lower, and make the conversion speed of the SAR ADC faster. BRIEF DESCRIPTION OF DRAWINGS
[0008] The above and other objects, features and advantages of the exemplary embodiments of the present application will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which several embodiments of the present application are shown by way of example, and wherein like or corresponding elements refer to like or corresponding parts throughout. In the drawings: Figure 1 A structural schematic diagram of the multi-channel comparator multiplexing circuit of the high-speed high-energy efficiency time interleaving architecture is schematically shown; Figure 2 A structural schematic diagram of the successive approximation type analog-digital converter is schematically shown; Figure 3 A working time sequence diagram of the successive approximation type analog-digital converter is schematically shown. DETAILED DESCRIPTION
[0009] The embodiments of the present application will be further described in detail below with reference to the accompanying drawings and examples. The detailed description and the accompanying drawings of the following examples are used to exemplarily illustrate the principles of the present application, but cannot be used to limit the scope of the present application, and the present application can be implemented in many different forms, and is not limited to the specific examples disclosed herein, but includes all technical solutions falling within the scope of the claims.
[0010] The structural schematic diagram of the multi-channel comparator multiplexing circuit of the high-speed high-energy efficiency time interleaving architecture in the embodiment of the present application is described in detail below.
[0011] Referring to Figure 1 as shown, Figure 1 The structure of the multi-channel comparator multiplexing circuit of the high-speed high-energy efficiency time interleaving architecture is schematically shown. The embodiment of the present application provides a multi-channel comparator multiplexing circuit of a high-speed high-energy efficiency time interleaving architecture, which comprises a preamplifier, a plurality of latches, a node VIPS and a node VINS. The preamplifier is connected to the node VIPS and the node VINS, and is used to amplify the voltage of the node VIPS and the voltage of the node VINS in multiple comparison operations in the form of charging and discharging alternation, to generate an amplified voltage difference corresponding to each comparison operation, and to trigger the corresponding latch operation after reaching a preset amplification gain. The plurality of latches are connected to the preamplifier, and are used to latch the amplified voltage difference to obtain the corresponding comparison result.
[0012] In the embodiment, the preamplifier comprises MOS tubes M0, M1, M2, M3, M4, M5, a first comparator clock and a positive power supply terminal. The gate terminals of the MOS tubes M0 and M1 are connected to the first comparator clock, the drain terminal of the MOS tube M0 is connected to the source terminals of the MOS tubes M2 and M3, the source terminal of the MOS tube M0 is grounded, the drain terminals of the MOS tubes M2 and M4 are connected to the node AP, the gate terminals of the MOS tubes M2 and M4 are connected to the node VIPS, the gate terminals of the MOS tubes M3 and M5 are connected to the node VINS, the drain terminals of the MOS tubes M3 and M5 are connected to the node AN, the source terminals of the MOS tubes M4 and M5 are connected to the drain terminal of the MOS tube M1, and the source terminal of the MOS tube M1 is connected to the positive power supply terminal.
[0013] In the embodiment, the structures of the plurality of latches are the same.
[0014] In the embodiment, the structure of each latch comprises MOS tubes M6, M7, M8, M9, M10, M11, M12, M13, M14, a second comparator clock, a positive power supply terminal, a first comparison result node and a second comparison result node. The gate end of MOS transistor M7 is connected with node AN, the gate end of MOS transistor M8 is connected with node AP, the source end of MOS transistor M6 is grounded, the gate end of MOS transistor M6, the gate end of MOS transistor M11 and the gate end of MOS transistor M12 are all connected with the second comparator clock, the drain end of MOS transistor M6 is connected with the source end of MOS transistor M7, the source end of MOS transistor M9, the source end of MOS transistor M10 and the source end of MOS transistor M8, the drain end of MOS transistor M7 and the drain end of MOS transistor M11 are both connected with node Al, the drain end of MOS transistor M9 and the drain end of MOS transistor M13 are both connected with node A2, the gate end of MOS transistor M9 and the gate end of MOS transistor M13 are both connected with node A3, the gate end of MOS transistor M10 and the gate end of MOS transistor M14 are both connected with node A4, the drain end of MOS transistor M10 and the drain end of MOS transistor M14 are both connected with node A5, the drain end of MOS transistor M8 and the drain end of MOS transistor M12 are both connected with node A6, the source end of MOS transistor M11, the source end of MOS transistor M13, the source end of MOS transistor M14 and the source end of MOS transistor M12 are all connected with the positive end of power supply, node Al and node A3 are both connected with the first comparison result node, node A2 and node A4 are both connected with the second comparison result node.
[0015] In the embodiment, MOS transistor M2, MOS transistor M3, MOS transistor M4 and MOS transistor M5 are all input differential pair transistors.
[0016] In the embodiment, the cross-coupled inverter is composed of MOS transistor M9, MOS transistor M10, MOS transistor M13 and MOS transistor M14.
[0017] Specifically, the application utilizes the advantage of high speed and low power consumption in the ADC conversion process based on the working timing of cycle expansion. The multi-channel comparator of the high-speed and high-energy efficiency timing interlaced architecture is composed of a complementary working pre-amplifier and sequentially activated multiple latches. The MOS tube M2, MOS tube M3, MOS tube M4 and MOS tube M5 of the pre-amplifier in the comparator are input differential pair tubes, the gate end of the input differential pair tubes is directly connected to the top plate of the first and second capacitive digital-to-analog converters, the source end of the input differential pair tubes is respectively connected to the tail current tubes M0 and M1 controlled by the first comparator clock Clkc1, and the node AP and node AN of the drain end of the input differential pair tubes are the output ends of the pre-amplifier. The node AP and node AN are simultaneously connected to the gate end of the input pair tubes M7 and M8 of the second multiple latches of the multi-channel comparator of the high-speed and high-energy efficiency timing interlaced architecture, each latch contains the tail current tube M6 controlled by the second comparator clock Clkc2, and the reset tubes M11 and M12, and further includes the cross-coupled inverter composed of M9, M10, M13 and M14, and the output ends of the cross-coupled inverter are respectively the first comparison result node D and the second comparison result node DB of the multi-channel comparator. The multi-channel comparator of the high-speed and high-energy efficiency timing interlaced architecture can eliminate the comparator reset stage and the comparison result latch stage in the ADC conversion process while maintaining the single comparison speed, thereby reducing the system power consumption, and at the same time, the conversion speed of the ADC can be improved.
[0018] Referring to Figure 2 as shown, Figure 2 The structure schematic diagram of the successive approximation type analog-to-digital converter is schematically shown, and the embodiment of the application proposes a successive approximation type analog-to-digital converter comprising a multi-channel comparator multiplexing circuit of a high-speed and high-energy efficiency timing interlaced architecture, and the successive approximation type analog-to-digital converter further comprises: a switch S1, a switch S2, a sampling clock, a first differential input signal VIP, a second differential input signal VIN, a first capacitive digital-to-analog converter, a second capacitive digital-to-analog converter, a successive approximation control logic, a first reference voltage, a second reference voltage and a digital output end; One end of the switch S1 is connected with the first differential input signal VIP, the control end of the switch S1 is connected with the sampling clock, and the other end of the switch S1, the non-inverting input end of the multi-channel comparator multiplexing circuit and one end of the first capacitive digital-to-analog converter are commonly connected to the node VIPS. One end of the switch S2 is connected with the second differential input signal VIN, the control end of the switch S2 is connected with the sampling clock, and the other end of the switch S2, the inverting input end of the multi-channel comparator multiplexing circuit and one end of the second capacitive digital-to-analog converter are commonly connected to the node VINS. The output end of the multi-channel comparator multiplexing circuit, the other end of the first capacitive digital-to-analog converter, the other end of the second capacitive digital-to-analog converter and the digital output end are all connected with the successive approximation control logic. The first and second capacitor type digital-to-analog converters are connected with the first and second reference voltages respectively; The successive approximation control logic is configured to generate control signals for controlling the first and second capacitor type digital-to-analog converters according to the comparison results, and generate signals for the first and second comparator clocks. The first and second capacitor type digital-to-analog converters are configured to generate corresponding reference voltages according to the comparison results when the successive approximation control logic generates the control signals, and change the voltages of the nodes VIPS and VINS according to the reference voltages.
[0019] In the embodiment, the first capacitor type digital-to-analog converter includes a plurality of identical first unit structures, and the second capacitor type digital-to-analog converter includes a plurality of identical second unit structures.
[0020] In the embodiment, each first unit structure includes a capacitor C1, a transistor switch S3 and a transistor switch S4. The top plate of the capacitor C1, the other end of the switch S1 and the non-inverting input terminal of the multi-channel comparator multiplexing circuit are connected to the node VIPS, the bottom plate of the capacitor C1 is connected with the source terminal of the transistor switch S3 and the source terminal of the transistor switch S4, the gate terminal of the transistor switch S3 is connected with the successive approximation control logic, the drain terminal of the transistor switch S3 is connected with the first reference voltage, the gate terminal of the transistor switch S4 is connected with the successive approximation control logic, and the drain terminal of the transistor switch S4 is connected with the second reference voltage. Each second unit structure includes a capacitor C2, a transistor switch S5 and a transistor switch S6. The top plate of the capacitor C2, the other end of the switch S2 and the inverting input terminal of the multi-channel comparator multiplexing circuit are connected to the node VINS, the bottom plate of the capacitor C2 is connected with the source terminal of the transistor switch S5 and the source terminal of the transistor switch S6, the gate terminal of the transistor switch S5 is connected with the successive approximation control logic, the drain terminal of the transistor switch S5 is connected with the first reference voltage VREFp, the gate terminal of the transistor switch S6 is connected with the successive approximation control logic, and the drain terminal of the transistor switch S6 is connected with the second reference voltage VREFn.
[0021] In the embodiment, the number of the plurality of latches is the same as the number of bits of the successive approximation type analog-to-digital converter.
[0022] Specifically, Figure 3 The working timing diagram of the successive approximation type analog-to-digital converter is schematically shown, referring to Figure 2 and Figure 3As shown, the first differential input signal VIP and the second differential input signal VIN are differential input signals of the successive approximation type analog-to-digital converter, the first differential input signal VIP and the second differential input signal VIN are connected to the top plates of the first capacitive digital-to-analog converter CDACp and the second capacitive digital-to-analog converter CDACn through switches S1 and S2 respectively, the on-off states of the switches are controlled by the sampling clock Clks, and the start of the multi-channel comparison is controlled by the first comparator clock Clkc1 and the second comparator clock Clkc2[1] generated by the successive approximation control logic. The working principle of the successive approximation type analog-to-digital converter is as follows: in each conversion period, during the sampling stage, the sampling clock Clks becomes high, the switches S1 and S2 are turned on, the first differential input signal VIP and the second differential input signal VIN are sampled to the nodes VIPS and VINS corresponding to the top plates of the first capacitive digital-to-analog converter CDACp and the second capacitive digital-to-analog converter CDACn respectively, at this time, the first comparator clock Clkc1 and the second comparator clock Clkc2[1] are low, the multi-channel comparator does not work, the nodes AP and AN in the middle of the multi-channel comparator remain high, and the output of the multi-channel comparator is reset to high.
[0023] In the quantization stage, the sampling clock Clks becomes low, the switches S1 and S2 are turned off, the sampled input signals of the nodes VIPS and VINS are kept on the differential CDAC capacitor array, the first comparator clock Clkc1 and the second comparator clock Clkc2[1] controlled by the successive approximation control logic become high, and the rest of the comparator clocks remain low, at this time, the first bit digital code quantization is performed, and the multi-channel comparator starts the first comparison of the signals on the CDAC top plate. In the quantization of the first bit digital code, the preamplifier and the first latch in the multi-channel comparator work, since the first comparator clock Clkc1 is high, the tail current tube M0 is turned on and M1 is turned off, the preamplifier amplifies in the discharge process. If VIPS>VINS, the discharge current of the input tube M2 will be greater than that of the input tube M3, so that the voltage at the node AP is lower than that at the node AN, in the first latch, since the second comparator clock Clkc2[1] is high, the reset tubes M11 and M12 are turned off, and the tail current tube M6 is turned on, the first latch latches the output of the preamplifier, since the voltage at the node AP is lower than that at the node AN, the current of the input tube M7 in the first latch will be less than that of the input tube M8, resulting in that the voltage of the first comparison result node D of the multi-channel comparator will be higher than that of the second comparison result node DB, so that the cross-coupled inverter quickly latches the first comparison result node D and the second comparison result node DB to high and low respectively, obtaining the first bit digital code D[1], and the opposite is true when VIPS<VINS.
[0024] After the first bit digital code quantization, the comparison result is directly latched in the first latch of the multi-channel comparator, and through the switch in the successive approximation control logic, the control logic can directly switch the switch of the CDAC bottom plate to establish the voltage, and at the same time, the trigger of the comparison clock of the next comparison of the multi-channel comparator can be performed, and in this process, the nodes AP and AN of the preamplifier in the multi-channel comparator are discharged to the low level. After the first CDAC voltage establishment is completed, the successive approximation control logic controls the first comparator clock Clkc1 to become low, and the second comparator clock Clkc2[2] becomes high, and the rest of the clocks remain unchanged, at this time, the second bit digital code quantization is performed, and the multi-channel comparator starts the second comparison of the signal on the CDAC top plate.
[0025] When quantizing the second bit digital code, the preamplifier and the second latch of the multi-channel comparator work, since the first comparator clock Clkc1 is low, the tail current tube M1 is turned on, M0 is turned off, and the preamplifier amplifies in the charging process. If VIPS>VINS, the charging current of the input tube M4 will be smaller than that of the input tube M5, so that the voltage at the node AP is lower than that at the node AN. In the second latch, since the second comparator clock Clkc[2] is high, the reset tubes M11 and M12 are turned off, and the tail current tube M6 is turned on. The second latch latches the output of the preamplifier. Since the voltage at the node AP is lower than that at the node AN, the current of the input tube M7 of the second latch will be smaller than that of the input tube M8, resulting in that the voltage of the first comparison result node D of the multi-channel comparator will be higher than that of the second comparison result node DB, so that the cross-coupled inverter quickly latches the first comparison result node D and the second comparison result node DB to high and low respectively, obtaining the second bit digital code D[2], and when VIPS<VINS, the opposite is true.
[0026] After the second bit digital code quantization, the comparison result is also latched in the second latch of the multi-channel comparator, and through the successive approximation control logic, the voltage establishment of the CDAC and the trigger of the comparison clock of the next comparison are performed at the same time, and in this process, the nodes AP and AN of the preamplifier in the multi-channel comparator are charged to the high level. After the second CDAC voltage establishment is completed, the successive approximation control logic controls the first comparator clock Clkc1 to become high again, and the second comparator clock Clkc2[3] becomes high, and the rest of the clocks remain unchanged, at this time, the third bit digital code quantization is performed, and the multi-channel comparator starts the third comparison of the signal on the CDAC top plate, and the working process is the same as that of the first comparison, obtaining the third bit digital code D[3].
[0027] Then, after the fourth CDAC voltage is established completely, the successive approximation control logic controls the first comparator clock Clkc1 to be low again and the second comparator clock Clkc2[4] to be high, and the rest of the clocks remain unchanged, at this time, the fourth bit digital code quantization is performed, and the fourth bit digital code D[4] is obtained. In this way, until all the digital codes are quantized, at this time, the successive approximation control logic outputs all the comparison results latched in the multi-channel comparator through the digital output terminal DOUT, that is, the corresponding digital code obtained by converting the analog input, and resets all the comparison clocks of the multi-channel comparator, the first comparator clock Clkc1 and the second comparator clock Clkc2[:] become low, and a conversion period ends, the output of the preamplifier and the latch is charged to high to perform the next conversion.
[0028] Since the preamplifier in the multi-channel comparator amplifies in the complementary working process of adjacent two comparisons, and the latch adopts a loop-unrolled working timing, the multi-channel comparator multiplexing circuit of the high-speed and high-energy-efficient timing interlaced architecture eliminates the reset phase of the multi-channel comparator in the SAR ADC compared with the SAR ADC adopting the traditional dynamic comparator, reduces the additional time and power consumption overhead required for latching the comparison result of the SAR ADC, and can realize the simultaneous establishment of the CDAC voltage and the triggering of the comparison clock, thereby realizing the high-speed working of the SAR ADC quantization phase and having lower dynamic power consumption.
[0029] The high-speed and high-energy-efficient timing interlaced architecture multi-channel comparator multiplexing circuit of the embodiment of the application comprises a preamplifier, a plurality of latches, a node VIPS and a node VINS; the preamplifier is connected with the node VIPS and the node VINS, and is used for amplifying the voltage of the node VIPS and the voltage of the node VINS in a plurality of comparison operations in an alternating form of charging and discharging, generating a plurality of amplified voltage differences corresponding to the plurality of comparison operations, and triggering the corresponding latches to work after reaching a preset amplification gain; the plurality of latches are connected with the preamplifier, and are used for latching the amplified voltage differences to obtain corresponding comparison results. In this way, the preamplifier amplifies the voltage of the node VIPS and the voltage of the node VINS in a plurality of comparison operations in an alternating form of charging and discharging, that is, the preamplifier amplifies in the complementary working process of adjacent two comparisons, generates a plurality of amplified voltage differences corresponding to the plurality of comparison operations, sequentially activates the corresponding latches in a loop-unrolled working timing sequence, realizes the reset-free operation of the multi-channel comparator multiplexing, saves the timing overhead, allows the voltage to be established and the next comparison to be triggered synchronously, so that the power consumption of the multi-channel comparator multiplexing circuit is low and the conversion speed of the SAR ADC is fast.
[0030] Although some specific embodiments of the present application have been described in detail by way of examples, one skilled in the art should understand that the above examples are only for the purpose of illustration, but not for the purpose of limiting the scope of the present application. One skilled in the art should understand that the above embodiments can be modified or equivalent replacements can be made to some technical features without departing from the scope and spirit of the present application. In particular, each technical feature mentioned in each embodiment can be combined in any manner as long as there is no structural conflict.
[0031] The above merely illustrates the specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims
1. A multi-channel comparator multiplexing circuit with a high-speed, high-efficiency, sequentially interleaved architecture, characterized in that, The multi-channel comparator multiplexing circuit includes a preamplifier, multiple latches, a VIPS node, and a VINS node. The preamplifier is connected to both the VIPS node and the VINS node. During multiple comparison operations, it amplifies the voltage of the VIPS node and the VINS node by alternating charging and discharging to generate the amplified voltage difference corresponding to each comparison operation. After reaching the preset amplification gain, it triggers the corresponding latch to work. The plurality of latches are all connected to the preamplifier and are used to latch the amplified voltage difference to obtain the corresponding comparison result.
2. The multi-channel comparator multiplexing circuit with a high-speed, high-efficiency timing interleaved architecture according to claim 1, characterized in that, The preamplifier includes MOSFETs M0, M1, M2, M3, M4, and M5, a first comparator clock, and a positive power supply terminal; The gate terminals of MOSFET M0 and M1 are both connected to the clock of the first comparator. The drain terminal of MOSFET M0 is connected to the source terminals of MOSFET M2 and M3. The source terminal of MOSFET M0 is grounded. The drain terminals of MOSFET M2 and M4 are connected to node AP. The gate terminals of MOSFET M2 and M4 are both connected to node VIPS. The gate terminals of MOSFET M3 and M5 are both connected to node VINS. The drain terminals of MOSFET M3 and M5 are both connected to node AN. The source terminals of MOSFET M4 and M5 are both connected to the drain terminal of MOSFET M1. The source terminal of MOSFET M1 is connected to the positive power supply terminal.
3. The multi-channel comparator multiplexing circuit with a high-speed, high-efficiency timing interleaving architecture according to claim 2, characterized in that, The structures of the multiple latches are all identical.
4. The multi-channel comparator multiplexing circuit with a high-speed, high-efficiency timing interleaving architecture according to claim 3, characterized in that, Each latch structure includes MOSFETs M6, M7, M8, M9, M10, M11, M12, M13, and M14, a second comparator clock, the positive terminal of the power supply, a first comparison result node, and a second comparison result node; The gate of MOSFET M7 is connected to node AN, the gate of MOSFET M8 is connected to node AP, the source of MOSFET M6 is grounded, and the gates of MOSFET M6, MOSFET M11, and MOSFET M12 are all connected to the clock of the second comparator. The drain of MOSFET M6 is connected to the sources of MOSFET M7, MOSFET M9, MOSFET M10, and MOSFET M8. The drain of MOSFET M7 and MOSFET M11 are shared at node A1, and the drain of MOSFET M9 and MOSFET M13 are shared at node A2. The gate of M9 is connected to the gate of MOSFET M13 at node A3. The gate of MOSFET M10 is connected to the gate of MOSFET M14 at node A4. The drain of MOSFET M10 is connected to the drain of MOSFET M14 at node A5. The drain of MOSFET M8 is connected to the drain of MOSFET M12 at node A6. The sources of MOSFETs M11, M13, M14, and M12 are all connected to the positive power supply terminal. Nodes A1 and A3 are both connected to the first comparison result node. Nodes A2 and A4 are both connected to the second comparison result node.
5. The multi-channel comparator multiplexing circuit with a high-speed, high-efficiency timing interleaved architecture according to claim 2, characterized in that, The MOS transistors M2, M3, M4, and M5 are all input differential pairs.
6. The multi-channel comparator multiplexing circuit with a high-speed, high-efficiency timing interleaved architecture according to claim 4, characterized in that, The cross-coupled inverter is composed of MOSFET M9, MOSFET M10, MOSFET M13 and MOSFET M14.
7. A successive approximation analog-to-digital converter, characterized in that, The multi-channel comparator multiplexing circuit with a high-speed, high-efficiency timing interleaved architecture as described in any one of claims 1-6, wherein the successive approximation analog-to-digital converter further includes: switch S1, switch S2, sampling clock, first differential input signal VIP, second differential input signal VIN, first capacitive digital-to-analog converter, second capacitive digital-to-analog converter, successive approximation control logic, first reference voltage, second reference voltage, and digital output terminal; One end of switch S1 is connected to the first differential input signal VIP, and the control terminal of switch S1 is connected to the sampling clock. The other end of switch S1, the non-inverting input terminal of the multi-channel comparator multiplexing circuit, and one end of the first capacitive digital-to-analog converter are all connected to node VIS. One end of switch S2 is connected to the second differential input signal VIN, and the control terminal of switch S2 is connected to the sampling clock. The other end of switch S2, the inverting input terminal of the multi-channel comparator multiplexing circuit, and one end of the second capacitive digital-to-analog converter are all connected to node VINS. The successive approximation control logic is connected to the output terminal of the multi-channel comparator multiplexing circuit, the other end of the first capacitive digital-to-analog converter, the other end of the second capacitive digital-to-analog converter, and the digital output terminal. Both the first capacitive digital-to-analog converter and the second capacitive digital-to-analog converter are connected to the first reference voltage and the second reference voltage; The successive approximation control logic is used to generate control signals for the first capacitive digital-to-analog converter and the second capacitive digital-to-analog converter based on the comparison result, and to generate a first comparator clock signal and a second comparator clock signal. Both the first capacitive digital-to-analog converter and the second capacitive digital-to-analog converter are used to generate a corresponding reference voltage based on the comparison result when the successive approximation control logic generates the control signal, and to change the voltage of the node VIPS and the voltage of the node VINS based on the reference voltage.
8. The successive approximation analog-to-digital converter according to claim 7, characterized in that, The first capacitive digital-to-analog converter includes multiple identical first unit structures, and the second capacitive digital-to-analog converters each include multiple identical second unit structures.
9. The successive approximation analog-to-digital converter according to claim 8, characterized in that, Each first unit structure includes a capacitor C1, a transistor switch S3, and a transistor switch S4; The top plate of capacitor C1, the other end of switch S1, and the non-inverting input of the multi-channel comparator multiplexing circuit are all connected to node VIPS. The bottom plate of capacitor C1 is connected to the source terminals of transistor switch S3 and transistor switch S4. The gate terminal of transistor switch S3 is connected to the successive approximation control logic. The drain terminal of transistor switch S3 is connected to the first reference voltage. The gate terminal of transistor switch S4 is connected to the successive approximation control logic. The drain terminal of transistor switch S4 is connected to the second reference voltage. Each second unit structure includes a capacitor C2, a transistor switch S5, and a transistor switch S6; The top plate of capacitor C2, the other end of switch S2, and the inverting input of the multi-channel comparator multiplexing circuit are all connected to node VINS. The bottom plate of capacitor C2 is connected to the source terminals of transistor switch S5 and transistor switch S6. The gate terminal of transistor switch S5 is connected to the successive approximation control logic. The drain terminal of transistor switch S5 is connected to the first reference voltage. The gate terminal of transistor switch S6 is connected to the successive approximation control logic. The drain terminal of transistor switch S6 is connected to the second reference voltage.
10. The successive approximation analog-to-digital converter according to claim 7, characterized in that, The number of the plurality of latches is the same as the number of bits of the successive approximation analog-to-digital converter.