Implementation method of FMQL-based multi-clock-source configurable high-precision time synchronization system

Abstract

The invention relates to an implementation method of a multi-clock-source configurable high-precision time synchronization system based on FMQL, and belongs to the technical field of time synchronization. The system comprises a timing system board card, an exchange board card and a mainboard, the timing system board card takes an FMQL chip as a core and receives and decodes a time service signal source in real time, and the time service signal source comprises a PTP, a B code and a TOD; the PL end of the FMQL runs a decoding time algorithm, and then encodes the decoded time information into a PTP message and sends the PTP message to the network; and the PS end of the FMQL runs the control logic, and controls the mode selection of the PL end according to the instruction sent by the main control board card. According to the invention, nanosecond-level time synchronization precision can be realized, time service sources can be flexibly switched in various complex environments, and the overall performance and reliability of the system are significantly improved.

Description

Technical Field

[0001] This invention belongs to the field of time synchronization technology, specifically relating to a method for implementing a high-precision time synchronization system based on FMQL with multiple configurable clock sources. Background Technology

[0002] With the rapid development of information technology, the requirements for the accuracy and stability of time synchronization are increasing. Accurate time synchronization is fundamental to ensuring normal system operation, data consistency, and security. Existing time synchronization systems often rely on a single time source, which can easily lead to decreased synchronization accuracy or even system failure when the time source is unreliable or interfered with. Furthermore, traditional time synchronization systems lack sufficient flexibility and adaptability when facing complex and ever-changing external environments. Summary of the Invention

[0003] (a) Technical problems to be solved

[0004] The technical problem to be solved by this invention is how to provide a method for implementing a high-precision time synchronization system based on FMQL with multiple configurable clock sources, so as to solve the problem that traditional time synchronization systems lack sufficient flexibility and adaptability when facing complex and ever-changing external environments.

[0005] (II) Technical Solution

[0006] To address the aforementioned technical problems, this invention proposes a method for implementing a high-precision time synchronization system based on FMQL with multiple configurable clock sources. The system includes: a time synchronization board, a switching board, and a motherboard.

[0007] The timing board, with the FMQL chip as its core, receives and decodes timing signals in real time. The timing signals include PTP, B code, and TOD. The PL end of FMQL runs the decoding time algorithm and then encodes the decoded time information into a PTP message and sends it to the network. The PS end of FMQL runs the control logic and controls the mode selection of the PL end according to the instructions sent by the main control board.

[0008] The switching board is used to establish a network path between the timing board and each motherboard, transmit the PTP messages sent by the timing board to each motherboard for timing synchronization, and transmit the control messages sent by the main control board to the timing board.

[0009] The motherboard consists of one main control board and three service boards. The host computer software runs on the main control board and can view the status of the three timing signal sources in real time and set the mode for the timing board to select the clock source.

[0010] (III) Beneficial Effects

[0011] This invention proposes a method for implementing a high-precision time synchronization system with multiple configurable clock sources based on FMQL. The invention includes a system architecture centered on FMQL, an algorithm for switching the optimal clock source, and software. It designs priority scoring and sorting methods for PTP, TOD, and B codes, achieving nanosecond-level time synchronization accuracy and enabling flexible switching of time sources in various complex environments, significantly improving the overall performance and reliability of the system. It can be widely applied in aerospace, autonomous driving, precision manufacturing, smart grids, and other fields with stringent requirements for time synchronization accuracy and reliability. Attached Figure Description

[0012] Figure 1 This is a diagram of the FMQL-based time synchronization system architecture of the present invention;

[0013] Figure 2 A schematic diagram of the host computer software running on the main control board;

[0014] Figure 3 This is a flowchart of the control algorithm for the operation of the timing board. Detailed Implementation

[0015] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0016] This invention relates to the field of high-precision time synchronization technology, specifically to a method for implementing a high-precision time synchronization system based on FMQL with multiple configurable clock sources, applicable to time synchronization scenarios in fields such as communication networks and industrial control.

[0017] The technical problem this invention aims to solve is how to provide a method for implementing a high-precision time synchronization system based on FMQL with multiple configurable clock sources. Specifically, the problems to be solved include: how to design a system architecture with multiple configurable clock sources, and how to design algorithms and software to achieve flexible switching between multiple clock sources.

[0018] To address the aforementioned technical problems, this invention proposes a method for implementing a high-precision time synchronization system based on FMQL with multiple configurable clock sources. This system can flexibly configure multiple clock sources (including PTP, B-code, and TOD) and select the optimal clock source through an automatic source selection algorithm, thereby ensuring high precision and stability of time synchronization. It can also manually switch the time source according to the needs of different environments, significantly improving system reliability. The system includes: a time synchronization board, a switching board, a motherboard (including a main control board and service boards), and corresponding algorithm software. The system architecture is as follows: Figure 1 As shown.

[0019] The timing board, with the FMQL chip at its core, receives and decodes timing signals (PTP, B code, TOD) in real time. The PL (Programmable Logic Unit) of the FMQL runs the decoding timing algorithm, and then encodes the decoded time information into a PTP message for transmission over the network. The PS (Power Supply Unit) of the FMQL runs the control logic, controlling the mode selection of the PL based on instructions sent by the main control board.

[0020] The switching board is used to establish a network path between the timing board and each motherboard, transmit the PTP messages sent by the timing board to each motherboard for timing synchronization, and transmit the control messages sent by the main control board to the timing board.

[0021] The motherboard consists of one main control board and three service boards. Host computer software runs on the main control board, allowing real-time monitoring of the status of the three timing signal sources and setting the clock source selection mode (manual or automatic) for the timing boards.

[0022] The host computer software running on the main control board is as follows: Figure 2 As shown, the host computer software includes three functional areas: a clock source status indicator area, a manual clock source selection area, and an automatic clock source selection area. Users can view the status of the three clock sources in real time through the host computer software. When the clock source signal is stable, the status indicator light will be constantly on; when the clock source signal is unstable, the status indicator light will not be on. Users can manually select a clock source based on the status indicator light. Alternatively, they can use the automatic clock source selection mode, where the clock board will select the optimal clock source based on an automatic selection algorithm.

[0023] The control algorithm flow for the operation of the timing board is as follows: Figure 3 As shown. The steps are as follows:

[0024] S1. Initialize the registers;

[0025] S2. Create threads: Thread 1 is used to listen for control commands from the main control board; Thread 2 is used to monitor the status of the three clock sources.

[0026] S3. When thread 1 receives the instruction to enable automatic clock source selection from the main control board, the PS end of FMQL will run the automatic source selection algorithm to select the optimal clock source; when it receives the instruction to manually select the clock source, the PS end will select the corresponding clock source; if neither the automatic selection nor the manual selection of the clock source is enabled, the PS end will run the automatic source selection algorithm.

[0027] S4. After determining the clock source to be selected, the PS terminal controls the register of the PL terminal through the AXI bus, thereby controlling the PL terminal to switch the corresponding decoding algorithm.

[0028] S5. Then, the PL end encodes the time information obtained by the decoding algorithm into a PTP protocol message and sends it to the network;

[0029] S6 and Thread 2 will monitor the status of the three clock sources every second and report it to the main control board via the network; Thread 1 will also use the real-time status information of the clock sources when running the automatic source selection algorithm.

[0030] The automatic source selection algorithm first determines the validity of each clock source. A clock source is valid if it has no alarms or abnormalities; otherwise, it is invalid. Only valid clock sources participate in priority score calculation. Based on the calculated scores, clock sources are sorted from highest to lowest, and the highest priority source is selected as the timing reference source. When there are two or more highest scores, they are sorted according to the priority of PTP, TOD, and B-code. Different evaluation parameters need to be considered when calculating the priority score for different clock sources. For PTP signal sources, the parameters to be evaluated are path delay variance and Sync message loss rate; for B-code signal sources, the parameters to be evaluated are signal error rate and PPS interval standard deviation; and for TOD signal sources, the parameters to be evaluated are NEMA check error count and PPS interval standard deviation. The specific priority score calculation formula is shown below.

[0031] PTP Priority Score Calculation Formula:

[0032]

[0033] In the formula, S PTP The score representing the PTP signal source is a weighted sum of the path delay variance score and the Sync message loss rate score; η1 indicates whether the PTP signal source is valid, with 1 for valid and 0 for invalid; σ 2 This represents the path delay variance of the PTP signal source; Indicates the maximum allowable variance; L represents the Sync message loss rate; L max This represents the maximum allowable loss rate; W1 and W2 are the weights of the parameters, which are 0.7 and 0.3, respectively.

[0034] Formula for calculating B-code priority score:

[0035]

[0036] In the formula, S B The score for the B-code signal source is a weighted sum of the B-code signal bit error rate score and the PPS interval standard deviation score; η2 indicates whether the B-code signal source is valid, with 1 for valid and 0 for invalid; BER represents the bit error rate of the B-code signal source; BER max Indicates the maximum allowable bit error rate; μ represents the standard deviation of the PPS interval; μ max This represents the maximum permissible standard deviation of the PPS interval; W3 and W4 are the weights of the parameters, which are 0.6 and 0.4, respectively.

[0037] TOD Priority Score Calculation Formula:

[0038]

[0039] In the formula, S TOD The score for the TOD signal source is a weighted sum of the NEMA error count score and the PPS interval standard deviation score; η3 indicates whether the TOD signal source is valid, with 1 for valid and 0 for invalid; N represents the number of NEMA errors of the TOD signal source; N max Indicates the maximum allowed number of verification errors; δ represents the standard deviation of the PPS interval; δ max This represents the maximum permissible standard deviation of the PPS interval; W5 and W6 are the weights of the parameters, which are 0.6 and 0.4, respectively.

[0040] This invention proposes a method for implementing a high-precision time synchronization system with multiple configurable clock sources based on FMQL. The system provides a multi-clock-source time synchronization system, including a system architecture centered on FMQL, an algorithm for switching the optimal clock source, and software. This invention designs priority scoring and sorting methods for PTP, TOD, and B codes, achieving nanosecond-level time synchronization accuracy and enabling flexible switching of time sources in various complex environments, significantly improving the overall performance and reliability of the system. It can be widely applied in aerospace, autonomous driving, precision manufacturing, smart grids, and other fields with stringent requirements for time synchronization accuracy and reliability.

[0041] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for implementing a high-precision time synchronization system with multiple configurable clock sources based on FMQL, characterized in that, The system includes: a timing board, a switching board, and a motherboard; The timing board, with the FMQL chip as its core, receives and decodes timing signals in real time. The timing signals include PTP, B code, and TOD. The PL end of FMQL runs the decoding time algorithm and then encodes the decoded time information into a PTP message and sends it to the network. The PS end of FMQL runs the control logic and controls the mode selection of the PL end according to the instructions sent by the main control board. The switching board is used to establish a network path between the timing board and each motherboard, transmit the PTP messages sent by the timing board to each motherboard for timing synchronization, and transmit the control messages sent by the main control board to the timing board. The motherboard consists of one main control board and three service boards. The host computer software runs on the main control board and can view the status of the three timing signal sources in real time and set the mode for the timing board to select the clock source.

2. The method for implementing a high-precision time synchronization system based on FMQL with multiple configurable clock sources as described in claim 1, characterized in that, The host computer software includes three functional areas: a clock source status indicator area, a manual clock source selection area, and an automatic clock source selection area. Users can view the status of the three clock sources in real time through the host computer software. When the clock source signal is stable, the status indicator light will be constantly on; when the clock source signal is unstable, the status indicator light will not be on. Users can manually select the clock source based on the status indicator light, or use the automatic clock source selection mode, in which the clock board will select the optimal clock source according to the automatic source selection algorithm.

3. The method for implementing a high-precision time synchronization system based on FMQL with multiple configurable clock sources as described in claim 1 or 2, characterized in that, The control algorithm flow for the operation of the timing board includes: S1. Initialize the registers; S2. Create threads: Thread 1 is used to listen for control commands from the main control board; Thread 2 is used to monitor the status of the three clock sources. S3. When thread 1 receives the instruction to enable automatic clock source selection from the main control board, the PS end of FMQL will run the automatic source selection algorithm to select the optimal clock source; when it receives the instruction to manually select the clock source, the PS end will select the corresponding clock source; if neither the automatic selection nor the manual selection of the clock source is enabled, the PS end will run the automatic source selection algorithm. S4. After determining the clock source to be selected, the PS terminal controls the register of the PL terminal through the AXI bus, thereby controlling the PL terminal to switch the corresponding decoding algorithm. S5. Then, the PL end encodes the time information obtained by the decoding algorithm into a PTP protocol message and sends it to the network; S6 and Thread 2 will monitor the status of the three clock sources every second and report it to the main control board via the network; Thread 1 will also use the real-time status information of the clock sources when running the automatic source selection algorithm.

4. The method for implementing a high-precision time synchronization system based on FMQL with multiple configurable clock sources as described in claim 3, characterized in that, In the automatic source selection algorithm, the validity of each clock source is first determined. If a clock source has no alarms or abnormalities, it is valid; otherwise, it is invalid. Only valid clock sources participate in the priority score calculation. Based on the calculated scores, the clock sources are sorted from high to low, and then the highest priority is selected as the timing reference source. When there are two or more highest scores, they are sorted according to the priority of PTP, TOD, and B code.

5. The method for implementing a high-precision time synchronization system based on FMQL with multiple configurable clock sources as described in claim 4, characterized in that, The parameters that need to be evaluated for the PTP signal source are path delay variance and Sync message loss rate. The PTP priority score is calculated using the following formula: In the formula, S PTP The score representing the PTP signal source is a weighted sum of the path delay variance score and the Sync message loss rate score; η1 indicates whether the PTP signal source is valid, with 1 for valid and 0 for invalid; σ 2 This represents the path delay variance of the PTP signal source; Indicates the maximum allowable variance; L represents the Sync message loss rate; L max This represents the maximum allowable loss rate; W1 and W2 are the weights of the parameters.

6. The method for implementing a high-precision time synchronization system based on FMQL with multiple configurable clock sources as described in claim 5, characterized in that, W1 and W2 are 0.7 and 0.3, respectively.

7. The method for implementing a high-precision time synchronization system based on FMQL with multiple configurable clock sources as described in claim 4, characterized in that, The parameters that need to be evaluated for a B-code signal source are the signal bit error rate and the standard deviation of the PPS interval. The formula for calculating the B-code priority score is: In the formula, S B The score representing the B-code signal source is a weighted sum of the B-code signal bit error rate score and the PPS interval standard deviation score. η2 indicates whether the B-code signal source is valid, with 1 for valid and 0 for invalid; BER indicates the bit error rate of the B-code signal source. BER max Indicates the maximum allowable bit error rate; μ represents the standard deviation of the PPS interval; μ max W3 represents the maximum permissible standard deviation of the PPS interval; W4 and W3 are the weights of the parameters.

8. The method for implementing a high-precision time synchronization system based on FMQL with multiple configurable clock sources as described in claim 7, characterized in that, W3 and W4 are 0.6 and 0.4 respectively.

9. The method for implementing a high-precision time synchronization system based on FMQL with multiple configurable clock sources as described in claim 4, characterized in that, The parameters that need to be evaluated for a TOD signal source are the number of NEMA check errors and the standard deviation of the PPS interval. The formula for calculating the TOD priority score is: In the formula, S TOD The score representing the TOD signal source is a weighted sum of the NEMA check error count score and the PPS interval standard deviation score. η3 indicates whether the TOD signal source is valid, with 1 when valid and 0 when invalid; N indicates the number of NEMA check errors of the TOD signal source; N max Indicates the maximum number of allowed checksum errors; δ represents the standard deviation of the PPS interval; δ max This represents the maximum permissible standard deviation of the PPS interval; W5 and W6 are the weights of the parameters, which are 0.6 and 0.4, respectively.

10. The method for implementing a high-precision time synchronization system based on FMQL with multiple configurable clock sources as described in claim 9, characterized in that, W5 and W6 are 0.6 and 0.4 respectively.

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