A communication conflict detection control method, device, apparatus and storage medium

Abstract

The application discloses a communication conflict detection control method, device and equipment and a storage medium. The application controls a bus slave module to send a request signal containing a unique feature identifier to a bus; controls a bus master module to listen to the bus in real time; controls the bus master module to identify bus slave modules participating in a conflict; controls the bus master module to allocate different sending time slots to the identified conflict bus slave modules; controls the bus master module to broadcast a control frame containing a conflict slave module list and corresponding sending time slots; controls each conflict slave module to perform local clock synchronization according to the allocated sending time slots after receiving the control frame; controls each conflict slave module to send data to the bus in the synchronized sending time slot; and controls the bus master module to enter a next round of listening period after each conflict slave module completes data sending. The application can realize accurate positioning and identification of bus communication conflicts, optimize communication resource allocation, and improve communication efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of bus module, and particularly relates to a communication conflict detection control method, device, equipment and storage medium. BACKGROUND

[0002] In modern communication systems, especially in industrial control, intelligent transportation, Internet of Things devices and other application scenarios, bus communication technology is widely used due to its simple structure, low cost, easy expansion and other advantages. In a typical bus communication architecture, multiple slave modules communicate with a master module through a shared physical bus. Since the bus is a shared medium, when multiple slave modules simultaneously attempt to send data, data collision, i.e., bus conflict, is likely to occur, resulting in data transmission failure, communication efficiency decline, and even system malfunction.

[0003] To solve the above problems, carrier sense multiple access / collision detection or its variants are commonly used in the prior art. The basic principle of this method is that a node listens to the bus before sending to determine whether the bus is idle. If it is idle, it sends; if it is busy, it waits for a random time and retries. Although this method performs well under light load, in scenarios with increasing number of nodes and increasing communication load, the conflict probability increases dramatically, resulting in increased number of retries and significant decrease in network throughput.

[0004] In addition, the existing conflict resolution mechanism has limited ability to identify conflict sources. Most solutions can only detect the occurrence of conflicts, but cannot accurately identify which nodes have caused the conflicts. This causes the master station to only broadcast instructions to all nodes that may have participated in the conflict to back off and retry, which not only increases unnecessary communication delay, but also wastes bandwidth resources. Therefore, how to reliably and efficiently solve the problem of bus communication conflict detection has become a problem that needs to be solved by technical personnel in the field. SUMMARY

[0005] Embodiments of the present application provide a communication conflict detection control method, device, equipment and storage medium to solve the problems in the prior art.

[0006] To solve the above technical problems, the embodiments of the present application provide a communication conflict detection control method, which comprises:

[0007] controlling a bus slave module to send a request signal containing a unique feature identifier to the bus; wherein the unique feature identifier is a combination of the physical address of the bus slave module and an adaptively generated pseudo-random code;

[0008] controlling the bus master module to listen to the bus in real time, and if a composite signal with multiple feature identifiers superimposed is detected within a preset detection window, determining that there is a bus conflict;

[0009] controlling the bus master module to identify the bus slave modules involved in the conflict by analyzing the plurality of feature identifiers in the composite signal;

[0010] controlling the bus master module to assign different transmission time slots to the identified bus slave modules involved in the conflict, the transmission time slots being determined according to the request sequence of each of the bus slave modules and a current load state of the bus;

[0011] controlling the bus master module to broadcast a control frame containing a list of the bus slave modules involved in the conflict and corresponding transmission time slots;

[0012] controlling each of the bus slave modules involved in the conflict to perform local clock synchronization according to the assigned transmission time slot after receiving the control frame;

[0013] controlling each of the bus slave modules involved in the conflict to transmit data to the bus in the synchronized transmission time slot;

[0014] controlling the bus master module to reset the bus listening state and enter a next round of listening period after each of the bus slave modules involved in the conflict completes data transmission.

[0015] Preferably, the controlling the bus master module to assign different transmission time slots to the identified bus slave modules involved in the conflict, the transmission time slots being determined according to the request sequence of each of the bus slave modules and a current load state of the bus comprises:

[0016] generating a preliminary time slot assignment sequence according to the request sequence of each of the bus slave modules involved in the conflict;

[0017] obtaining the current load state of the bus, the current load state including currently active bus slave modules and corresponding data transmission volume;

[0018] adaptively adjusting the time slot assignment sequence according to the current load state;

[0019] determining final transmission time slots of each of the bus slave modules involved in the conflict according to the adjustment result, and generating a time slot assignment table.

[0020] Preferably, the controlling the bus slave module to transmit a request signal containing a unique feature identifier to the bus comprises:

[0021] detecting whether the bus is in an idle state before the bus slave module transmits the request signal;

[0022] generating the unique feature identifier if the bus is idle;

[0023] encapsulating the unique feature identifier into the request signal and transmitting the request signal through the bus;

[0024] If the bus is busy, a random backoff algorithm is executed, and the sending is reattempted after a preset time delay.

[0025] Preferably, the control bus master module monitors the bus in real time, and if a composite signal with multiple characteristic identifiers superimposed is detected within a preset detection window, it is determined that there is a bus conflict, including:

[0026] The control bus master module continuously monitors the bus signal, and collects the signal waveform in real time within the preset detection window;

[0027] The received signal waveform is subjected to frequency spectrum analysis;

[0028] If the frequency spectrum analysis result shows that there are multiple characteristic identifiers superimposed, it is determined that there is a bus conflict;

[0029] The timestamp of the conflict occurrence and the composite signal data are recorded for subsequent analysis.

[0030] Preferably, the control bus master module identifies the bus slave modules participating in the conflict by analyzing the multiple characteristic identifiers in the composite signal, including:

[0031] The composite signal is subjected to digital filtering processing to extract the frequency spectrum components of the multiple characteristic identifiers;

[0032] The original data of the multiple characteristic identifiers are restored through a signal demodulation algorithm;

[0033] The restored multiple characteristic identifiers are compared with a preset identifier library to identify the bus slave modules participating in the conflict;

[0034] A list of the conflict slave modules is generated, and the conflict time information of each bus slave module in conflict is recorded.

[0035] Preferably, the control of each conflict slave module to perform local clock synchronization according to the allocated sending time slot after receiving the control frame includes:

[0036] The control of each conflict slave module to analyze the control frame and extract the time reference information of the sending time slot;

[0037] The local clock is compared with the time reference information in the control frame to calculate the clock deviation;

[0038] The local clock is adjusted according to the clock deviation to achieve clock synchronization with the bus master module;

[0039] After synchronization is completed, a synchronization confirmation signal is sent to the bus master module.

[0040] Preferably, after the control of each of the conflict slave station modules to send data to the bus in the synchronized sending time slot, the method further comprises:

[0041] The bus master module is controlled to receive the data sent by each of the conflict slave station modules and to check the data integrity.

[0042] To solve the above technical problems, the embodiment of the present application provides a communication conflict detection control, and the device comprises:

[0043] The request sending module is configured to control the bus slave station module to send a request signal containing a unique feature identifier to the bus, wherein the unique feature identifier is a combination of the physical address of the bus slave station module and a pseudo-random code adaptively generated.

[0044] The listening module is configured to control the bus master module to listen to the bus in real time, and if a composite signal in which multiple feature identifiers are superimposed is detected in a preset detection window, it is determined that there is a bus conflict.

[0045] The analysis and identification module is configured to control the bus master module to identify the bus slave station modules participating in the conflict by analyzing the multiple feature identifiers in the composite signal.

[0046] The allocation module is configured to control the bus master module to allocate different sending time slots to the identified conflict bus slave station modules, and the sending time slots are determined according to the request order of each of the conflict bus slave station modules and the current load state of the bus.

[0047] The broadcast module is configured to control the bus master module to broadcast a control frame containing a list of conflict slave station modules and corresponding sending time slots.

[0048] The synchronization control module is configured to control each of the conflict slave station modules to perform local clock synchronization according to the allocated sending time slots after receiving the control frame.

[0049] The synchronized sending module is configured to control each of the conflict slave station modules to send data to the bus in the synchronized sending time slot.

[0050] The reset module is configured to control the bus master module to reset the bus listening state and enter the next listening period after each of the conflict slave station modules completes data sending.

[0051] To solve the above technical problems, the embodiment of the present application provides a spliced screen automatic splicing control device, which comprises at least one processor, at least one memory, and computer program instructions stored in the memory, and when the computer program instructions are executed by the processor, the method of the first aspect in the above embodiment is implemented.

[0052] To address the aforementioned technical problems, embodiments of the present invention provide a storage medium storing computer program instructions, which, when executed by a processor, implement the method of the first aspect described above.

[0053] In summary, the embodiments of the present invention provide a communication conflict detection and control method, apparatus, device, and storage medium. The present invention controls a bus slave module to send a request signal containing a unique identifier to the bus; wherein the unique identifier is a combination of the physical address of the bus slave module and an adaptively generated pseudo-random code. In this application, the physical address is inherent in the hardware, ensuring the uniqueness of each slave station at the system level. The pseudo-random code is adaptively generated, preventing malicious attacks and enhancing system security. The control bus master module monitors the bus in real time. If a composite signal with multiple superimposed feature identifiers is detected within a preset detection window, it is determined to be a bus conflict. Thus, this application avoids misjudging normal signals as conflicts through real-time monitoring and judgment based on signal characteristics, and also improves the real-time performance of conflict detection. The control bus master module identifies the bus slave modules involved in the conflict by parsing multiple feature identifiers in the composite signal. Therefore, this application can accurately identify the bus slave modules involved in the conflict, improving the efficiency and targeting of conflict resolution. The control bus master module allocates different transmission time slots to the identified conflicting bus slave modules. The transmission time slots are determined based on the request order of each conflicting bus slave module and the current load status of the bus. Through time slot allocation, it is ensured that conflicting nodes do not collide in subsequent communications. Simultaneously, by combining the request order and load status-based transmission slot algorithm, the allocation of bus bandwidth is no longer random, improving communication efficiency. The control bus master module broadcasts a control frame containing a list of conflicting slave modules and their corresponding transmission slots, thus conveying conflict resolution instructions to all relevant parties in one go, avoiding point-to-point communication delays. Upon receiving the control frame, each conflicting slave module synchronizes its local clock according to its allocated transmission slot, preventing clock drift. Each conflicting slave module then sends data to the bus within its synchronized transmission slot, improving the synchronization and accuracy of data transmission. Finally, after each conflicting slave module completes data transmission, the control bus master module resets the bus listening state and enters the next listening cycle. Therefore, this invention can achieve precise location and identification of bus communication conflicts, optimize communication resource allocation, and improve communication efficiency. Attached Figure Description

[0054] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0055] Figure 1is a flow chart of a communication conflict detection control method according to an embodiment of the present application.

[0056] Figure 2 is a flow chart of a process of assigning different transmission time slots to the identified conflict bus slave modules by the bus master module according to an embodiment of the present application.

[0057] Figure 3 is a flow chart of a process of transmitting a request signal containing a unique feature identifier by the bus slave module according to an embodiment of the present application.

[0058] Figure 4 is a flow chart of a process of real-time monitoring the bus by the bus master module according to an embodiment of the present application, and if a composite signal with multiple feature identifiers superimposed is detected within a preset detection window, determining that there is a bus conflict.

[0059] Figure 5 is a flow chart of a process of identifying the bus slave modules participating in the conflict by the bus master module by analyzing the multiple feature identifiers in the composite signal according to an embodiment of the present application.

[0060] Figure 6 is a flow chart of a process of synchronizing the local clock of each conflict slave module according to an embodiment of the present application.

[0061] Figure 7 is a structural diagram of a communication conflict detection control device according to an embodiment of the present application.

[0062] Figure 8 is a structural diagram of a communication conflict detection control device according to an embodiment of the present application. DETAILED DESCRIPTION

[0063] The features and exemplary embodiments of various aspects of the present application will be described in detail below with reference to the drawings. To make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are configured only to explain the present application and are not configured to limit the present application. The present application can be implemented without some of the specific details by those skilled in the art. The following description of the embodiments is merely to provide a better understanding of the present application by showing examples of the present application.

[0064] It is to be noted that the relative terms such as first and second and the like in this context are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between such entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article or apparatus. Without further limitation, an element defined by an "includes" statement does not exclude the existence of additional identical elements in the process, method, article or apparatus including the element.

[0065] Please refer to Figure 1 , Figure 1 A communication conflict detection control method is provided in the present application, and the method comprises the following steps:

[0066] S1, a bus slave module sends a request signal containing a unique feature identifier to the bus; wherein the unique feature identifier is a combination of the physical address of the bus slave module and a pseudo-random code generated adaptively;

[0067] Specifically, in the embodiment, the bus module comprises a bus master module and a plurality of bus slave modules. The bus master module acts as a control center in the network, responsible for managing network communication and operation, and exchanges data with each bus slave module. The bus slave module acts as an execution unit, responds to the instructions of the bus master module and completes the specified tasks. The bus master module and the bus slave modules form a one-to-many control relationship.

[0068] Specifically, in the embodiment, the bus master module, each bus slave module and the host computer terminal communicate with each other through communication technologies such as CAN protocol, Modbus protocol, CANopen protocol, Profinet protocol and EtherCAT protocol, and the communication mode between the bus master module, each bus slave module and the host computer terminal is not specifically limited herein.

[0069] Specifically, in the embodiment, the physical address of the bus slave module is a MAC address, and the MAC address is fixed in the non-volatile memory of the bus slave module. At the same time, in order to avoid deadlock caused by the use of the same identifier by multiple bus slave modules in multiple conflicts, each bus slave module generates a pseudo-random code according to the internal state before each transmission of the request.

[0070] Specifically, in this embodiment, the bus slave module encapsulates a unique identifier consisting of a MAC address and a pseudo-random code into a request frame, and sends the request frame to the shared bus through the bus transceiver. For example, the physical address 0x01 and the pseudo-random code 0xA5 combine to form the unique identifier 0x01A5, which is not specifically limited here.

[0071] S2. The control bus master module monitors the bus in real time. If a composite signal with multiple superimposed feature identifiers is detected within the preset detection window, it is determined to be a bus conflict.

[0072] Specifically, in this embodiment, the bus interface unit of the bus master module always remains in a receiving state, sampling the level signals on the bus in real time. The bus master module decodes the received analog signals into a digital signal stream and buffers them in a first-in-first-out circular buffer. The bus master module internally defines a detection window, the length of which is greater than the transmission time of a standard request signal. When the bus master module detects a signal that does not conform to the expected model of a single signal and can distinguish that it contains multiple feature identifiers, it determines that a bus collision has occurred.

[0073] S3. The control bus master module identifies the bus slave modules involved in the conflict by analyzing multiple feature identifiers in the composite signal.

[0074] Specifically, in this embodiment, since each feature identifier has a known format, the bus master module matches the components in the composite signal using the known pattern, thereby resolving the bus slave modules involved in the conflict.

[0075] Specifically, for example, the bus master module analyzes the received composite signal and successfully separates and identifies three characteristic identifiers: 0x013C, 0x028D, and 0x03E7. Therefore, the bus master module confirms that a conflict has occurred between bus slave modules 01, 02, and 03.

[0076] S4. The control bus master module allocates different transmission time slots to the identified conflicting bus slave modules. The transmission time slots are determined based on the request order of each conflicting bus slave module and the current load status of the bus.

[0077] Specifically, in this embodiment, the bus master module obtains the current bus load status from the bus load monitoring module. The load status includes the currently allocated time slot occupancy rate, data traffic, etc., which are not specifically limited here.

[0078] Specifically, in this embodiment, the bus master module allocates time slots according to a preset scheduling strategy and calculates time slot parameters for each bus slave module in the conflict list. The time slot parameters include time slot offset and time slot duration. The bus master module associates the physical address of each conflicting slave with the corresponding time slot parameters to form a time slot allocation table.

[0079] In this application, once the conflict bus slave module receives the time slot allocation, it can accurately know when the slave data will be sent, effectively improving the real-time performance of data transmission.

[0080] Therefore, this application resolves the conflict issue and ensures a high data transmission success rate by allocating transmissions to each conflicting party. Furthermore, the bus master module can intelligently schedule transmissions based on global load conditions, avoiding wasted time slots and fully utilizing bus bandwidth, resulting in overall communication efficiency higher than random contention mechanisms.

[0081] S5. The control bus master module broadcasts a control frame containing a list of conflicting slave modules and their corresponding transmission time slots.

[0082] Specifically, in this embodiment, the bus master module encapsulates the generated time slot allocation table as payload into a control frame. The frame type field of the control frame is set with a specific identifier to distinguish it from ordinary data frames. The bus master module listens to the bus to confirm when it is idle and broadcasts the control frame to the entire bus. It can be understood that payload refers to the effective data, that is, the core data part that is actually transmitted and meaningful to the upper-layer application in the communication data frame.

[0083] S6. After receiving the control frame, each conflicting slave module performs local clock synchronization according to the allocated transmission time slot.

[0084] Specifically, in this embodiment, each bus slave module is listening to the bus. When each bus slave module receives a broadcast control frame, it checks the frame type of the control frame. If it is a scheduling control frame, each bus slave module performs a CRC check.

[0085] Specifically, after successful verification, the bus slave module parses the conflicting slave list and time slot allocation table within the frame, and compares its own physical address with the addresses in the conflicting slave list one by one. If the bus slave module finds its own physical address in the conflicting slave list, it performs local clock synchronization. If it is not in the list, the bus slave module ignores the control frame and continues normal operation.

[0086] Specifically, the scheduled bus slave modules need to be clock-synchronized to ensure that they are in time alignment with the bus master module and other bus slave modules.

[0087] S7. Control each conflicting slave module to send data to the bus within the transmission time slot after synchronization;

[0088] Specifically, in this embodiment, after completing clock synchronization and setting the internal timer, the bus slave module enters a waiting state. When the internal timer reaches the preset transmission time, the internal timer interrupt is triggered, the interrupt service routine is called, the bus slave module immediately stops listening, switches to transmission mode, and begins to send the data frames to be transmitted onto the bus with the highest priority.

[0089] S8. After each conflicting slave module completes data transmission, the control bus master module resets the bus listening state and enters the next listening cycle.

[0090] Specifically, in this embodiment, the bus slave module must complete the transmission of data frames within the time slot allocated to it. After the data transmission is complete, the bus slave module immediately releases bus control, switches back to listening mode, and waits for the next communication opportunity. Therefore, the data transmission process in this application is driven by an internal timer interrupt, ensuring the timeliness and accuracy of the transmission action and effectively avoiding bus conflicts.

[0091] In summary, this application provides a communication conflict detection and control method. In this scheme, the bus slave module sends a request signal containing a unique identifier to the bus. The unique identifier is a combination of the physical address of the bus slave module and an adaptively generated pseudo-random code. In this application, the physical address is inherent in the hardware, ensuring the uniqueness of each slave station at the system level. The pseudo-random code is adaptively generated, preventing malicious attacks and enhancing system security. The control bus master module monitors the bus in real time. If a composite signal with multiple superimposed feature identifiers is detected within a preset detection window, it is determined to be a bus conflict. Thus, this application avoids misjudging normal signals as conflicts through real-time monitoring and judgment based on signal characteristics, and also improves the real-time performance of conflict detection. The control bus master module identifies the bus slave modules involved in the conflict by parsing multiple feature identifiers in the composite signal. Therefore, this application can accurately identify the bus slave modules involved in the conflict, improving the efficiency and targeting of conflict resolution. The control bus master module allocates different transmission time slots to the identified conflicting bus slave modules. The transmission time slots are determined based on the request order of each conflicting bus slave module and the current load status of the bus. Through time slot allocation, it is ensured that conflicting nodes do not collide in subsequent communications. Simultaneously, by combining the request order and load status-based transmission slot algorithm, the allocation of bus bandwidth is no longer random, improving communication efficiency. The control bus master module broadcasts a control frame containing a list of conflicting slave modules and their corresponding transmission slots, thus conveying conflict resolution instructions to all relevant parties in one go, avoiding point-to-point communication delays. Upon receiving the control frame, each conflicting slave module synchronizes its local clock according to its allocated transmission slot, preventing clock drift. Each conflicting slave module then sends data to the bus within its synchronized transmission slot, improving the synchronization and accuracy of data transmission. Finally, after each conflicting slave module completes data transmission, the control bus master module resets the bus listening state and enters the next listening cycle. Therefore, this invention can achieve precise location and identification of bus communication conflicts, optimize communication resource allocation, and improve communication efficiency.

[0092] Based on the above embodiments:

[0093] Please see Figure 2 , Figure 2 This application provides a schematic diagram illustrating the process by which a control bus master module allocates different transmission time slots to identified conflicting bus slave modules, with the transmission time slots determined based on the request order of each conflicting bus slave module and the current load status of the bus.

[0094] In a preferred embodiment, the control bus master module allocates different transmission time slots to the identified conflicting bus slave modules. The transmission time slots are determined based on the request order of each conflicting bus slave module and the current bus load status, including:

[0095] S41. Generate a preliminary time slot allocation sequence based on the request order of each conflicting bus slave module;

[0096] Specifically, in this embodiment, when a collision is detected and the composite signal is parsed, the bus master module timestamps each conflicting bus slave module. The timestamp indicates the precise moment when the bus master module detected the collision event.

[0097] Specifically, in this embodiment, there are slight differences in the arrival times of the start edges of signals from different bus slave modules to the receiver of the bus master module, typically on the order of nanoseconds or microseconds. The bus master module captures these differences using a high-precision timer and sorts the identified bus slave modules according to their arrival order. For example, the sorting order of the conflicting bus slave modules is: Slave 02 -> Slave 01 -> Slave 03, but this is not specifically limited here.

[0098] Specifically, in this embodiment, the bus master module continuously allocates time slots to each conflicting bus slave module according to the sorting order, forming an ordered list, which is the initial time slot allocation sequence.

[0099] S42. Obtain the current bus load status, which includes the currently active slave station and its corresponding data transmission volume;

[0100] Specifically, in this embodiment, the bus master module dynamically maintains a network status table. This table records the status information of all known bus slave modules on the bus. The bus master module records the frequency, packet size, and timestamp of successful data transmission by each bus slave module over several past communication cycles.

[0101] Specifically, in this embodiment, the bus master module periodically sends status query frames to all bus slave modules, containing information such as the length of the data queue to be sent. The network interface chip of the bus master module counts the total traffic on the bus and the traffic categorized by source address.

[0102] Specifically, in this embodiment, the bus master module calculates key load indicators based on the collected information. These key load indicators include the current active slave list, data transmission volume of each slave, bus utilization, and congestion area identification, etc., which are not specifically limited here.

[0103] S43. Adaptively adjust the time slot allocation sequence based on the current load status;

[0104] Specifically, in this embodiment, the bus master module adjusts the time slot allocation sequence according to a preset optimization goal. The preset optimization goal is to achieve load balancing, that is, to evenly distribute communication tasks across the entire time axis, avoiding congestion during busy periods and idle periods.

[0105] Specifically, the bus master module takes the initial time slot allocation sequence and the current bus load status as input and runs an adjustment algorithm. In the adjustment algorithm, the bus master module examines consecutive time slots in the initial time slot allocation sequence. If a time slot falls within the current bus peak period, the bus master module attempts to find a consecutive, sufficiently long time slot block during an idle period and shifts the entire conflict sequence there. If a complete shift is not possible, it attempts to "insert" some nodes into idle time slot gaps. After the above adjustment algorithm, the initial time slot allocation sequence is modified, forming the adjusted time slot allocation sequence.

[0106] S44. Based on the adjustment results, determine the final transmission time slot of each conflicting bus slave module and generate a time slot allocation table.

[0107] Specifically, in this embodiment, the bus master module accurately calculates the time slot parameters for each bus slave module in the adjusted time slot allocation sequence. The bus master module creates a structured data table, namely the time slot allocation table, which lists the physical address of each conflicting bus slave module, as well as its corresponding time slot offset and duration.

[0108] Please see Figure 3 , Figure 3 This application provides a schematic diagram of a process for a control bus slave module to send a request signal containing a unique identifier to the bus.

[0109] In a preferred embodiment, the control bus slave module sending a request signal containing a unique identifier to the bus includes:

[0110] S11. Before the bus slave module sends a request signal, check whether the bus is in an idle state;

[0111] Specifically, in this embodiment, before the bus slave module sends a request signal, the microcontroller command transceiver of the bus slave module enters a high-impedance listening mode. To avoid misinterpreting the brief interval between two frames as complete idleness, the bus slave module continuously listens for a minimum time unit, such as a few bits. Only if the bus remains idle within this duration is the bus determined to be in an idle state.

[0112] S12. If the bus is idle, generate a unique feature identifier;

[0113] Specifically, in this embodiment, if the bus is idle, the bus slave module reads the device's fixed MAC address from the non-volatile memory and calls the internal pseudo-random number generator to generate a pseudo-random code for this communication.

[0114] S13. Encapsulate the unique identifier into a request signal and send it via the bus;

[0115] Specifically, in this embodiment, the system combines the physical address and the newly generated pseudo-random code into a unique identifier, and encapsulates the unique identifier into a request frame. The controller drives the bit stream of the request frame bit by bit onto the bus to complete the data transmission.

[0116] S14. If the bus is busy, execute the random backoff algorithm and retry sending after a preset delay.

[0117] Specifically, in this embodiment, if the bus is busy, the controller of the bus slave module calls the internal random backoff algorithm, starts the internal timer, enters low-power mode, or processes other tasks. When the internal timer expires, the bus slave module's backoff counter restarts the listen-and-determine process.

[0118] Specifically, the random backoff algorithm in this application is set as a binary exponential backoff algorithm, without further specific limitations.

[0119] Please see Figure 4 , Figure 4 This application provides a flowchart illustrating a control bus master module that monitors the bus in real time. If a composite signal with multiple superimposed feature identifiers is detected within a preset detection window, it is determined to be a bus conflict.

[0120] In a preferred embodiment, the control bus master module monitors the bus in real time. If a composite signal with multiple superimposed feature identifiers is detected within a preset detection window, it is determined to be a bus conflict, including:

[0121] S21. Control the bus master module to continuously monitor the bus signal and collect the signal waveform in real time within the preset detection window;

[0122] Specifically, in this embodiment, the physical layer interface of the bus master module continuously samples the analog signals on the bus at a sampling rate higher than the bus signal baud rate, and the sampled data is stored in a circular buffer.

[0123] S22. Perform spectrum analysis on the received signal waveform;

[0124] Specifically, in this embodiment, to reduce the spectral leakage effect caused by signal truncation during spectral analysis and to make the analysis results more accurate, the system applies a window function to the extracted data blocks before performing spectral analysis. Furthermore, the bus master module performs a Fast Fourier Transform on the acquired and windowed signal data blocks for spectral analysis.

[0125] S23. If the spectrum analysis results show that multiple feature identifiers are superimposed, it is determined to be a bus conflict;

[0126] Specifically, in this embodiment, the bus master module analyzes the power spectral density map of the current window, extracts key features, and compares the extracted key features with a pre-stored reference spectrum template. If the main lobe width of the current spectrum is significantly larger than the main lobe width of the reference template, it indicates that multiple signals with offset center frequencies are superimposed. Alternatively, if a new, obvious spectral peak appears at a position where there is no spectral peak in the reference template, or if a companion peak appears next to an existing spectral peak, it is determined to be a bus conflict.

[0127] S24. Record the timestamp of the collision and the composite signal data for subsequent analysis.

[0128] Specifically, in this embodiment, if a bus conflict is determined, the bus master module immediately reads the current time from the high-precision clock and generates a conflict timestamp accurate to microseconds. It also saves the original data in the relevant detection window that triggered the conflict determination, including the original waveform sampling points and / or its spectrum analysis results, and associates them with the conflict timestamp to form a complete conflict event log.

[0129] Please see Figure 5 , Figure 5 The present application provides a flowchart illustrating how a control bus master module identifies bus slave modules involved in a conflict by analyzing multiple feature identifiers in a composite signal.

[0130] In a preferred embodiment, the control bus master module identifies the bus slave modules involved in the conflict by parsing multiple feature identifiers in the composite signal, including:

[0131] S31. Perform digital filtering on the composite signal to extract the spectral components of multiple feature identifiers;

[0132] Specifically, in this embodiment, the bus master module obtains the saved original sampled data of the composite signal from the recorded collision events. The bus master module pre-designs a digital filter based on the bus protocol and the modulation scheme of the unique feature identifier. The bus master module inputs the digital sampled data stream of the composite signal into the digital filter, so that the target spectral component, i.e., the part carrying the feature identifier information, is preserved and enhanced. The digital filter can be either a bandpass filter or a matched filter, without specific limitations.

[0133] S32. Restore the original data of multiple feature identifiers using a signal demodulation algorithm;

[0134] Specifically, in this embodiment, the bus master module selects the appropriate demodulation algorithm based on the modulation scheme used by the bus and performs demodulation on the filtered signal. The output of the demodulation algorithm is one or more candidate digital bitstreams, which are the restored original data containing multiple feature identifiers.

[0135] S33. Compare the restored multiple feature identifiers with the preset identifier library to identify the bus slave module involved in the conflict;

[0136] Specifically, in this embodiment, the preset identifier library contains the physical addresses of all legitimate bus slave modules in the network, as well as the algorithm rules for generating pseudo-random codes. The bus master module parses each restored bitstream, extracts the physical address and pseudo-random code bit by bit or byte by byte from the bitstream, and uses the extracted "physical address" part as a keyword to query the preset identifier library.

[0137] Specifically, in this embodiment, if the query is successful, that is, a matching physical address is found in the preset identifier library, the bus master module successfully identifies a slave module involved in the conflict.

[0138] S34. Generate a list of conflicting slave modules and record the conflict time information of each conflicting bus slave module.

[0139] Specifically, the bus master module creates a data structure to store detailed information about the current conflict event. For each identified conflicting slave, the bus master module creates an entry in the list. Once all identified slave information has been filled into the list, the conflicting slave module list is complete. The bus master module then uses this conflicting slave module list as input for time slot allocation and passes it to the scheduling module. In this embodiment, the data structure can be an array or a linked list; no specific limitation is made here.

[0140] Please see Figure 6 , Figure 6 This application provides a schematic diagram of a process for controlling each conflicting slave module to perform local clock synchronization according to the allocated transmission time slot after receiving a control frame.

[0141] In a preferred embodiment, controlling each conflicting slave module to perform local clock synchronization according to the allocated transmission time slot after receiving the control frame includes:

[0142] S61. Control each conflicting slave module to parse the control frame and extract the time reference information of the transmission time slot;

[0143] Specifically, in this embodiment, after receiving the control frame broadcast by the bus master module, the bus slave module performs a CRC check to ensure the data is error-free. The bus slave module extracts the time base information for synchronization from the payload of the control frame according to a predefined protocol format and records the local received timestamp.

[0144] S62. Compare the local clock with the time reference information in the control frame and calculate the clock deviation;

[0145] Specifically, in this embodiment, the bus slave module estimates the one-way propagation delay of the signal from the bus master module to itself. Based on the bus master module's timestamp and the estimated delay, the bus slave module calculates the theoretical reception timestamp for receiving control frames if its own clock is perfectly synchronized with the bus master module. The bus slave module compares the theoretical reception timestamp with its local reception timestamp to determine the clock offset.

[0146] S63. Adjust the local clock according to the clock deviation to achieve clock synchronization with the bus master module;

[0147] Specifically, in this embodiment, the bus slave module adjusts its local clock based on the calculated clock offset value. After synchronization adjustment, the bus slave module recalculates the absolute moment at which it should send data and combines the time slot offset specified in the control frame with the synchronized local time base to obtain a precise future transmission time.

[0148] S64. After synchronization is complete, send a synchronization confirmation signal to the bus master module.

[0149] Specifically, in this embodiment, after completing clock adjustment, the bus slave module generates a synchronization acknowledgment frame and sends it to the bus master module. The bus master module listens for and receives acknowledgment signals from all conflicting slaves.

[0150] In a preferred embodiment, after controlling each conflicting slave module to send data to the bus within the synchronized transmission time slot, the method further includes:

[0151] The control bus master module receives data sent by each conflicting slave module and verifies the data integrity.

[0152] Please see Figure 7 This invention provides a communication conflict detection and control device, the device comprising:

[0153] The request sending module 1 is used to control the bus slave module to send a request signal containing a unique identifier to the bus; wherein, the unique identifier is a combination of the physical address of the bus slave module and an adaptively generated pseudo-random code;

[0154] The monitoring module 2 is used to control the bus master module to monitor the bus in real time. If a composite signal with multiple superimposed feature identifiers is detected within the preset detection window, it is determined to be a bus conflict.

[0155] The parsing and identification module 3 is used to control the bus master module to identify the bus slave module involved in the conflict by parsing multiple feature identifiers in the composite signal;

[0156] Allocation module 4 controls the bus master module to allocate different transmission time slots to the identified conflicting bus slave modules. The transmission time slots are determined based on the request order of each conflicting bus slave module and the current load status of the bus.

[0157] Broadcast module 5 is used to control the bus master module to broadcast a control frame containing a list of conflicting slave modules and their corresponding transmission time slots;

[0158] Synchronization control module 6 is used to control each conflicting slave module to synchronize its local clock according to the allocated transmission time slot after receiving the control frame;

[0159] Synchronization transmission module 7 is used to control each conflicting slave module to send data to the bus within the transmission time slot after synchronization;

[0160] Reset module 8 is used to control the bus master module to reset the bus listening state after each conflicting slave module has completed data transmission and enter the next listening cycle.

[0161] In addition, combined Figure 1 The communication conflict detection and control method described in this embodiment of the invention can be implemented by a network communication conflict detection and control device. Figure 8 A schematic diagram of the hardware structure of the communication conflict detection and control device provided in an embodiment of the present invention is shown.

[0162] The communication conflict detection and control device may include a processor 401 and a memory 402 storing computer program instructions.

[0163] Specifically, the processor 401 may include a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of the present invention.

[0164] Memory 402 may include mass storage for data or instructions. For example, and not limitingly, memory 402 may include a hard disk drive (HDD), a floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or a Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 402 may include removable or non-removable (or fixed) media. Where appropriate, memory 402 may be internal or external to a data processing device. In a particular embodiment, memory 402 is a non-volatile solid-state memory. In a particular embodiment, memory 402 includes read-only memory (ROM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), an electrically rewritable ROM (EAROM), or flash memory, or a combination of two or more of these.

[0165] The processor 401 reads and executes computer program instructions stored in the memory 402 to implement any of the communication conflict detection and control methods in the above embodiments.

[0166] In one example, the communication conflict detection and control device may further include a communication interface 403 and a bus 410. Wherein, as Figure 8 As shown, the processor 401, memory 402, and communication interface 403 are connected through bus 410 and complete communication with each other.

[0167] The communication interface 403 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of the present invention.

[0168] Bus 410 includes hardware, software, or both, that couples components of a communication conflict detection control device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 410 may include one or more buses. While specific buses are described and illustrated in embodiments of the invention, the invention contemplates any suitable bus or interconnect.

[0169] Furthermore, in conjunction with the communication conflict detection and control method in the above embodiments, this invention can be implemented using a computer-readable storage medium. This computer-readable storage medium stores computer program instructions; when executed by a processor, these computer program instructions implement any of the communication conflict detection and control methods in the above embodiments.

[0170] It should also be noted that the exemplary embodiments mentioned in this invention describe methods or systems based on a series of steps or apparatus. However, this invention is not limited to the order of the steps described above; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0171] The above are merely specific embodiments of the present invention. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the protection scope of the present invention.

Claims

1. A communication collision detection and control method, characterized in that, The communication collision detection and control method includes: The control bus slave module sends a request signal containing a unique identifier to the bus; wherein the unique identifier is a combination of the physical address of the bus slave module and an adaptively generated pseudo-random code; The control bus master module monitors the bus in real time. If a composite signal with multiple superimposed feature identifiers is detected within the preset detection window, it is determined to be a bus conflict. The bus master module controls the bus slave module to identify the bus slave module involved in the conflict by parsing multiple feature identifiers in the composite signal; The bus master module is controlled to allocate different transmission time slots to the identified conflicting bus slave modules. The transmission time slots are determined based on the request order of each conflicting bus slave module and the current load status of the bus. The bus master module is controlled to broadcast a control frame containing a list of conflicting slave modules and their corresponding transmission time slots. After receiving the control frame, each conflicting slave module performs local clock synchronization according to the allocated transmission time slot; Control each conflicting slave module to send data to the bus within the synchronized transmission time slot; After each conflicting slave module completes data transmission, the bus master module resets the bus listening state and enters the next listening cycle.

2. The communication conflict detection and control method according to claim 1, characterized in that, The bus master module allocates different transmission time slots to the identified conflicting bus slave modules. The transmission time slots are determined based on the request order of each conflicting bus slave module and the current bus load status, including: A preliminary time slot allocation sequence is generated based on the request order of each conflicting bus slave module; Obtain the current bus load status, which includes the currently active slave station and its corresponding data transmission volume; The time slot allocation sequence is adaptively adjusted based on the current load status; Based on the adjustment results, the final transmission time slots of each conflicting bus slave module are determined, and a time slot allocation table is generated.

3. The communication conflict detection and control method according to claim 1, characterized in that, The control bus slave module sends a request signal containing a unique identifier to the bus, including: Before the bus slave module sends the request signal, it checks whether the bus is in an idle state; If the bus is idle, the unique feature identifier is generated; The unique identifier is encapsulated into the request signal and sent via the bus; If the bus is busy, a random backoff algorithm is executed, and the transmission is retried after a preset delay.

4. The communication collision detection and control method according to claim 1, characterized in that, The control bus master module monitors the bus in real time. If it detects a composite signal with multiple superimposed feature identifiers within a preset detection window, it determines it to be a bus conflict, including: The bus master module is controlled to continuously monitor the bus signal and acquire the signal waveform in real time within the preset detection window; Perform spectrum analysis on the received signal waveform; If the spectrum analysis results show that multiple of the aforementioned feature identifiers are superimposed, it is determined to be a bus conflict; Record the timestamp of the collision and the composite signal data for subsequent analysis.

5. The communication conflict detection and control method according to claim 1, characterized in that, The bus master module identifies the bus slave modules involved in the conflict by parsing multiple feature identifiers in the composite signal, including: The composite signal is digitally filtered to extract the spectral components of multiple feature identifiers; The original data of the multiple feature identifiers are restored using a signal demodulation algorithm; The restored feature identifiers are compared with a preset identifier library to identify the bus slave modules involved in the conflict. Generate the list of conflicting slave modules and record the conflict time information of each conflicting bus slave module.

6. The communication conflict detection and control method according to claim 1, characterized in that, The process of controlling each conflicting slave module to perform local clock synchronization according to the allocated transmission time slot after receiving the control frame includes: The control module of each conflicting slave station parses the control frame and extracts the time reference information of the transmission time slot; The local clock is compared with the time reference information in the control frame to calculate the clock deviation; The local clock is adjusted according to the clock deviation to achieve clock synchronization with the bus master module; After synchronization is complete, a synchronization confirmation signal is sent to the bus master module.

7. The communication collision detection and control method according to claim 1, characterized in that... After controlling each of the conflicting slave modules to send data to the bus within the synchronized transmission time slot, the method further includes: The bus master module receives data sent by each conflicting slave module and verifies the data integrity.

8. A communication conflict detection and control device, characterized in that, The device includes: A request sending module is used to control the bus slave module to send a request signal containing a unique identifier to the bus; wherein, the unique identifier is a combination of the physical address of the bus slave module and an adaptively generated pseudo-random code; The monitoring module is used to control the bus master module to monitor the bus in real time. If a composite signal with multiple superimposed feature identifiers is detected within the preset detection window, it is determined to be a bus conflict. The parsing and identification module is used to control the bus master module to identify the bus slave module involved in the conflict by parsing multiple feature identifiers in the composite signal; The allocation module is used to control the bus master module to allocate different transmission time slots to the identified conflicting bus slave modules. The transmission time slots are determined according to the request order of each conflicting bus slave module and the current load status of the bus. The broadcast module is used to control the bus master module to broadcast a control frame containing a list of conflicting slave modules and the corresponding transmission time slots; The synchronization control module is used to control each conflicting slave module to perform local clock synchronization according to the allocated transmission time slot after receiving the control frame; The synchronous transmission module is used to control each of the conflicting slave modules to send data to the bus within the transmission time slot after synchronization; The reset module is used to control the bus master module to reset the bus listening state and enter the next listening cycle after each conflicting slave module has completed data transmission.

9. A communication conflict detection and control device, characterized in that, include: At least one processor, at least one memory, and computer program instructions stored in the memory, which, when executed by the processor, implement the method as described in any one of claims 1-7.

10. A storage medium storing computer program instructions thereon, characterized in that, The method as described in any one of claims 1-7 is implemented when the computer program instructions are executed by the processor.

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