Core particle interconnection network-oriented fault and congestion combined sensing routing method and system

Abstract

The invention discloses a core particle interconnection network-oriented fault and congestion combined sensing routing method, which comprises the following steps of: detecting a fault state of a two-way link from a current router to each adjacent router, and determining a fault cost from the current router to each adjacent router; detecting the congestion state of each adjacent router of the current router, and determining the congestion cost from the current router to each adjacent router; determining the distance cost from the current router to each adjacent router based on the distance from each adjacent router of the current router to the target router; the total cost from the current router to the adjacent routers is calculated based on the fault cost, the congestion cost and the distance cost from the current router to the adjacent routers, and the input port of the adjacent router with the minimum total cost is selected as the output port of the next hop; a local link fault state and a next hop port congestion degree are sensed in real time, a fault risk, a congestion level and a distance factor are comprehensively evaluated, and a next section of optimal routing path of a current router is dynamically selected.

Description

Technical Field

[0001] This invention belongs to the field of chip-to-chip interconnect technology. More specifically, this invention relates to a fault and congestion joint sensing routing method and system for chip-to-chip interconnect networks. Background Technology

[0002] As the physical limits of Moore's Law approach and the cost of integrated circuit manufacturing skyrockets, traditional monolithic integration has shown its limitations in sustaining computing performance growth. Chiplet technology, by breaking down a large monolithic System-on-Chip (SoC) into multiple smaller, functionally independent chips (chips) and achieving high-speed interconnection through advanced packaging technologies (such as 2.5D / 3D integration), offers key advantages for the post-Moore's Law era, including overcoming performance bottlenecks, optimizing design cycles and costs, and enabling heterogeneous integration. Currently, chip technology has been widely applied in cutting-edge fields such as High-Performance Computing (HPC), Artificial Intelligence (AI), and data centers, becoming a technological focus of common interest in both industry and academia.

[0003] In a chip-on-chip (SoC) system, the chip-on-chip interconnect network serves as the core infrastructure for inter-chip communication, and its performance and reliability directly determine the efficiency and stability of the entire system. Compared to the network-on-chip (NoC) of traditional monolithic SoCs, chip-on-chip interconnect networks face more severe challenges: First, the introduction of advanced packaging technologies (such as through-silicon vias (TSV) and microbumps (μBump)) and extremely high interconnect density significantly increases the risk of manufacturing defects and physical failures, making reliability issues such as link failures increasingly prominent. Second, chip-on-chip systems often contain units with diverse functions, and the workload changes dynamically and is unevenly distributed, resulting in time-varying and spatially localized traffic within the network, which easily leads to network congestion and severely affects communication performance. Link failures and network congestion are two key bottlenecks affecting the performance and reliability of chip-on-chip interconnect networks, and these two factors often coexist and are mutually coupled. Link failures not only reduce available network paths, forcing traffic to detour and potentially exacerbating congestion in other areas, but severe congestion can also lead to packet timeouts, buffer overflows, and other fault-like behaviors, further degrading overall system performance. Therefore, efficient routing algorithms are crucial for ensuring high-performance and highly reliable communication in core systems.

[0004] Existing routing algorithm research can be mainly divided into two categories: static and adaptive. Static routing, due to its fixed path selection strategy, cannot adapt to dynamically changing fault and congestion environments, resulting in significant performance bottlenecks. While adaptive routing algorithms have made some improvements, most existing works are biased. Fault-tolerant routing algorithms focus on bypassing or avoiding physical faults to ensure network connectivity through redundant paths, rerouting, or learning mechanisms; however, they often sacrifice some performance and do not adequately consider new congestion points that may arise on the bypass paths. On the other hand, congestion-aware routing algorithms aim to dynamically select low-load paths by monitoring network load information such as buffer occupancy and link load to achieve traffic balancing and improve network performance. However, these algorithms usually assume a complete and fault-free network topology. When link faults actually occur, the path diversity upon which they rely for load balancing may be disrupted, significantly reducing the effectiveness of the algorithm. They may even make incorrect decisions due to a lack of fault information, failing to effectively cope with fault interference. In summary, current research generally lacks an adaptive routing mechanism that can simultaneously and effectively coordinate the common problems of link faults and dynamic congestion concurrency in chip-and-chip interconnected networks. Summary of the Invention

[0005] This invention provides a fault and congestion-aware routing method for chip interconnect networks, aiming to improve at least one of the above-mentioned problems.

[0006] This invention is implemented as follows: a fault and congestion jointly aware routing method for chip-to-chip interconnect networks, the method comprising the following steps:

[0007] (1) Detect the fault status of the bidirectional links from the current router to each neighboring router, and determine the fault cost from the current router to each neighboring router.

[0008] (2) Detect the congestion status of each neighboring router of the current router and determine the congestion cost from the current router to each neighboring router;

[0009] (3) Determine the distance cost from the current router to each of its neighboring routers based on the distance from the target router to each of the current router's neighboring routers;

[0010] (4) Calculate the total cost from the current router to each neighboring router based on the fault cost, congestion cost and distance cost from the current router to each neighboring router, and select the input port of the neighboring router with the smallest total cost as the next-hop output port;

[0011] Among them, neighbor routers include adjacent routers.

[0012] Furthermore, the congestion state of the adjacent router is the congestion state of the input port of the adjacent router corresponding to the next hop, and the specific detection method is as follows:

[0013] Monitor the number of virtual channels occupied in the input ports of the adjacent routers corresponding to each next hop. If the number of occupied virtual channels exceeds a preset threshold, the corresponding adjacent router is considered to be in a congested state.

[0014] Furthermore, the specific method for detecting the fault status of the bidirectional link between the current router and its neighboring routers is as follows:

[0015] Both the current router and its neighboring router generate two test vectors tv1 and tv2, and send the two test vectors tv1 and tv2 to each other in a time-division multiplexing manner. The receiver receives the two test vectors tv1' and tv2' in a time-division multiplexing manner.

[0016] If the two test vectors tv1' and tv2' are the same as the two sent test vectors tv1 and tv2, then the corresponding link is normal; otherwise, the corresponding link is faulty.

[0017] Furthermore, test vectors tv1 and tv2 are binary sequences of the same length, and the corresponding binary values ​​in test vector tv1 are different from the corresponding binary values ​​in test vector tv2.

[0018] The receiver performs a bitwise XOR operation on the received test vectors tv1' and tv2' from both sides to generate a fault vector F. If there is a value "0" in the fault vector F, it indicates that the corresponding link is in a fault state.

[0019] Furthermore, the formula for calculating the total cost is as follows:

[0020] W(dir) = σ f ×W f (dir)+σ c ×W c (dir)+σ d ×W d (dir)

[0021] Where, σ f σ c σ d W is the weighting coefficient. f (dir) represents the fault cost corresponding to the fault state of the bidirectional link between the current router and each neighboring router, W c (dir) represents the congestion cost corresponding to the congestion state of the input port of the adjacent router, W d (dir) represents the distance cost between the node where the adjacent router is located and the node where the target router is located.

[0022] Furthermore, when both bidirectional links between the current router and its neighboring routers are normal links, the failure cost W f(dir) = 0; when the bidirectional link between the current router and its neighboring router is partially faulty, the fault cost W f (dir) = W pf When the bidirectional link between the current router and its neighboring router is completely faulty, the fault cost W is... f (dir) = INF, where INF > W pf >0.

[0023] Furthermore, when the input port of the adjacent router is in a congested state, the congestion cost W... c (dir) = 1, when the non-congested state of the input port of the adjacent router is a congested state, the congestion cost W c (dir) = 0.

[0024] Furthermore, the distance cost W d (dir) indicates the following:

[0025] W d (dir)=D(neighbor(dir),d)+L router

[0026] Where D(neighbor(dir),d) represents the Manhattan distance from the neighboring router node to the target router node d, and L router This represents the base latency cost of switching from the current router to a neighboring router.

[0027] This invention is implemented as follows: a fault and congestion jointly aware routing system for chip-to-chip interconnect networks, the system comprising:

[0028] Link fault detection unit, congestion detection unit, and adaptive route calculation unit are installed on each router, and the link fault detection unit, congestion detection unit, and adaptive route calculation unit are connected.

[0029] The link fault detection unit is used to detect the fault status of the output link directly connected to the router and send it to the adaptive routing calculation unit;

[0030] The congestion awareness unit is used to monitor the congestion status of the input ports of each adjacent router and send the data to the adaptive routing calculation unit.

[0031] The adaptive routing calculation unit calculates the total cost from the current router to each neighboring router using the fault and congestion joint awareness routing method for chip interconnect networks, with the input port of the neighboring router serving as the next-hop output port.

[0032] Furthermore, the link failure detection module includes: a test vector generator and a test vector comparator;

[0033] The test vector generator generates two test vectors, tv1 and tv2, which are transmitted in a time-division manner to the test vector comparators of the corresponding link-connected routers.

[0034] The test vector comparator receives test vectors tv1' and tv2' in sequence, performs a bitwise XOR operation on test vectors tv1' and tv2' to generate a fault vector F. If there is a value "0" in the fault vector F, it indicates that the corresponding link is in a fault state.

[0035] The test vectors tv1 and tv2 are binary sequences of the same length, and the binary values ​​of each bit in test vector tv1 are different from the corresponding binary values ​​in test vector tv2.

[0036] This invention constructs a cost function that comprehensively evaluates fault risk, congestion level, and distance factors by real-time sensing of local link fault status and next-hop port congestion level, and dynamically selects the next optimal routing path for the current router. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the core system provided in an embodiment of the present invention;

[0038] Figure 2 This is a schematic diagram illustrating the sensing range of link fault information within a two-hop range provided by the link fault sensing unit in an embodiment of the present invention.

[0039] Figure 3 This is a schematic diagram of the link fault status perception process based on the link fault detection module provided in an embodiment of the present invention;

[0040] Figure 4 This is a schematic diagram of the key functional unit architecture of the baseboard router provided in an embodiment of the present invention;

[0041] Figure 5 This is a performance comparison chart under uniform random flow conditions without faults, provided by an embodiment of the present invention.

[0042] Figure 6 The performance comparison of various algorithms under uniform random traffic with the same failure rate is provided in the embodiments of the present invention, wherein (a) 10% failure rate, (b) 20% failure rate;

[0043] Figure 7 This is a comparison chart of the average packet delay of various algorithms provided in the embodiments of the present invention under a fixed injection rate;

[0044] Figure 8 The performance comparison of different traffic patterns under a 20% failure rate is provided for the embodiments of the present invention, wherein (a) transpose, (b) hot spot. Detailed Implementation

[0045] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, so as to help those skilled in the art to have a more complete, accurate and in-depth understanding of the inventive concept and technical solution of the present invention.

[0046] Figure 1 This is a schematic diagram of the structure of a core-particle system provided in an embodiment of the present invention. For ease of explanation, only the parts related to the embodiment of the present invention are shown. The core-particle system includes:

[0047] Several chips and a silicon substrate, a designated chip router in the chip is connected to a substrate router on the silicon substrate, the chips communicate with each other through the silicon substrate, and the processing data packets (Flit) sent by the chip are routed to the target chip through the basic router on the silicon substrate.

[0048] To address the complex challenges of concurrent link failures and network congestion in chip-to-chip interconnect networks, this invention proposes a fault and congestion joint awareness adaptive routing method. The core mechanism of this method lies in the router's ability to jointly evaluate the fault risk, congestion level, and distance cost of all available candidate paths in real time when making routing decisions for each data packet. Based on this comprehensive evaluation result, it dynamically selects the optimal next-hop path for forwarding, aiming to maximize network performance and reliability under complex operating conditions. This invention dynamically selects the optimal routing path by sensing the fault and congestion states in the network, bypassing faulty and congested areas, thereby balancing network load and improving system reliability, providing a more reliable communication environment for integrated chips.

[0049] To detect link faults in the baseboard network, each baseboard router integrates a link fault detection unit. The connection relationships of these link fault detection units are the same as those of their corresponding baseboard routers, forming a link fault status awareness network used to transmit link fault information between baseboard routers. Each baseboard router can detect the fault status of the links corresponding to its 12 neighboring routers, such as... Figure 2 As shown, the received information is stored in the corresponding link fault status register. On the other hand, to sense the congestion status in the baseboard network, the baseboard router is equipped with a congestion sensing unit.

[0050] The core of the congestion-aware unit is a local congestion status register, used to characterize the congestion status of all input ports of the current router. The congestion-aware unit determines congestion by monitoring the number of occupied virtual channels in the input ports. Specifically, if the number of occupied virtual channels in an input port exceeds a preset threshold, the port is considered congested. The link failure and congestion status awareness process is executed every clock cycle to ensure timely updates to the network status and provide accurate status information for subsequent path calculation.

[0051] (1) Fault detection mechanism

[0052] like Figure 3 As shown, this invention integrates a link fault detection module in each baseboard router, capable of real-time detection of the fault status of each directly connected link. The link fault detection module includes a test vector generator and a test vector comparator. Since there are two bidirectional links between the two baseboard routers, the test vector generators of the two baseboard routers generate test vectors and send them to the test vector comparator of the other. The test vector generator generates two test vectors, denoted as test vector tv1 and test vector tv2, which are transmitted on each link. Test vector tv1 and test vector tv2 are transmitted in a time-division multiplexing manner, each transmitted within two consecutive clock cycles. Test vector tv1 and test vector tv2 consist of alternating binary values, with a strategic one-bit offset between them. This offset ensures that any fault that is fixed at 0 (Stuck-at-Zero) or fixed at 1 (Stuck-at-One) can be detected. The test vector generator on the baseboard router transmits the two generated test vectors in a time-division multiplexing manner to the test vector comparators on other baseboard routers connected to its links, and the test vector comparators receive and analyze them.

[0053] The test vector comparator receives the propagated signals tv1' and tv2' sequentially. In a fault-free condition, tv1' and tv2' should be identical to the original test vectors tv1 and tv2, respectively. However, consider a scenario where a fault permanently sets a value to 1 in a lower link. This fault forces some "0" bits to be incorrectly converted to "1". The detection mechanism performs a bitwise XOR operation between tv1' and tv2' to generate a fault vector F. A "1" in fault vector F indicates that the corresponding link is fault-free, while a "0" indicates a fault. Based on fault vector F, the test vector comparator synthesizes a two-bit fault signal, where each bit corresponds to the state (faulty or fault-free) of its two links. For each output direction dir, a 2-bit status code is used to represent F. code (dir) indicates the failure status of its connection link:

[0054]

[0055] The router has a dedicated fault status register that stores and updates these status codes in real time for direct use in subsequent cost calculations. To maintain the algorithm's low complexity and distributed nature, the current design prioritizes utilizing local fault information.

[0056] (2) Congestion sensing mechanism

[0057] In terms of congestion awareness, it is necessary to obtain congestion information from the next-hop router (neighboring router). This invention assumes the existence of a lightweight reverse signaling mechanism between neighboring routers, such as utilizing existing credit flow control signals or designing dedicated sideband signals, to transmit the congestion status of the next-hop input port. The current router then obtains the congestion information of its neighbor (dir)'s corresponding input port in the dir direction. The congestion status is represented by a Boolean value C. status (dir) is used to represent the congestion status of the output direction dir:

[0058]

[0059] Where V is the preset congestion threshold, and F s This is the number of VCs occupied by the input port corresponding to the next-hop neighbor. If the number of VCs occupied by the input port corresponding to the next-hop neighbor is lower than or equal to the congestion threshold, the corresponding input port is defined as non-congested; otherwise, the corresponding input port is defined as congested. The router periodically receives and updates this congestion status information and stores it in its internal registers.

[0060] Figure 4 The key functional units of a baseboard router are described in detail, with particular emphasis on modules added or enhanced to achieve joint awareness. Specifically, each baseboard router integrates a link fault awareness unit and a congestion awareness unit. The link fault awareness unit is responsible for detecting the status of output links directly connected to the router and storing the detected fault information (such as normal, partial fault, and complete fault) in a local link fault status register. Simultaneously, the congestion awareness unit monitors indicators such as the virtual channel buffer occupancy rate of each input port (including ports from neighboring routers and upper-level cores) to assess the congestion level of the ports in real time and stores the quantified congestion status in a local congestion status register. Finally, the real-time fault and congestion status information stored in the local register, along with neighbor status information that may be obtained from the awareness network, are fed to the adaptive routing calculation unit. The adaptive routing calculation unit performs cost calculations based on the cost function proposed in this invention, dynamically selects the next-hop output port with the lowest cost for incoming data packets, and completes data forwarding through cross-connect switches.

[0061] (3) Cost function

[0062] After obtaining real-time fault and congestion status, the cost of each candidate output direction is calculated. This cost function aims to quantify the overall "cost" of selecting a candidate output direction dir as the next hop, and is a key basis for routing decisions. The total cost W(dir) is composed of three weighted parts: fault cost W... f (dir), congestion cost W c (dir) and distance cost W d (dir).

[0063] Failure cost W f (dir) directly reflects the physical reliability of the link: based on the fault status code F of the output direction dir. code (dir) defines the cost of the failure. The more severe the failure, the higher the cost, denoted as W. f The expression for (dir) is as follows:

[0064]

[0065] The cost of a normal link is 0, and the cost of a partially failed link is W. pf (A penalty value greater than 0), the cost of a completely failed link is set to INF (a sufficiently large constant) to prohibit the selection of that direction.

[0066] Congestion Cost W c (dir) quantifies the queuing delay that may be encountered when choosing this direction: directly using the quantified congestion state C. status (dir) represents the congestion cost; the cost for choosing a congested direction is 1, and for a non-congested direction it is 0. The congestion cost W c (dir) indicates the following:

[0067]

[0068] Distance Cost W d (dir) aims to guide data packets toward the destination node, reflecting the distance to the target router node d after selecting the direction dir: it is usually the Manhattan distance D(neighbor(dir),d) from the next-hop router node neighbor(dir) to the target router node d, and the base delay cost L of each hop is taken into account. router Distance cost W d (dir) indicates the following:

[0069] W d (dir)=D(neighbor(dir),d)+L router (5)

[0070] Among them, L router It can be set to 1 or other values ​​that represent the base delay cost per hop.

[0071] The joint weight is obtained by weighted summation of the three sub-costs, and the three sub-costs are then weighted by the weight coefficient σ. f , σ c , σ d Perform a weighted summation to obtain the final path weight W(dir):

[0072] W(dir) = σ f ×W f (dir)+σ c ×W c (dir)+σ d ×W d (dir) (6)

[0073] Where, σ f σ c σ d σ is the weighting coefficient. f σ c σ d The selection of weights is crucial for algorithm performance, directly determining the algorithm's emphasis on fault, congestion, and distance factors. To ensure the correctness and efficiency of routing, the weight coefficients should follow the core principle of prioritizing faults, followed by congestion, and guaranteeing distance as a minimum; that is, setting σ... f ≥σ c >σ d >0. Specifically, σ f It should be large enough to ensure its dominant role in the total cost, thus forcing the algorithm to preferentially avoid any links with faults (especially complete faults); σ c It should be greater than σ d This causes the algorithm to tend to choose non-congested paths to optimize performance when distance and failure conditions are similar; while σ d These coefficients serve as fundamental weights to ensure that data packets proceed in the target direction when there are no significant faults or congestion differences. The specific values ​​of these coefficients need to be optimized and determined through detailed simulation experiments, taking into account factors such as network size and traffic characteristics.

[0074] When a packet arrives and is ready for routing, the adaptive routing calculation unit executes FCARA logic based on the packet's destination address d, the locally stored link fault status information FaultStatus(dir) for each output direction dir (N, E, S, W, L), and the next-hop input port congestion status information CongestionStatus(neighbor_dir) obtained from the neighbor. Its processing flow can be summarized into three steps: state awareness, cost calculation, and route decision. Finally, the routing calculation unit calculates the optimal next-hop direction next... dir The information is passed to the virtual channel allocation unit. The adaptive routing decision process includes: first, determining all possible candidate output directions based on the current router c and destination node d; then, calculating the joint weight W(dir) for each direction; next, eliminating unavailable directions (complete failures) with a weight of INF; and finally, selecting the direction with the minimum joint weight from the remaining available directions. dir As the next jump.

[0075] To comprehensively and quantitatively verify the effectiveness and robustness of the proposed Fault and Congestion Joint Awareness Adaptive Routing Algorithm (FCARA), this section constructs a detailed simulation environment, conducts a series of comparative experiments, and performs an in-depth evaluation of the performance of the FCARA algorithm under different network conditions. It also makes detailed comparisons with various benchmark routing algorithms.

[0076] This experiment uses the periodically accurate Noxim simulator to evaluate the proposed FCARA algorithm (Fault and Congestion Joint Awareness) adaptive routing method for chip interconnect networks. This paper extends the functionality of the Noxim simulator to model systems based on 2.5D chips, such as... Figure 1 As shown, the extended simulator can accurately simulate the microarchitectural behavior of chip interconnect networks, supporting flexible topology configuration, link fault injection, diverse traffic pattern generation, and accurate statistics of key performance indicators.

[0077] Table 1 Simulation parameter configuration

[0078]

[0079] Detailed simulation parameter configurations are shown in Table 1. Each router has five physical input / output ports, connecting to four neighbors (east, west, south, and north) and the local processing unit, respectively. The border router has an additional port connected to the baseboard network. Each port is configured with four virtual channels, and the buffer depth of each virtual channel is set to 8 folds. The fold width is 64 bits, and the average packet length is set to 1–5 folds. To comprehensively examine algorithm performance, three typical traffic patterns were used in the experiment: Uniform Random (UR), simulating a load-balanced scenario; Transpose (TR), simulating an unbalanced global communication pattern; and Hotspot (HS), simulating a scenario where some nodes have highly concentrated loads, with four hotspot nodes receiving an additional 20% of the traffic. Permanent link faults were injected into the experiment, with the fault rate (defined as the percentage of faulty logical link units out of the total) gradually increasing from 0% (no fault) to 30% (high fault). The location of the faulty link was randomly selected and fixed before each simulation run.

[0080] To conduct effective performance comparisons, the experiment selected Dimensional Order Routing (DOR), the representative pure fault-tolerant adaptive routing algorithm FT-Adap, the representative pure congestion-aware adaptive routing algorithm CA-Adap, and ReD, a routing algorithm that combines fault tolerance and deadlock-free characteristics, as benchmark algorithms. Except for ReD, all adaptive algorithms incorporate the same Escape VC mechanism. For the proposed FCARA algorithm, the key parameters are set according to the design principles in Section 3.4 and after preliminary optimization: the weight coefficient is set to σ.f =100, σ c =10, σ d =1, ensuring fault avoidance is the highest priority, followed by congestion awareness, and finally distance factors are considered. The congestion threshold V is set to half the total number of VCs, i.e., V=2. To avoid deadlock, FCARA operates in conjunction with the Escape VC mechanism, with VC0 acting as an Escape VC to force the use of DOR routing.

[0081] This section will present and analyze in detail the performance comparison results of the FCARA algorithm and four benchmark algorithms (DOR, FT-Adap, CA-Adap and ReD) under different network conditions.

[0082] First, the basic communication performance of each algorithm was evaluated under an ideal fault-free (failure rate = 0%) network environment, and the results are as follows: Figure 5 As shown, under fault-free, uniform random traffic, the DOR algorithm, due to its fixed path selection strategy, cannot dynamically avoid instantaneous congestion points caused by random traffic. This results in a rapid increase in average latency after the injection rate exceeds 0.04 flits / cycle / node, with the lowest saturation throughput at approximately 0.35 flits / cycle / node. In this scenario, FT-Adap, lacking a fault-tolerance mechanism, behaves essentially the same as DOR, exhibiting similar performance with a slight but insignificant improvement in saturation throughput. In contrast, both CA-Adap and FCARA algorithms utilize congestion-aware mechanisms, dynamically selecting paths with lower buffer occupancy for forwarding, effectively balancing network load. Therefore, they maintain a low latency growth rate even with high injection rates, significantly improving saturation throughput to approximately 0.75 flits / cycle / node, an improvement of approximately 87.5% compared to DOR. Because FCARA includes additional fault cost calculation logic (which is ineffective in this scenario), its zero-load latency and saturation performance are very close to CA-Adap. While there may be negligible overhead, the overall performance is not significantly different. This result clearly demonstrates that in fault-free scenarios with dynamic load changes, congestion awareness is a key factor in improving interconnect network performance, and the congestion awareness component of the FCARA algorithm is validated here.

[0083] To evaluate the robustness of the algorithm in the presence of link failures, experiments were conducted by injecting different proportions of permanent link failures under uniform random traffic. Figure 6The latency curves of each algorithm are shown when the failure rate is 10% and 20%. As can be seen from the figures, link failures have a significant negative impact on network performance. Latency increases and saturation throughput decreases for all algorithms, with the performance degradation being more severe at higher failure rates. The DOR algorithm has no ability to avoid faulty paths, resulting in the most drastic performance degradation. At high failure rates, it may even cause some nodes to become unreachable due to network segmentation (manifested in simulations as infinitely increasing latency or throughput approaching zero). FT-Adap, by bypassing faulty links, exhibits some fault tolerance compared to DOR, maintaining basic network connectivity. However, its simple bypass strategy does not consider the new congestion that may be caused by bypassing, resulting in still high latency at high injection rates and limited improvement in saturation throughput. For example, at a 20% failure rate, its saturation throughput is only about 0.04 flits / cycle / node. The problem with the CA-Adap algorithm is that it "cannot see" the fault, incorrectly directing packets to the faulty link. It can only rely on the Escape VC mechanism for recovery, which is inefficient and creates severe congestion around the faulty link. Therefore, its performance deteriorates sharply with increasing failure rate. In contrast, the FCARA algorithm exhibits superior robustness. This is due to the design of its joint cost function, where the high-weighted failure cost W... f The algorithm prioritizes fault-free or partially faulty paths, effectively avoiding completely faulty links; meanwhile, the congestion cost W... c This allows it to further select the least congested path from the available non-faulty paths. This synergistic effect of fault avoidance and congestion mitigation enables FCARA to maintain a saturated throughput of approximately 0.75 flits / cycle / node even with a high failure rate of 20%, significantly higher than other algorithms.

[0084] Figure 7This performance difference is presented in a more intuitive and quantifiable way. The graph details the trend of average packet latency as a function of the failure rate, assuming a fixed injection rate (0.04 flits / cycle / node). It clearly shows that as the failure rate increases from 0% to 30%, the latency of DOR and CA-Adap exhibits an exponential growth, quickly becoming unacceptable. FT-Adap's latency growth is relatively slower, although its absolute value remains high. The FCARA algorithm shows the most moderate latency growth; even at a failure rate as high as 30%, its average latency is significantly lower than other algorithms at lower failure rates. For example, at a failure rate of 20%, FCARA's latency is only about 67% of FT-Adap's and 73% of CA-Adap's. This fully demonstrates that the FCARA algorithm, through joint perception and decision-making, can achieve "graceful degradation" of performance under extremely harsh fault environments. That is, when faced with faults, its performance decline is relatively gradual and controllable, demonstrating excellent adaptability and stability.

[0085] To further test the adaptability of the algorithms under unbalanced loads, experiments were conducted at a 20% failure rate to evaluate the performance of each algorithm under transpose (TR) and hotspot (HS) traffic modes. The results are summarized in […]. Figure 8 The results show that unbalanced traffic patterns, due to their inherent load concentration, pose a greater challenge to routing algorithms compared to uniform random patterns, leading to a general decrease in the saturation throughput of all algorithms. For DOR and FT-Adap, the lack of effective congestion management mechanisms results in particularly significant performance degradation when facing specific collision patterns of TR traffic and highly concentrated loads of HS traffic. Although CA-Adap can adapt to unbalanced traffic through congestion awareness, its routing space is limited under a 20% failure rate, and it cannot effectively handle the additional congestion and path interruptions caused by failures, resulting in a significant impact on its throughput. In contrast, the FCARA algorithm benefits from its dual adaptive capabilities—adapting to both congestion distribution differences caused by changes in traffic patterns and changes in network topology due to failures—achieving the highest saturation throughput in both transposed and hotspot traffic patterns. This fully demonstrates that the FCARA algorithm not only performs well under uniform random traffic but also exhibits good adaptability and robustness to unbalanced and challenging communication patterns.

[0086] Based on the experimental results and analysis from the three dimensions above, it is clear that in the simulated chip-and-chip interconnect network environment, when link failures and dynamic network congestion coexist, traditional static routing algorithms (DOR) and adaptive routing algorithms that only focus on a single problem (such as FT-Adap focusing on failures and CA-Adap focusing on congestion) struggle to provide satisfactory performance and reliability guarantees. The proposed FCARA algorithm, by innovatively introducing a joint fault and congestion awareness mechanism and designing a joint cost function to guide routing decisions, achieves a comprehensive and coordinated consideration of the real-time network state. Experimental results strongly demonstrate that FCARA significantly outperforms benchmark algorithms under various failure rates and traffic patterns, especially under complex and harsh conditions such as high failure rates and unbalanced traffic, exhibiting the lowest average latency, the highest saturation throughput, and stronger robustness. This fully validates the effectiveness of the FCARA algorithm design and indicates its significant application potential in improving the communication efficiency of future high-performance, high-reliability chip-and-chip interconnect networks.

[0087] To comprehensively evaluate the implementation overhead of the proposed routing algorithms, this section models and synthesizes their hardware implementations, analyzing their costs in terms of area and power consumption. This paper uses Verilog HDL to model different routers. All designs were synthesized using Synopsys Design Compiler, based on a commercial 65nm standard cell technology library, with a target clock frequency of 1.0GHz and typical operating conditions. Power consumption analysis is based on the synthesized gate-level netlist and the SAIF activity file (UR traffic, injection rate 0.3, failure rate 10%) generated through simulation, using Synopsys PrimeTime PX.

[0088] Table 2 details the area overhead estimates for each major component of the router under different routing algorithms. It can be seen that the increase in area overhead mainly stems from the increased complexity of the routing computation unit. Compared to the baseline DOR RC unit (approximately 3850.2 μm)... 2 The FT-Adap RC module has a slightly increased area of ​​approximately 4420.8 μm due to the addition of fault diagnosis logic. 2 (Approximately 114.8%). CA-Adap RC introduces congestion cost calculation and comparison, and the area is significantly increased to approximately 6510.5 μm. 2 (Approximately 169.1%). FCARA RC, however, requires simultaneous processing of fault and congestion information and performs joint cost calculations, resulting in the largest area overhead, reaching approximately 9550.7 μm. 2This is approximately 2.48 times the area of ​​the DOR RC. It's worth noting that other logic units such as VA, SA, and control logic also see a slight increase in area to support more complex routing decisions, but the increase is far smaller than that of the RC unit. The input buffer (approximately 29875.5 μm) occupies the majority of the router's area. 2 ) and cross switches (approximately 7450.3μm) 2 The area of ​​the RC unit is largely unaffected by the logical complexity of the routing algorithm. Therefore, although the relative area increase of the RC unit is significant, its low proportion in the total router area (DOR RC accounts for approximately 7.8% of the total area) ultimately results in a smaller overall area of ​​the FCARA router (approximately 55968.4 μm). 2 Compared to DOR (approximately 49496.8 μm) 2 It only increased by about 13.1%.

[0089] Table 2. Area cost (μm) of main components under different routing algorithms 2 )

[0090]

[0091] Table 3 further illustrates the total power consumption estimates of the router's main components under different routing algorithms. The power consumption analysis results show a similar trend to the area overhead, but the relative increase is slightly different. The power consumption increase is also mainly concentrated in the RC unit. The total power consumption of the FCARA RC (approximately 1.80mW) increased by approximately 130.8% compared to the DOR RC (approximately 0.78mW). This is mainly due to the increased number of gate circuits resulting from more complex logic (increasing static power consumption) and increased signal switching activity (increasing dynamic power consumption). The power consumption of other logic units also increased slightly with area. The power consumption of the input buffer and crossbar switch is less affected by the routing algorithm logic; their slight changes mainly come from the differences in internal data activity patterns that may be caused by different routing strategies. Ultimately, the overall total power consumption of the FCARA router (approximately 11.36mW) increased by approximately 15.6% compared to the DOR (approximately 9.83mW).

[0092] Table 3 Power consumption (mW) of major components under different routing algorithms

[0093]

[0094] A comprehensive analysis of hardware overhead data clearly shows that the introduction of the FCARA algorithm does indeed bring additional hardware costs, primarily due to the increased complexity of the routing computation unit, leading to a significant increase in the area and power consumption of the RC unit. However, since the RC unit accounts for a limited proportion of the overall router hardware budget, this increase effectively mitigates its impact on the overall router area and power consumption, keeping the total overhead increase below 16%. Considering the significant advantages demonstrated by the FCARA algorithm in performance evaluation, especially its substantial improvements in network latency, throughput, and robustness under high failure rates and complex traffic conditions, this moderate increase in hardware overhead is generally acceptable. This indicates that the FCARA algorithm can provide a good performance-cost-benefit trade-off in core system applications that prioritize high performance and high reliability, making it highly valuable for practical applications. Designers can make reasonable choices among different routing algorithms based on the performance requirements and hardware resource constraints of specific application scenarios.

[0095] To address the increasingly prominent challenges of concurrent link failures and network congestion in chip-to-chip interconnect networks (CTI), this paper proposes a Joint Fault and Congestion Awareness Adaptive Routing (FCARA) algorithm. This algorithm innovatively constructs a joint cost function that comprehensively evaluates fault risk, congestion level, and distance factors by real-time sensing of local link failure status and next-hop port congestion. Based on this function, it dynamically and intelligently selects the optimal next-hop path. Comprehensive simulation results demonstrate that, compared with classic deterministic routing, pure fault-tolerant routing, and pure congestion-aware routing, the FCARA algorithm exhibits superior overall performance and robustness under various failure rate and traffic patterns, especially under harsh conditions such as high failure rates and unbalanced traffic. Hardware overhead analysis confirms that FCARA keeps the increase in router overall area and power consumption within a reasonable range, reflecting a good performance-cost-benefit trade-off. In conclusion, the proposed FCARA algorithm provides an effective solution to address the key reliability and performance challenges in CTI, and has important reference value for designing high-performance, highly reliable CTI systems.

[0096] The present invention has been described by way of example. Obviously, the specific implementation of the present invention is not limited to the above-described manner. Any non-substantial improvements made using the inventive concept and technical solution of the present invention, or the direct application of the inventive concept and technical solution of the present invention to other occasions without modification, are all within the protection scope of the present invention.

Claims

1. A fault and congestion joint sensing routing method for chip-particle interconnect networks, characterized in that, The method includes the following steps: (1) Detect the fault status of the bidirectional links from the current router to each neighboring router, and determine the fault cost from the current router to each neighboring router. (2) Detect the congestion status of each neighboring router of the current router and determine the congestion cost from the current router to each neighboring router; (3) Determine the distance cost from the current router to each of its neighboring routers based on the distance from the target router to each of the current router's neighboring routers; (4) Calculate the total cost from the current router to each neighboring router based on the fault cost, congestion cost and distance cost from the current router to each neighboring router, and select the input port of the neighboring router with the smallest total cost as the next-hop output port; Among them, neighbor routers include adjacent routers.

2. The fault and congestion joint sensing routing method for chip interconnect networks as described in claim 1, characterized in that, The congestion state of an adjacent router is the congestion state of the input port of the next-hop adjacent router, and the specific detection method is as follows: Monitor the number of virtual channels occupied in the input ports of the adjacent routers corresponding to each next hop. If the number of occupied virtual channels exceeds a preset threshold, the corresponding adjacent router is considered to be in a congested state.

3. The fault and congestion joint sensing routing method for chip-to-chip interconnect networks as described in claim 1, characterized in that, The specific method for detecting fault status in the bidirectional link between the current router and its neighboring routers is as follows: Both the current router and its neighboring router generate two test vectors tv1 and tv2, and send the two test vectors tv1 and tv2 to each other in a time-division multiplexing manner. The receiver receives the two test vectors tv1' and tv2' in a time-division multiplexing manner. If the two test vectors tv1' and tv2' are the same as the two sent test vectors tv1 and tv2, then the corresponding link is normal; otherwise, the corresponding link is faulty.

4. The fault and congestion joint sensing routing method for chip-to-chip interconnect networks as described in claim 3, characterized in that, Test vectors tv1 and tv2 are binary sequences of the same length, and the corresponding binary values ​​in test vector tv1 and test vector tv2 are different. The receiver performs a bitwise XOR operation on the received test vectors tv1' and tv2' from both sides to generate a fault vector F. If there is a value "0" in the fault vector F, it indicates that the corresponding link is in a fault state.

5. The fault and congestion joint sensing routing method for chip-to-chip interconnect networks as described in claim 1, characterized in that, The formula for calculating the total cost is as follows: W(dir)=σ f ×W f (dir)+s c ×W c (dir)+s d ×W d (dir) Where, σ f σ c σ d W is the weighting coefficient. f (dir) represents the fault cost corresponding to the fault state of the bidirectional link between the current router and each neighboring router, W c (dir) represents the congestion cost corresponding to the congestion state of the input port of the adjacent router, W d (dir) represents the distance cost between the node where the adjacent router is located and the node where the target router is located.

6. The fault and congestion joint sensing routing method for chip-to-chip interconnect networks as described in claim 5, characterized in that, When both bidirectional links between the current router and its neighboring routers are normal, the failure cost W is... f (dir) = 0; when the bidirectional link between the current router and its neighboring router is partially faulty, the fault cost W f (dir) = W pf When the bidirectional link between the current router and its neighboring router is completely faulty, the fault cost W is... f (dir) = INF, where INF > W pf >0.

7. The fault and congestion joint sensing routing method for chip interconnect networks as described in claim 5, characterized in that, When the congestion state of the input port of the adjacent router is congested, the congestion cost W c (dir) = 1, when the non-congested state of the input port of the adjacent router is a congested state, the congestion cost W c (dir) = 0.

8. The fault and congestion joint sensing routing method for chip-to-chip interconnect networks as described in claim 5, characterized in that, Distance Cost W d (dir) indicates the following: W d (dir)=D(neighbor(dir),d)+L router Where D(neighbor(dir),d) represents the Manhattan distance from the neighboring router node to the target router node d, and L router This represents the base latency cost of switching from the current router to a neighboring router.

9. A fault and congestion joint sensing routing system for chip-to-chip interconnect networks, characterized in that, The system includes: Link fault detection unit, congestion detection unit, and adaptive route calculation unit are installed on each router, and the link fault detection unit, congestion detection unit, and adaptive route calculation unit are connected. The link fault detection unit is used to detect the fault status of the output link directly connected to the router and send it to the adaptive routing calculation unit; The congestion awareness unit is used to monitor the congestion status of the input ports of each adjacent router and send the data to the adaptive routing calculation unit. The adaptive routing calculation unit calculates the total cost from the current router to each neighboring router based on the fault and congestion joint awareness routing method for chip interconnect networks as described in any one of claims 1 to 8, with the input port of the neighboring router serving as the next-hop output port.

10. A fault and congestion joint sensing routing system for chip-to-chip interconnect networks, characterized in that, The link failure detection module includes: a test vector generator and a test vector comparator; The test vector generator generates two test vectors, tv1 and tv2, which are transmitted in a time-division manner to the test vector comparators of the corresponding link-connected routers. The test vector comparator receives test vectors tv1' and tv2' in sequence, performs a bitwise XOR operation on test vectors tv1' and tv2' to generate a fault vector F. If there is a value "0" in the fault vector F, it indicates that the corresponding link is in a fault state. The test vectors tv1 and tv2 are binary sequences of the same length, and the binary values ​​of each bit in test vector tv1 are different from the corresponding binary values ​​in test vector tv2.

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