Wafer test data transmission method and device, computer equipment and storage medium
By automatically calculating the divisor for block division and screening effective dies, the system burden caused by excessive wafer test data volume is solved, achieving efficient data transmission and analysis, reducing system burden and improving detection accuracy.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-21
- Publication Date
- 2026-03-27
AI Technical Summary
In existing technologies, the excessive amount of wafer test data leads to an excessive processing burden on the design technology collaborative optimization system, and the lack of filtering for abnormal data can easily drag down system performance.
By automatically calculating the block division divisor, the wafer is divided into representative blocks, and only the die measurement values of the representative blocks are sent to the design technology collaborative optimization system for analysis. At the same time, valid dies are screened out, and the measurement values of abnormal dies are avoided from being input.
This reduces the processing burden of the design technology collaborative optimization system, improves the efficiency of block partitioning, and ensures detection accuracy and system stability.
Smart Images
Figure CN120980038B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of chip testing, and particularly relates to a wafer test data transmission method and device, computer equipment and a storage medium. BACKGROUND
[0002] In the process of chip design and process manufacturing, integrated optimization is often sought through the method of design-technology co-optimization (DTCO) to improve performance, power efficiency, transistor density, and cost. The dies on the wafer / silicon wafer are measured by an automatic test equipment (ATE) to obtain relevant parameters, which are transmitted to a DTCO system for data analysis, and then an improvement direction is obtained.
[0003] However, the DTCO requires a large number of measurement items, and the data generated by one lot (a batch of wafers subjected to the same processing steps) can reach tens of millions or even hundreds of millions. The existing method usually transmits the measurement values of each die to the system, and such a large amount of data will cause the processing burden of the DCTO system to be too large.
[0004] Therefore, the prior art still needs to be improved and developed. SUMMARY
[0005] In view of the above problems of the prior art, the present application aims to provide a wafer test data transmission method and device, computer equipment and a storage medium to solve the problem that the processing burden of the DCTO system is too large due to too large data flow when the wafer data is tested.
[0006] The technical solutions of the present application are as follows:
[0007] In a first aspect, the present application provides a wafer test data transmission method, which comprises:
[0008] obtaining the amount of data to be transmitted and the expected amount of data to be transmitted for each wafer;
[0009] square rooting the ratio of the amount of data to be transmitted and the expected amount of data to be transmitted;
[0010] obtaining a division divisor by taking the square root value obtained after square rooting and taking the upper value;
[0011] dividing the wafer into blocks according to the division divisor and obtaining the number of blocks to be transmitted;
[0012] obtaining the test data of one die on the block to be transmitted and sending it to a design-technology co-optimization system for analysis.
[0013] The step of obtaining the division divisor according to the division of the amount of data to be transmitted and the expected amount of data of the transmission block further comprises:
[0014] Square root of the ratio of the amount of data to be transmitted and the expected amount of data of the transmission block;
[0015] The value obtained by square root is rounded up to obtain the division divisor.
[0016] The step of dividing the wafer into blocks according to the division divisor and obtaining the number of blocks to be transmitted further comprises:
[0017] Divide the wafer into blocks along the transverse direction and the longitudinal direction of the wafer with the division divisor; wherein the division divisor represents the number of grids that need to be divided on the wafer.
[0018] The step of obtaining the test data of one of the dies on the block to be transmitted and sending it to the design technology collaborative optimization system for analysis further comprises:
[0019] Obtain the measurement value of the die at the same position of each block to be transmitted, and take the coordinates of the die and the measurement value as the representative value and representative coordinates of the block to be transmitted;
[0020] Send the measurement value of the die at the same position of each block to be transmitted to the design technology collaborative optimization system.
[0021] The step of obtaining the test data of one of the dies on the block to be transmitted and sending it to the design technology collaborative optimization system for analysis further comprises:
[0022] Obtain the measurement value of the die on the block to be transmitted and average to obtain the average measurement value;
[0023] Assign the coordinates of the die at the center of the block to be transmitted to the average measurement value, and take the coordinates of the center die and the measurement value as the representative value and representative coordinates of the block to be transmitted.
[0024] The step of obtaining the test data of one of the dies on the block to be transmitted and sending it to the design technology collaborative optimization system for analysis further comprises:
[0025] Screen the dies on each block to be transmitted to screen out effective dies;
[0026] If the dies in the block to be transmitted are all abnormal dies, the test data of the block with all abnormal dies is not transmitted to the design technology collaborative optimization system.
[0027] Further, the expression of the division divisor is:
[0028] .
[0029] In a second aspect, the present application further provides a wafer test data transmission device, comprising:
[0030] an acquisition unit, configured to acquire an amount of data to be transmitted for each wafer and an expected amount of data to be transmitted for each block;
[0031] a calculation unit, configured to square a ratio of the amount of data to be transmitted to the expected amount of data to be transmitted for each block, and obtain a division divisor by rounding up the squared value;
[0032] a block division unit, configured to divide the wafer into blocks according to the division divisor and obtain a number of blocks to be transmitted;
[0033] a data sending unit, configured to acquire test data of one die on the block to be transmitted and send the test data to a design technology collaborative optimization system for analysis.
[0034] In a third aspect, the present application further provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer program is used to implement the steps of the wafer test data transmission method when executed by the processor.
[0035] In a fourth aspect, the present application further provides a storage medium, wherein the storage medium stores a computer program, and the computer program is used to implement the steps of the wafer test data transmission method when executed by a processor.
[0036] The wafer test data transmission method, device, computer equipment and storage medium provided by the present application, the wafer test data transmission method comprises: obtaining the amount of data to be transmitted and the expected amount of block data to be transmitted of each wafer; square root of the ratio of the amount of data to be transmitted and the expected amount of block data to be transmitted; the value obtained after square root is taken is taken up to obtain a division divisor; the wafer is divided into blocks according to the division divisor, and the number of blocks to be transmitted is obtained; the test data of one die on the block to be transmitted is obtained and sent to the design technology collaborative optimization system for analysis. The present application can automatically calculate the appropriate block division divisor to automatically realize the wafer block processing, which greatly improves the efficiency of block division compared with the traditional scheme of manually planning the division divisor on the wafer (the staff needs to plan the division divisor on the wafer, that is, the staff needs to try multiple division methods repeatedly to calculate the corresponding block data amount to find the division divisor close to the expected block data amount, which is extremely low in efficiency). In this way, the present application only sends the measurement value of the die representing the block in the wafer to the design technology collaborative optimization system for analysis, which can reduce the processing burden of the design technology collaborative optimization system while ensuring the detection of wafer feature distribution. BRIEF DESCRIPTION OF DRAWINGS
[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings according to the structures shown in these drawings without creative labor.
[0038] Figure 1 It is a flowchart of the wafer test data transmission method in the present application.
[0039] Figure 2 It is a principle diagram of automatic block division in an embodiment of the present application.
[0040] Figure 3 It is a diagram of obtaining the representative value and representative coordinate of each block after automatic block division in an embodiment of the present application.
[0041] Figure 4 It is a diagram of obtaining the representative value and representative coordinate of each block in the case of lacking die in the block in an embodiment of the present application.
[0042] Figure 5 It is a diagram of obtaining the representative value and representative coordinate of each block in an embodiment of the present application.
[0043] Figure 6is a schematic diagram of obtaining a representative value and a representative coordinate of a block when there is an abnormal crystal grain in the block in one embodiment of the present application.
[0044] Figure 7 is a schematic diagram of obtaining a representative value and a representative coordinate of a block when all the crystal grains in the block are abnormal in one embodiment of the present application.
[0045] Figure 8 is a principle block diagram of a wafer test data transmission device. DETAILED DESCRIPTION
[0046] The present application provides a wafer test data transmission method, device, computer equipment and storage medium, in order to make the purpose, technical scheme and effect of the present application more clear and definite, the present application will be further described in detail below with reference to the drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and not to limit the present application.
[0047] In the embodiments and the patent application scope, unless the article has a special definition in the text, "one", "a", "said" and "the" can also include the plural form. If the description of "first", "second" and the like is involved in the embodiments of the present application, the description of "first", "second" and the like is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can be explicitly or implicitly included at least one of the features.
[0048] It should be further understood that the phrase "comprising" used in the specification of the present application means that the features, integers, steps, operations, elements and / or components exist, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when an element is said to be "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intermediate elements. In addition, "connection" or "coupling" used herein can include wireless connection or wireless coupling. The phrase "and / or" used herein includes all or any single unit and all combinations of the associated listed items.
[0049] Those skilled in the art can understand that, unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as that generally understood by those skilled in the art to which the present application belongs. It should also be understood that terms such as those defined in general dictionaries should be understood as having meanings consistent with those in the prior art, and should not be interpreted with idealized or overly formal meanings unless specifically defined as such.
[0050] In addition, the technical solutions among various embodiments can be combined with each other, but the combination of the technical solutions should be considered not to exist and not within the protection scope of the present application on the basis that the combination of the technical solutions can be realized by the ordinary skilled in the art, and the combination of the technical solutions cannot be realized or contradicts each other.
[0051] The inventor has found that the DTCO requires a large number of measurement items, and the data generated by one lot (a batch of wafers subjected to the same processing steps) can reach tens of millions or even hundreds of millions. The existing method usually transmits the measurement value of each die to the system, and such a large amount of data will cause the processing burden of the DCTO system to be too large. Moreover, the existing method does not filter abnormal data before transmitting the data to the system. Instead, the DCTO system filters and screens one by one, which easily drags down the system performance.
[0052] In view of the above technical problems, the present application provides a wafer test data transmission method and device, computer equipment and storage medium, which can automatically realize wafer blocking processing, and only transmit the measurement value of the die representing the block in the wafer to the design technology collaborative optimization system for analysis, so as to reduce the processing burden of the design technology collaborative optimization system while ensuring the detection of wafer feature distribution. In addition, the effective dies of the wafer are screened before testing, so that the measurement value of the abnormal die will not be input to the design technology collaborative optimization system for analysis, and the design technology collaborative optimization system does not need to detect the abnormal state of the die, which can further reduce the processing burden of the design technology collaborative optimization system.
[0053] Please refer to Figures 1 to 7 The present application provides a preferred embodiment of a wafer test data transmission method.
[0054] In some embodiments, as Figure 1 The present application provides a wafer test data transmission method, which includes the following steps:
[0055] S100, obtaining the amount of data to be transmitted and the expected amount of data to be transmitted for each wafer;
[0056] Specifically, the wafer (or silicon wafer) is composed of a plurality of arranged dies, each die has its own coordinate value and measurement value. The expected amount of data to be transmitted refers to theoretically dividing the dies on the wafer into blocks, and analyzing the feature distribution of the wafer in the design technology collaborative optimization system in units of blocks, so that the analysis result obtained is accurate.
[0057] S200, obtaining a division divisor according to the amount of data to be transmitted and the expected amount of data to be transmitted;
[0058] Specifically, the division divisor refers to the number of dies that need to be divided in the wafer transverse direction (X-axis direction) and longitudinal direction (Y-axis direction). The division divisor is calculated by the amount of data to be transmitted and the expected amount of data to be transmitted.
[0059] S300, dividing the wafer into blocks according to the division divisor and obtaining the number of blocks to be transmitted;
[0060] Specifically, please refer to Figure 2 and Figure 3 , in Figure 3 , the origin represents the selected die, for example, when the division divisor is calculated to be 3, then divide every 3 grids in the X-axis and Y-axis of the wafer to obtain the actual number of blocks to be transmitted. It should be noted that there may be a small error between the actual amount of block data to be transmitted and the expected amount of block data to be transmitted according to the division divisor, for example, the expected amount of block data to be transmitted is 90, the division divisor is 3, and every 3 grids in the X-axis and Y-axis are divided, and the actual amount of block data to be transmitted is calculated to be 86. The actual amount of block data to be transmitted is close to the expected amount of block data to be transmitted, and will not affect the analysis result.
[0061] S400, obtaining the test data of one of the dies on the block to be transmitted and sending it to the design technology collaborative optimization system for analysis.
[0062] Specifically, the design technology collaborative optimization system is a system capable of data analysis on the input wafer measurement data. By analyzing the feature distribution of each region on the wafer, the improvement direction of the wafer can be obtained. After completing the block division of the wafer, the coordinate values and measurement values of the dies on each block to be transmitted can be taken as representative of the coordinate values and measurement values of the corresponding block to be transmitted and sent to the design technology collaborative optimization system for data analysis to complete the test of the wafer.
[0063] In the above technical solution, the present application can automatically calculate the appropriate block division divisor to automatically realize the block division of the wafer, which greatly improves the efficiency of block division compared with the traditional scheme of manually planning the division divisor on the wafer (the worker needs to plan the division divisor on the wafer manually, i.e. the worker needs to try multiple division methods repeatedly to calculate the corresponding block data amount in order to find the division divisor close to the expected amount of block data to be transmitted, which is extremely low in efficiency). In this way, the present application only sends the measurement values of the dies representing the blocks in the wafer to the design technology collaborative optimization system for analysis, which can reduce the data transmission amount and reduce the computational burden of the design technology collaborative optimization system while ensuring the detection of the feature distribution of the wafer.
[0064] In some embodiments, the step of obtaining the division divisor according to the amount of data to be transmitted and the expected amount of data to be transmitted comprises:
[0065] S210, square root of the ratio of the amount of data to be transmitted and the expected amount of data to be transmitted block;
[0066] S220, the value obtained after square root is obtained by rounding up the division divisor.
[0067] In this embodiment, when calculating the division divisor, the expression of the division divisor is: .
[0068] Where ROUNDUP refers to rounding up, for example, the value obtained after square root of the ratio of the amount of data to be transmitted and the expected amount of data to be transmitted block is between 2 and 3.31, then rounding up to 3, so that the block data obtained by division is closer to the expected amount of data to be transmitted block, that is, the block data obtained after rounding up is more than the case without rounding up, so that the detection of wafer feature distribution in the design technology collaborative optimization system is more accurate.
[0069] In some embodiments, the step of dividing the wafer into blocks according to the division divisor and obtaining the number of blocks to be transmitted comprises:
[0070] S310, dividing the wafer into blocks along the transverse direction and the longitudinal direction of the wafer with the division divisor; wherein the division divisor represents the number of cells to be divided on the wafer.
[0071] In this embodiment, the X-axis direction and the Y-axis direction of the wafer are taken as the transverse direction and the longitudinal direction of the wafer, for example, when the division divisor is calculated to be 4, then divide every 4 cells on the X-axis and Y-axis of the wafer to obtain the number of blocks to be transmitted.
[0072] In some embodiments, the step of obtaining the test data of one of the dies on the block to be transmitted and sending it to the design technology collaborative optimization system for analysis comprises:
[0073] S410, obtaining the measurement value of the die at the same position of each block to be transmitted, and taking the coordinates of the die and the measurement value as the representative value and representative coordinates of the block to be transmitted;
[0074] S420, sending the measurement value of the die at the same position of each block to be transmitted to the design technology collaborative optimization system.
[0075] In the embodiment, after the division of the wafer into blocks is completed, the measurement values of the dies at the same position coordinates of each block are directly taken, and then the measurement values of each block are sent to the design technology integration system. In the embodiment, the dies at the same position of each block are directly taken, without any calculation, so that the computing power can be reduced and the power consumption can be lowered. It should be noted that for the blocks at the edge of the wafer, if there is no die at the same position as other dies on the wafer, the measurement value of the die at the same position is taken as shown in Figure 4
[0076] In some embodiments, the step of obtaining the test data of one of the dies on the block to be transmitted and sending the test data to the design technology integration optimization system for analysis comprises:
[0077] S410, obtaining the measurement values of the dies on the block to be transmitted and performing average processing to obtain a measurement average value;
[0078] S420, assigning the measurement average value to the coordinates of the die at the center of the block to be transmitted, and taking the coordinates and the measurement value of the center die as the representative value and the representative coordinates of the block to be transmitted.
[0079] In the embodiment, please refer to Figure 5 The measurement data of all the dies of the divided blocks are summed, and then the measurement average value is calculated. The calculated measurement average value is assigned to the coordinates of the die at the center, and the coordinates and the measurement value of the center die are taken as the representative value of the coordinates and the measurement value of the corresponding block. In this way, the test data sent to the design technology integration optimization system is more accurate in analyzing the feature distribution of the wafer.
[0080] In some embodiments, the step of obtaining the test data of one of the dies on the block to be transmitted and sending the test data to the design technology integration optimization system for analysis further comprises:
[0081] S430, screening the dies on each block to be transmitted to screen out effective dies;
[0082] S440, if all the dies in the block to be transmitted are abnormal dies, the test data of the block with all abnormal dies is not transmitted to the design technology integration optimization system.
[0083] In the embodiment, please refer to Figure 6 and Figure 7 In Figure 6 and Figure 7 In the figure, the origin represents the selected die, and the rectangle represents the abnormal die. Before testing the wafer, the integrated circuit automatic test machine detects the dies on the wafer to distinguish the valid dies from the abnormal dies. After dividing the wafer into blocks, the validity of the dies on each block is detected. When a die is directly selected for detection, if the selected die is an abnormal die, a nearby die is selected as the representative die of the corresponding block. If all the dies of all the blocks are abnormal dies, the corresponding block is not included in the detection range. When the measurement values of the dies are averaged and then assigned to the center die of the block, the abnormal dies are excluded before the average calculation of the measurement values, and then the coordinates of the center die of the block are assigned as the representative value and the representative coordinates of the corresponding block.
[0084] In some embodiments, as shown in FIG. 1, the present application also provides a wafer test data transmission device, which comprises: Figure 8
[0085] The acquisition unit is configured to acquire the amount of data to be transmitted and the amount of data of the blocks expected to be transmitted for each wafer. Details are described in the embodiments of the wafer test data transmission method, which are not repeated here.
[0086] The calculation unit is configured to obtain a division divisor according to the amount of data to be transmitted and the amount of data of the blocks expected to be transmitted. Details are described in the embodiments of the wafer test data transmission method, which are not repeated here.
[0087] The block division unit is configured to divide the wafer into blocks according to the division divisor and obtain the number of blocks to be transmitted. Details are described in the embodiments of the wafer test data transmission method, which are not repeated here.
[0088] The data sending unit is configured to acquire the test data of one die on the block to be transmitted and send the test data to the design technology collaborative optimization system for analysis. Details are described in the embodiments of the wafer test data transmission method, which are not repeated here.
[0089] In some embodiments, the present application also provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the computer program is used to implement the steps in the following method when executed by the processor:
[0090] S100, acquiring the amount of data to be transmitted and the amount of data of the blocks expected to be transmitted for each wafer;
[0091] S200, obtaining a division divisor according to the amount of data to be transmitted and the amount of data of the blocks expected to be transmitted;
[0092] S300, dividing the wafer into blocks according to the division divisor and obtaining the number of blocks to be transmitted.
[0093] S400, test data of one of the dies on the block to be transmitted is acquired and sent to a design technology collaborative optimization system for analysis.
[0094] In some embodiments, the application also provides a storage medium having a computer program stored thereon, the computer program being executed by a processor to implement the steps in the following method:
[0095] S100, the amount of data to be transmitted for each wafer and the expected amount of data to be transmitted for each block are acquired;
[0096] S200, a division divisor is obtained according to the amount of data to be transmitted and the expected amount of data to be transmitted for each block;
[0097] S300, the wafer is divided into blocks according to the division divisor, and the number of blocks to be transmitted is obtained;
[0098] S400, test data of one of the dies on the block to be transmitted is acquired and sent to a design technology collaborative optimization system for analysis.
[0099] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by a computer program instructing related hardware, and the computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. Any reference to memory, storage, database or other medium used in the embodiments provided by the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM) and memory bus dynamic RAM (RDRAM).
[0100] In summary, the wafer test data transmission method and device, computer equipment and storage medium provided by the present application have the following beneficial effects:
[0101] The wafer can be automatically divided into blocks, and only the measurement values of the grains representing the blocks in the wafer are sent to the design technology collaborative optimization system for analysis, so that the processing burden of the design technology collaborative optimization system can be reduced while ensuring the detection of the feature distribution of the wafer.
[0102] Before testing, the effective grains of the wafer are screened, so that the measurement values of abnormal grains will not be input to the design technology collaborative optimization system for analysis, and the design technology collaborative optimization system does not need to detect the abnormal state of the grains, which can further reduce the processing burden of the design technology collaborative optimization system.
[0103] It should be understood that the application of the present application is not limited to the above examples, and those skilled in the art can make improvements or changes according to the above description, and all these improvements and changes shall belong to the protection scope of the appended claims of the present application.
Claims
1. A wafer test data transmission method, characterized by, The method comprises the following steps: Obtaining the amount of data to be transmitted for each wafer and the expected amount of data to be transmitted for each block; Taking the square root of the ratio of the amount of data to be transmitted and the expected amount of data to be transmitted for each block; Taking the square root of the value obtained after taking the square root to obtain the division divisor; Dividing the wafer into blocks according to the division divisor and obtaining the number of blocks to be transmitted; Obtaining the test data of one of the dies on the block to be transmitted and sending it to the design technology collaborative optimization system for analysis; the step of dividing the wafer into blocks according to the division divisor and obtaining the number of blocks to be transmitted comprises: Dividing the wafer into blocks along the transverse direction and the longitudinal direction of the wafer with the division divisor; wherein the division divisor represents the number of grids that need to be divided on the wafer; The step of obtaining the test data of one of the dies on the block to be transmitted and sending it to the design technology collaborative optimization system for analysis comprises: Obtaining the measurement value of the die at the same position of each block to be transmitted, and taking the coordinates of the die and the measurement value as the representative value and representative coordinates of the block to be transmitted; Sending the measurement value of the die at the same position of each block to be transmitted to the design technology collaborative optimization system.
2. The wafer test data transfer method of claim 1, wherein, The step of obtaining the test data of one of the dies on the block to be transmitted and sending it to the design technology collaborative optimization system for analysis comprises: Obtaining the measurement value of the die on the block to be transmitted and performing average processing to obtain the average measurement value; Assigning the average measurement value to the coordinates of the die at the center of the block to be transmitted, and taking the coordinates of the center die and the measurement value as the representative value and representative coordinates of the block to be transmitted.
3. The wafer test data transfer method of claim 1, wherein, The step of obtaining the test data of one of the dies on the block to be transmitted and sending it to the design technology collaborative optimization system for analysis further comprises: Screening the dies on each block to be transmitted to screen out effective dies; If all the dies in the block to be transmitted are abnormal dies, the test data of the block with all abnormal dies is not transmitted to the design technology collaborative optimization system.
4. The wafer test data transfer method of claim 1, wherein, The expression of the division divisor is: ; where ROUNDUP means rounding up.
5. A wafer test data transmission apparatus based on the wafer test data transmission method according to any one of claims 1 to 4, characterized by The method comprises the following steps: An obtaining unit is configured to obtain the amount of data to be transmitted for each wafer and the expected amount of data to be transmitted for each block; A calculation unit is configured to take the square root of the ratio of the amount of data to be transmitted and the expected amount of data to be transmitted for each block, and take the square root of the value obtained after taking the square root to obtain the division divisor; A block division unit is configured to divide the wafer into blocks according to the division divisor and obtain the number of blocks to be transmitted; A data sending unit is configured to obtain the test data of one of the dies on the block to be transmitted and send it to the design technology collaborative optimization system for analysis.
6. A computer device, comprising: The computer program is executed by the processor to implement the steps in the wafer test data transmission method according to any one of claims 1-4.
7. A storage medium having stored thereon a computer program, characterized in that The computer program is executed by the processor to implement the steps in the wafer test data transmission method according to any one of claims 1-4.
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