Semiconductor structure and preparation method thereof, memory and memory system

Abstract

The embodiment of the invention provides a semiconductor structure, a preparation method of the semiconductor structure, a memory and a memory system, and the semiconductor structure comprises a first stacking structure which comprises first insulating layers and gate layers which are alternately stacked; the multiple first isolation structures penetrate through the first stacking structure in the stacking direction of the first stacking structure, extend in the first direction and are arranged at intervals in the first direction; the supporting structures are located between the adjacent first isolation structures in the first direction, and part of the first stacking structures are located between the first isolation structures and the supporting structures; wherein the first direction intersects with the stacking direction.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to semiconductor structures, methods for fabricating semiconductor structures, memories, and memory systems. Background Technology

[0002] Memory is one of the most important components in electronic systems. Flash memory is an important type of memory. Flash memory (also known as flash storage) is characterized by its ability to retain stored information for extended periods without power, and it boasts advantages such as high integration density, fast access speed, and ease of erasing and rewriting, making it the mainstream non-volatile memory. Based on its structure, flash memory is divided into NOR flash memory and NAND flash memory. Compared to NOR flash memory, NAND flash memory offers higher cell density, achieving higher storage density, and also provides faster write and erase speeds. With significant advancements in semiconductor manufacturing processes, three-dimensional (3D) flash memory, such as 3D NAND flash memory, has emerged to pursue lower production costs per unit of storage cell.

[0003] However, the performance of semiconductor structures, taking memory as an example, needs to be improved. Summary of the Invention

[0004] This application provides semiconductor structures, methods for fabricating semiconductor structures, memories, and memory systems that can at least partially solve the problems described above or other problems in the art.

[0005] This application provides a semiconductor structure, including: a first stacked structure including alternating layers of a first insulating layer and a gate layer; a plurality of first isolation structures extending through the first stacked structure along the stacking direction of the first stacked structure, extending along a first direction and spaced apart along the first direction; and a support structure located between adjacent first isolation structures along the first direction, with a portion of the first stacked structure located between the first isolation structure and the support structure; wherein the first direction intersects the stacking direction.

[0006] In some embodiments, the semiconductor structure further includes a channel structure located in a first stacked structure on the side of the support structure along the second direction; wherein the structure of the support structure and the structure of the channel structure are identical; wherein the second direction intersects the first direction and the stacking direction, respectively.

[0007] In some embodiments, the support structure includes a first functional layer and a first channel layer extending along the stacking direction, wherein the first functional layer is located between the first channel layer and the gate layer.

[0008] In some implementations, the material of the support structure is an insulating dielectric material.

[0009] In some embodiments, the number of supporting structures between adjacent first isolation structures is one; or, the number of supporting structures between adjacent first isolation structures is multiple.

[0010] In some embodiments, the semiconductor structure further includes a first channel structure and a second channel structure; wherein, a plurality of first channel structures are respectively located in first stacked structures on both sides of the first isolation structure along the second direction and are adjacent to the first isolation structure, and the second channel structure is located in a first stacked structure on the side of the first channel structure away from the first isolation structure; wherein, along the first direction, the size of the first channel structure is smaller than the size of the second channel structure, and along the second direction, the size of the first channel structure is larger than the size of the second channel structure; wherein, the second direction intersects the first direction and the stacking direction respectively.

[0011] In some embodiments, the size of the support structure is smaller than the size of the second channel structure along the first direction, and the size of the support structure is larger than the size of the second channel structure along the second direction.

[0012] In some embodiments, the size of the support structure is larger than the size of the first channel structure along the first direction, and the size of the support structure is smaller than the size of the first channel structure along the second direction.

[0013] In some embodiments, along the first direction, the spacing between adjacent first channel structures is greater than the spacing between adjacent second channel structures.

[0014] In some embodiments, the spacing between the first channel structures on both sides of the first isolation structure along the second direction is greater than the spacing between adjacent first isolation structures.

[0015] In some embodiments, the semiconductor structure further includes a channel structure that extends through the first stacked structure; and a top selection gate located on one side of the first stacked structure, the support structure, and the channel structure along the stacking direction; wherein the first isolation structure also extends through the top selection gate.

[0016] In some implementations, the portion of the first isolation structure that penetrates the top selection gate also extends to one side of a portion of the first stack structure along the stacking direction.

[0017] In some embodiments, the semiconductor structure further includes a first connection structure extending through the top select gate, the first connection structure including a first conductive connection layer and a first isolation layer, the first conductive connection layer connecting the channel structure, and the first isolation layer located between the first conductive connection layer and the top select gate.

[0018] In some embodiments, the semiconductor structure further includes a first contact structure located on the side of the top select gate opposite to the first stacked structure and connected to the top select gate.

[0019] In some embodiments, the semiconductor structure further includes a second isolation layer and a dielectric layer, wherein the second isolation layer is located on the side of the top select gate opposite to the first stacked structure, and the dielectric layer is located on the side of the second isolation layer opposite to the top select gate; wherein the material of the second isolation layer is different from the material of the dielectric layer and the material of the top select gate; wherein the first contact structure is located in the dielectric layer and penetrates the second isolation layer.

[0020] In some embodiments, the semiconductor structure further includes a second isolation structure located on the side of the first isolation structure along a second direction and extending through the first stacked structure and the top select gate; wherein, along the first direction, the second isolation structure extends by a larger dimension than the first isolation structure extends; wherein, the second direction intersects the first direction and the stacking direction, respectively.

[0021] In some embodiments, the first stacked structure includes a first portion of a first insulating layer; the semiconductor structure further includes a second stacked structure, the second stacked structure including a second portion of the alternating first insulating layer and a second insulating layer; wherein a second isolation structure extends along a first direction into a portion of the first stacked structure located on the side of the second stacked structure along a second direction; wherein the semiconductor structure further includes a second contact structure located in the second stacked structure and connected to a portion of the gate layer located between the second isolation structure and the second stacked structure.

[0022] This application also provides a method for fabricating a semiconductor structure, comprising: forming a first stacked structure, the first stacked structure including alternating layers of a first insulating layer and a gate layer; forming a plurality of first isolation structures, the plurality of first isolation structures extending through the first stacked structure along the stacking direction of the first stacked structure, extending along a first direction and being spaced apart along the first direction; and forming a support structure, the support structure being located between adjacent first isolation structures along the first direction, and a portion of the first stacked structure being located between the first isolation structure and the support structure; wherein the first direction intersects the stacking direction.

[0023] In some embodiments, forming a first stacked structure includes: forming an initial stacked structure, the initial stacked structure including alternating layers of first insulating layers and second insulating layers; replacing at least a portion of the second insulating layers with gate layers to form the first stacked structure; wherein forming a plurality of first isolation structures includes: forming a plurality of first isolation trenches extending through the initial stacked structure along the stacking direction of the initial stacked structure, the plurality of first isolation trenches extending along a first direction and spaced apart along the first direction; and after replacing at least a portion of the second insulating layers with gate layers, forming the first isolation structures in the first isolation trenches; wherein replacing at least a portion of the second insulating layers with gate layers includes: replacing at least a portion of the second insulating layers with gate layers via the first isolation trenches; wherein forming a support structure includes: before forming the first isolation trenches, forming a support structure extending through the initial stacked structure along the stacking direction of the initial stacked structure; the support structure is located between adjacent first isolation trenches along the first direction.

[0024] In some embodiments, the preparation method further includes: forming a channel structure located in a first stacked structure on the side of the support structure along the second direction; wherein the structure of the support structure and the structure of the channel structure are the same; wherein the second direction intersects the first direction and the stacking direction respectively.

[0025] In some implementations, the material forming the support structure is an insulating dielectric material.

[0026] In some embodiments, the number of supporting structures between adjacent first isolation structures along the first direction is one, or the number of supporting structures between adjacent first isolation structures along the first direction is multiple.

[0027] In some embodiments, the preparation method further includes: before forming the first isolation trench, forming a first channel structure and a second channel structure that both penetrate the initial stacked structure; wherein, a plurality of first channel structures are respectively located on both sides of the first isolation structure along a second direction and adjacent to the first isolation structure, and the second channel structure is located on the side of the first channel structure away from the first isolation structure; wherein, along the first direction, the size of the first channel structure is smaller than the size of the second channel structure, and along the second direction, the size of the first channel structure is larger than the size of the second channel structure; wherein, the second direction intersects the first direction and the stacking direction respectively.

[0028] In some embodiments, the size of the support structure is smaller than the size of the second channel structure along the first direction, and larger than the size of the second channel structure along the second direction; or, the size of the support structure is larger than the size of the first channel structure along the first direction, and smaller than the size of the first channel structure along the second direction.

[0029] In some embodiments, the fabrication method further includes: forming a channel structure that penetrates the initial stacked structure along the stacking direction; and forming a top selection gate on one side of the initial stacked structure, the support structure, and the channel structure along the stacking direction; wherein forming a plurality of first isolation grooves that penetrate the initial stacked structure along the stacking direction includes: forming first isolation grooves that penetrate the initial stacked structure and the top selection gate along the stacking direction on both sides of the support structure along the first direction.

[0030] In some embodiments, the fabrication method further includes: forming a first connection structure penetrating the top selection gate, including: forming a first opening penetrating the top selection gate; forming a first isolation layer on the sidewall of the first opening; and forming a first conductive connection layer in the first opening to form a connection channel structure; wherein the first isolation layer is located between the first conductive connection layer and the top selection gate.

[0031] In some embodiments, the fabrication method further includes forming a first contact structure for connecting the top selection gate on the side of the top selection gate away from the first insulating layer.

[0032] In some embodiments, the fabrication method further includes: forming a second isolation layer on the surface of the top select gate away from the initial stacked structure; forming a dielectric layer on the side of the second isolation layer away from the top select gate; wherein the material of the second isolation layer is different from the material of the dielectric layer and the material of the top select gate; wherein forming a first contact structure connecting the top select gate on the side of the top select gate away from the first insulating layer includes: forming the first contact structure in the dielectric layer and the second isolation layer.

[0033] In some embodiments, the fabrication method further includes: forming a second isolation trench extending through the initial stacked structure and the top selection gate along the stacking direction, wherein the second isolation trench is located on the side of the first isolation trench along the second direction; and forming a second isolation structure in the second isolation trench, the second isolation structure extending along the first direction having a larger dimension than the first isolation structure extending along the first direction, wherein at least a portion of the second insulating layer is also replaced by a gate layer via the second isolation trench; wherein the second direction intersects the first direction and the stacking direction, respectively.

[0034] In some embodiments, the first stacked structure includes a first portion of a first insulating layer; wherein, after a portion of the second insulating layer is replaced with a gate layer, the initial stacked structure further forms a second stacked structure, the second stacked structure including: a second portion of the alternating first insulating layer and a second insulating layer; wherein the formed second isolation structure extends along a first direction into a portion of the first stacked structure located on the side of the second stacked structure along a second direction; wherein the fabrication method further includes: forming a second contact structure in the second stacked portion, the second contact structure being connected to a portion of the gate layer located between the second isolation structure and the second stacked structure.

[0035] Another aspect of this application provides a memory, including: a memory cell array, including peripheral circuitry and a semiconductor structure as mentioned in any of the embodiments above; the peripheral circuitry is coupled to the memory cell array.

[0036] In another aspect, this application provides a memory system including a controller and a memory as mentioned in any of the embodiments described above, wherein the controller is coupled to the memory and is used to control the memory to store data. Attached Figure Description

[0037] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0038] Figure 1 It is a top view of a semiconductor structure;

[0039] Figure 2 It is along Figure 1 Cross-sectional view obtained by the cutting line A-A1 in the middle;

[0040] Figure 3 This is a partial top view of a semiconductor structure according to an exemplary embodiment of this application;

[0041] Figure 4 This is another partial top view of a semiconductor structure according to an exemplary embodiment of this application;

[0042] Figure 5 For along Figure 3 Cross-sectional view obtained from the cutting line MN in the middle;

[0043] Figure 6 and Figure 7 This is a top view of a semiconductor structure according to an exemplary embodiment of this application;

[0044] Figure 8 For along Figure 6 Cross-sectional views obtained by cutting lines M1-N1 and M2-N2;

[0045] Figure 9 This is a flowchart of a method for fabricating a semiconductor structure according to one embodiment of this application;

[0046] Figures 10 to 30 This is a schematic diagram of the fabrication process of a semiconductor structure according to one embodiment of this application;

[0047] Figure 31 A schematic diagram of a memory according to one embodiment of this application; and

[0048] Figure 32This is a schematic diagram of a memory system according to one embodiment of the present application. Detailed Implementation

[0049] Reference Figure 1 and Figure 2 A semiconductor structure is shown, comprising a stacked structure, a plurality of isolation structures 10, and a channel structure 20. The stacked structure includes alternately stacked insulating layers 31 and gate layers 30. The isolation structures 10 extend through the stacked structure along the stacking direction Z, extend along a first direction X, and are spaced apart along the first direction X, which intersects the stacking direction.

[0050] In this semiconductor structure, as the storage density of the semiconductor structure continuously increases, the number of stacked layers in the stacked structure needs to continuously increase, and the dimension of the insulating layer 31 along the stacking direction needs to continuously decrease. Secondly, as the number of stacked layers in the stacked structure needs to continuously increase, the dimension of the isolation structure 10 along the second direction Y needs to increase to ensure the positional stability of the isolation structure 10. Furthermore, the isolation structure 10 and the channel structure 20 also need to be spaced a certain distance apart in the second direction Y to reduce the risk of contact between the isolation structure 10 and the channel structure 20. This leads to an increase in the distance L1 between the channel structures adjacent to the isolation structure 10 on both sides of the second direction Y, making the insulating layer 31 prone to collapse between adjacent isolation structures 10. The gate layer 30 in some layers may not be adequately filled between adjacent insulating layers 31, and the first portion of the gate layer 30 located between adjacent isolation structures 10 and the second portion located on both sides of the isolation structure 10 along the second direction may easily break, making it difficult to control the gate layer 30 in the second portion on both sides of the isolation structure 10 along the second direction.

[0051] This application provides a semiconductor structure that reduces the risk of collapse of the first insulating layer between adjacent first isolation structures along a first direction, and the gate layer can be better filled between adjacent first insulating layers.

[0052] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0053] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence.

[0054] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0055] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0056] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0057] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0058] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or can be inferred from the context.

[0059] This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0060] This application provides a semiconductor structure in some embodiments. Figure 3 This is a partial top view of a semiconductor structure according to an exemplary embodiment of this application. Figure 4 This is another partial top view of a semiconductor structure according to an exemplary embodiment of this application. Figure 5 For along Figure 3 The cross-sectional view obtained by the cutting line MN. Figure 6 and Figure 7 This is a top view of a semiconductor structure according to an exemplary embodiment of this application. Figure 8 For along Figure 6 The cross-sectional views obtained by cutting lines M1-N1 and M2-N2, wherein, Figure 8 The diagram of the left-hand area is along Figure 6 The cross-sectional view obtained by the tangent line M2-N2. Figure 8 The diagram of the right-hand area is along Figure 6 The cross-sectional view obtained by the cutting line M1-N1.

[0061] It should be noted that, Figure 5 For along Figure 3 The cross-sectional view obtained by the cutting line MN. To clearly illustrate the positional relationship between the gate layer 211, the channel structure 220, the first isolation structure 240, and the support structure 230, Figure 3 The top selection gate 260, the second isolation layer 270, the first dielectric layer 280, and the second dielectric layer 290 are not shown in the diagram. Figure 5 The diagram illustrates the top selection gate 260, the second isolation layer 270, the first dielectric layer 280, and the second dielectric layer 290.

[0062] It should be noted that, Figure 8 For along Figure 6 The cross-sectional views obtained by cutting lines M1-N1 and M2-N2 are shown. To clearly illustrate the positional relationships of the channel structure 220, the first isolation structure 240, the support structure 230, the third channel structure 310, and the second isolation structure 300, the substrate layer 100, the top select gate 260, the second isolation layer 270, the dielectric layer 400, the fourth insulating layer 281, the first connection structure 500, and the first contact structure 510 are not shown schematically. Figure 8 The substrate layer 100, the top selection gate 260, the second isolation layer 270, the dielectric layer 400, the fourth insulating layer 281, the first connection structure 500, and the first contact structure 510 are illustrated.

[0063] Reference Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 The semiconductor structure includes: a first stacked structure D1 (reference). Figure 5 and Figure 7 ), multiple first isolation structures 240 and support structures 230.

[0064] refer to Figure 5 and Figure 8The first stacked structure D1 includes an alternately stacked first insulating layer 212 and a gate layer 211.

[0065] Reference Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 Multiple first isolation structures 240 extend through the first stacking structure D1 along the stacking direction Z, extend along the first direction X, and are spaced apart along the first direction X. Support structures 230 are located between adjacent first isolation structures 240 along the first direction X, and a portion of the first stacking structure D1 is located between the first isolation structures 240 and the support structures 230.

[0066] The first direction X intersects the stacking direction Z.

[0067] In at least one embodiment of this application, the semiconductor structure includes a support structure 230 located between adjacent first isolation structures 240 along the first direction X, and a portion of the first stacked structure D1 is located between the first isolation structure 240 and the support structure 230. The support structure 230 penetrates the first insulating layer 212 and the gate layer 211 along the stacking direction Z. The support structure 230 can support the first insulating layer 212 and the gate layer 211 between adjacent first isolation structures 240 along the first direction X, reducing the risk of collapse of the first insulating layer 212 between adjacent first isolation structures 240 along the first direction X. Therefore, the gate layer 211 can be better filled between adjacent first insulating layers 212.

[0068] In some implementations, in conjunction with reference Figure 5 and Figure 8 The first stacked structure D1 includes a first portion 212-1 of a first insulating layer 212, in which the first portion 212-1 and the gate layer 211 are alternately stacked.

[0069] In some embodiments, the material of the gate layer 211 includes any one of a metal gate material and a polysilicon gate material. For example, the material of the gate layer 211 can be any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicides.

[0070] In some implementations, reference Figure 8 The semiconductor structure also includes a second stacked structure D2, comprising a second portion 212-2 of an alternately stacked first insulating layer 212 and a second insulating layer 213.

[0071] In some embodiments, the material of the first insulating layer 212 includes, but is not limited to, insulating dielectric materials such as silicon oxide. The material of the second insulating layer 213 includes, but is not limited to, insulating dielectric materials such as silicon nitride. The materials of the first insulating layer 212 and the second insulating layer 213 are different.

[0072] Furthermore, the number of layers in the first insulating layer 212 and the number of layers in the gate layer 211 are not limited to... Figure 5 and Figure 8 The number of layers shown, the number of layers in the second insulating layer 213 is not limited to Figure 8 The number of layers shown can be set as needed. The number of layers in the first stack structure D1 is not limited to... Figure 5 and Figure 8 The number of layers shown is not limited to the number of layers in the second stacked structure D2. Figure 8 The number of layers shown can be set separately as needed.

[0073] The semiconductor structure can be a memory cell array, or it can be a part of a memory cell array. Memory cell arrays include 3D NAND flash memory.

[0074] Furthermore, as the demand for storage capacity in semiconductor structures continues to increase, the number of stacked layers in the first stacked structure D1 and the second stacked structure D2 gradually increases. The first stacked structure D1 and the second stacked structure D2 may include multiple sub-stacked structures formed using techniques such as dual-stack or multi-stack. The number of stacked layers in each sub-stacked structure may be the same or different. The first stacked structure D1 and the second stacked structure D2 described below are applicable, in whole or in part, to structures composed of multiple sub-stacked structures; therefore, related or similar content will not be repeated.

[0075] In some implementations, reference Figure 5 and Figure 8 The semiconductor structure also includes a substrate layer 100. The first stacked structure D1 and the second stacked structure D2 are located on one side of the substrate layer 100 along the stacking direction Z.

[0076] In some implementations, reference Figure 5 and Figure 8The substrate layer 100 includes a substrate semiconductor layer, a substrate dielectric layer 102, an interconnect layer 103, and contact structures. The substrate semiconductor layer includes a first semiconductor layer 106 and a second semiconductor layer 101, with the second semiconductor layer 101 located on the side of the first semiconductor layer 106 opposite to the first stacked structure D1 and the second stacked structure D2. The substrate dielectric layer 102 is located on the side of the second semiconductor layer 101 opposite to the first semiconductor layer 106. The interconnect layer 103 is located on the side of the substrate dielectric layer 102 opposite to the second semiconductor layer 101. The contact structures are located in the substrate dielectric layer 102 and a portion of the second semiconductor layer 101, and are connected to the interconnect layer 103.

[0077] The substrate semiconductor layer may be made of at least one of monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. The substrate dielectric layer 102 may be made of an insulating dielectric material such as silicon oxide. The interconnect layer 103 may be made of a metallic material.

[0078] In some embodiments, the contact structure may include a conductive layer 105 and an adhesive layer 104 surrounding the conductive layer 105. In other words, the adhesive layer 104 may at least surround the sidewalls of the conductive layer 105. The adhesive layer 104 may surround the sidewalls of the conductive layer 105 and the side surface of the conductive layer 105 facing the first stacked structure D1 and the second stacked structure D2. The material of the conductive layer 105 includes any one or a combination of several of tungsten, cobalt, copper, and aluminum. Furthermore, the material of the conductive layer 105 may also include semiconductor materials such as crystalline silicon or alloy materials such as silicides. The material of the adhesive layer 104 includes at least one of titanium (Ti) and titanium nitride (TiN).

[0079] In other embodiments, the substrate layer includes a substrate dielectric layer and a substrate semiconductor layer, the substrate semiconductor layer being located between the substrate dielectric layer and the first stacked structure D12 and between the substrate dielectric layer and the second stacked structure D2.

[0080] It should be noted that the structure of the substrate is not limited to the structures listed above; the substrate can also be other suitable structures.

[0081] Reference Figure 5 and Figure 7 Multiple first isolation structures 240 extend through the first stacking structure D1 along the stacking direction Z, extend along the first direction X, and are spaced apart along the first direction X. For example, the dimension of the first isolation structure 240 along the first direction X is larger than the dimension of the first isolation structure 240 along the second direction Y.

[0082] The second direction Y intersects both the first direction X and the stacking direction Z. For example, the first direction X is perpendicular to the stacking direction Z, and the second direction Y is perpendicular to both the stacking direction Z and the first direction X.

[0083] In some implementations, reference Figure 5 The first isolation structure 240 includes a first insulating isolation layer 241 and a first semiconductor isolation layer 242. The first insulating isolation layer 241 is located on the sidewall of the first semiconductor isolation layer 242 and on the side of the first semiconductor isolation layer 242 facing the substrate layer 100 in the direction opposite to the stacking direction Z.

[0084] In some embodiments, a portion of the first insulating structure 240 may extend between adjacent first insulating layers 212 and be disposed opposite to the first insulating layer 212 in the stacking direction Z. For example, a portion of the first insulating insulating layer 241 may extend between first portions 212-1 of adjacent first insulating layers 212 and be disposed opposite to the first portions 212-1 in the stacking direction Z.

[0085] In some embodiments, the material of the first semiconductor isolation layer 242 includes polycrystalline silicon or doped polycrystalline silicon. The material of the first insulating isolation layer 241 includes, but is not limited to, insulating dielectric materials such as silicon oxide layers.

[0086] In other embodiments, the material of the first isolation structure 240 is an insulating dielectric material.

[0087] The gate layer 211 between adjacent first isolation structures 240 along the first direction X is connected to the gate layers 211 on both sides of the first isolation structure 240 in the second direction Y, so that the gate layers 211 on both sides of the first isolation structure 240 in the second direction Y can be controlled together, without the need to control the gate layers 211 on both sides of the first isolation structure 240 in the second direction Y separately.

[0088] In some implementations, reference Figure 3 , Figure 4 and Figure 6 The semiconductor structure also includes a channel structure 220 located in the first stacked structure D1 along the second direction Y side of the support structure 230. The channel structure 220 extends through the first stacked structure D1.

[0089] In some implementations, the number of channel structures 220 is multiple.

[0090] In some embodiments, the structure of the support structure 230 is the same as that of the channel structure 220.

[0091] In some implementations, reference Figure 5 The support structure 230 includes a first functional layer 231 and a first channel layer 232 extending along the stacking direction Z, with the first functional layer 231 located between the first channel layer 232 and the gate layer 211. The support structure 230 may further include a first channel plug and a first filling dielectric layer 233. The first channel layer 232 is located between the first functional layer 231 and the first filling dielectric layer 233, and the first channel plug is located on one side of the first filling dielectric layer 233 along the stacking direction Z, connected to the first channel layer 232. For example, the first channel plug is located on the side of the first filling dielectric layer 233 along the stacking direction Z opposite to the substrate layer 100.

[0092] In some embodiments, the first functional layer 231 includes a first barrier layer, a first charge trapping layer, and a first tunneling layer. The first barrier layer, the first charge trapping layer, and the first tunneling layer all extend along the stacking direction Z. The first charge trapping layer is located between the first barrier layer and the first tunneling layer, and the first tunneling layer is located between the first charge trapping layer and the first channel layer.

[0093] In some embodiments, the channel structure 220 includes a second channel layer and a second functional layer extending along the stacking direction Z, the second functional layer being located between the second channel layer and the gate layer 211. The channel structure 220 also includes a second channel plug and a second filling dielectric layer. The second channel layer is located between the second functional layer and the second filling dielectric layer, and the second channel plug is located on one side of the second filling dielectric layer along the stacking direction Z, connected to the second channel layer. Exemplarily, the second channel plug is located on the side of the second filling dielectric layer along the stacking direction Z opposite to the substrate layer 100.

[0094] In some embodiments, the second functional layer includes a second barrier layer, a second charge trapping layer, and a second tunneling layer. The second barrier layer, the second charge trapping layer, and the second tunneling layer all extend along the stacking direction Z. The second charge trapping layer is located between the second barrier layer and the second tunneling layer, and the second tunneling layer is located between the second charge trapping layer and the second channel layer.

[0095] For example, the first channel layer 232 and the second channel layer may be N-type doped or P-type doped polycrystalline silicon layers. The materials of the first barrier layer and the second barrier layer may include silicon oxide. The materials of the first charge trapping layer and the second charge trapping layer may include silicon nitride. The materials of the first tunneling layer and the second tunneling layer may include silicon oxide. The materials of the first filling dielectric layer 233 and the second filling dielectric layer include, but are not limited to, insulating dielectric materials such as silicon oxide layers. The interior of the first filling dielectric layer 233 may include voids. The interior of the second filling dielectric layer may include voids.

[0096] In some embodiments, a portion of the channel structure 220 extends into the substrate layer 100, and a portion of the second channel layer extends into the substrate layer 100. The channel structure 220 extends into the substrate semiconductor layer and the substrate dielectric layer, and a portion of the second channel layer contacts the substrate semiconductor layer. For example, a portion of the second channel layer extends into and contacts the second semiconductor layer 101.

[0097] In other embodiments, the support structure is made of an insulating dielectric material. For example, the support structure may be made of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0098] In some implementations, reference Figure 5 and Figure 8 The semiconductor structure also includes a gate dielectric layer 214, which is located at least between the gate layer 211 and the second channel layer. For example, the gate dielectric layer 214 is located between the gate layer 211 and the second channel layer, and between the gate layer 211 and the first insulating layer 212.

[0099] In some embodiments, the gate dielectric layer 214 may be a high-k (dielectric constant) dielectric material, where k may be greater than 3.9. The material of the gate dielectric layer 214 may include any one of alumina, hafnium dioxide, zirconium dioxide, lanthanum oxide, and titanium oxide.

[0100] In some implementations, reference Figure 3 and Figure 4 The channel structure 220 includes a first channel structure 221 and a second channel structure 222. The channel structure 220 including a first channel structure 221 and a second channel structure 222 means that a portion of the channel structures 220 are the first channel structure 221 and a portion of the channel structures 220 are the second channel structure 222.

[0101] In some embodiments, a plurality of first channel structures 221 are located in the first stacked structure D1 on the side of the first isolation structure 240 along the second direction Y and are adjacent to the first isolation structure 240, and the second channel structure 222 is located in the first stacked structure D1 on the side of the first channel structure 221 away from the first isolation structure 240.

[0102] In some embodiments, the spacing between the first channel structures 221 on both sides of the first isolation structure 240 along the second direction Y is greater than the spacing between adjacent first isolation structures 240 along the first direction X.

[0103] In some implementations, reference Figure 3Along the first direction X, the dimension of the first channel structure 221 is smaller than the dimension of the second channel structure 222, and along the second direction Y, the dimension of the first channel structure 221 is larger than the dimension of the second channel structure 222. Along the first direction X, the dimension of the support structure 230 is smaller than the dimension of the second channel structure 222, and along the second direction Y, the dimension of the support structure 230 is larger than the dimension of the second channel structure 222. The dimension of the support structure 230 along the first direction X can be similar to or the same as the dimension of the first channel structure 221 along the first direction X. The dimension of the support structure 230 along the second direction Y can be similar to or the same as the dimension of the first channel structure 221 along the second direction Y.

[0104] In other embodiments, reference is made to Figure 4 Along the first direction X, the dimension of the first channel structure 221 is smaller than the dimension of the second channel structure 222, and along the second direction Y, the dimension of the first channel structure 221 is larger than the dimension of the second channel structure 222. Along the first direction X, the dimension of the support structure 230 is larger than the dimension of the first channel structure 221, and along the second direction Y, the dimension of the support structure 230 is smaller than the dimension of the first channel structure 221. The dimension of the support structure 230 along the first direction X can be selected to be similar to or the same as the dimension of the second channel structure 222 along the first direction X. The dimension of the support structure 230 along the second direction Y can be selected to be similar to or the same as the dimension of the second channel structure 222 along the second direction Y.

[0105] In some implementations, such as Figure 3 The number of support structures 230 between adjacent first isolation structures 240 can be one. For example... Figure 4 In this example, the number of supporting structures 230 between adjacent first isolation structures 240 can be two. It should be noted that there is no limit to the number of supporting structures 230 between adjacent first isolation structures 240, and it can be adjusted according to actual needs.

[0106] In some embodiments, along the first direction X, the spacing between adjacent first channel structures 221 is greater than the spacing between adjacent second channel structures 222, which is beneficial for filling the gate layer 211.

[0107] In other embodiments, there is no limitation on the relationship between the spacing distance between adjacent first channel structures 221 along the first direction X and the spacing distance between adjacent second channel structures 222 along the first direction X.

[0108] In other embodiments, the dimension of the first channel structure 221 along the first direction X may be greater than or equal to the dimension of the second channel structure 222 along the first direction X. The dimension of the first channel structure 221 along the second direction Y may be less than or equal to the dimension of the second channel structure 222 along the second direction Y.

[0109] In some implementations, in conjunction with reference Figure 5 and Figure 8 The semiconductor structure also includes a top select gate 260, which is located on one side of the first stacked structure D1, the support structure 230, and the channel structure 220 along the stacking direction Z. The first isolation structure 240 also extends through the top select gate 260.

[0110] In some embodiments, the material of the top select gate 260 includes any one of a metal gate material and a polysilicon gate material. For example, the material of the top select gate 260 can be any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicides.

[0111] In some embodiments, the portion of the first isolation structure 240 that penetrates the top selection gate 260 also extends to one side of the portion of the first stacked structure D1 along the stacking direction Z. Exemplarily, a portion of the first insulating isolation layer 241 also extends to one side of the portion of the first stacked structure D1 along the stacking direction Z.

[0112] In some implementations, reference Figure 8 The semiconductor structure also includes a first connection structure 500 extending through the top select gate 260. The first connection structure 500 may include a first isolation layer 501 and a first conductive connection layer 502. The first conductive connection layer 502 connects to the channel structure 220; exemplarily, the first conductive connection layer 502 connects to the channel plug. The first isolation layer 501 is located between the first conductive connection layer 502 and the top select gate 260.

[0113] In other embodiments, the first connection structure may include a first isolation layer, a first conductive connection layer, and a first filler portion, wherein the first isolation layer is located between the first conductive connection layer and the top selection gate, and the first conductive connection layer is located on the sidewall of the first filler portion and on the side surface of the first filler portion facing the channel structure.

[0114] In some embodiments, the material of the first conductive connection layer 502 includes any one or a combination of several of tungsten, cobalt, copper, and aluminum. Furthermore, the material of the first conductive connection layer 502 may also include semiconductor materials such as crystalline silicon or alloy materials such as silicides. The material of the first insulating layer 501 may be an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The material of the first filling portion may be an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0115] In some implementations, reference Figure 8 The semiconductor structure also includes a first contact structure 510, which is located on the side of the top select gate 260 away from the first stacked structure D1 and is connected to the top select gate 260.

[0116] In some embodiments, the first contact structure 510 may include a first conductive layer (not shown) and a first adhesive layer (not shown) surrounding the first conductive layer. In other words, the first adhesive layer may at least surround the sidewalls of the first conductive layer. The first adhesive layer may surround the sidewalls of the first conductive layer and the side surface of the first conductive layer facing the top selection gate 260. The material of the first conductive layer includes any one or a combination of several of tungsten, cobalt, copper, and aluminum. Furthermore, the material of the first conductive layer may also include semiconductor materials such as crystalline silicon or alloy materials such as silicides. The material of the first adhesive layer includes at least one of titanium (Ti) and titanium nitride (TiN).

[0117] In some implementations, reference Figure 8 The semiconductor structure also includes a second isolation layer 270 and a dielectric layer 400. The second isolation layer 270 is located on the side of the top select gate 260 opposite to the first stacked structure D1. The dielectric layer 400 is located on the side of the second isolation layer 270 opposite to the top select gate 260.

[0118] In some embodiments, the material of the second isolation layer 270 is different from the materials of the dielectric layer 400 and the top select gate 260, respectively. The first contact structure 510 is located in the dielectric layer 400 and extends through the second isolation layer 270. During the formation of the first contact hole accommodating the first contact structure 510, the etching rate of the second isolation layer 270 is lower than the etching rate of the dielectric layer 400, thereby reducing over-etching and reducing etching loss on the top select gate 260.

[0119] In some embodiments, the material of the second insulating layer 270 includes an insulating dielectric material such as silicon nitride. The material of the dielectric layer 400 includes an insulating dielectric material such as silicon oxide.

[0120] It should be noted that in other embodiments, the semiconductor structure may not include a second isolation layer.

[0121] In some implementations, reference Figure 8 The dielectric layer 400 includes a first dielectric layer 280 and a second dielectric layer 290, with the second dielectric layer 290 located on the side of the first dielectric layer 280 away from the first stacked structure D1.

[0122] In some implementations, in conjunction with reference Figure 6 , Figure 7 and Figure 8The semiconductor structure also includes a second isolation structure 300, which is located on the side of the first isolation structure 240 along the second direction Y and extends through the first stacked structure D1 and the top selection gate 260.

[0123] In some embodiments, the second isolation structure 300 extends in a larger dimension than the first isolation structure 240 along the first direction X.

[0124] In some embodiments, the second isolation structure 300 extends along the first direction X into the portion of the first stacked structure D1 located on the side of the second stacked structure D2 along the second direction Y.

[0125] In some implementations, in conjunction with reference Figure 6 , Figure 7 and Figure 8 The second isolation structure 300 includes a first isolation portion 300a and a second isolation portion 300b. The first isolation portion 300a is located on the side of the first isolation structure 240 along the second direction Y. The second isolation portion 300b is located in the first stacked structure D1 on the side of the second stacked structure D2 along the second direction Y.

[0126] The first isolation section 300a extends through the first stacked structure D1 and the top selection gate 260.

[0127] In some implementations, reference Figure 8 The first isolation portion 300a includes a first insulating isolation portion 301a and a first semiconductor isolation portion 302a. The first insulating isolation portion 301a is located on the sidewall of the first semiconductor isolation portion 302a and on the side of the first semiconductor isolation portion 302a facing the substrate layer 100 in the direction opposite to the stacking direction Z. The second isolation portion 300b includes a second insulating isolation portion 301b and a second semiconductor isolation portion 302b. The second insulating isolation portion 301b is located on the sidewall of the second semiconductor isolation portion 302b and on the side of the second semiconductor isolation portion 302b facing the substrate layer 100 in the direction opposite to the stacking direction Z.

[0128] In some embodiments, a portion of the first insulating isolation portion 300a may extend between adjacent first insulating layers 212 and be disposed opposite to the first insulating layer 212 in the stacking direction Z. For example, a portion of the first insulating isolation portion 301a may extend between first portions 212-1 of adjacent first insulating layers 212 and be disposed opposite to the first portions 212-1 in the stacking direction Z.

[0129] In some embodiments, a portion of the second insulating isolation portion 300b may extend between adjacent first insulating layers 212 and be disposed opposite to the first insulating layer 212 in the stacking direction Z. For example, a portion of the second insulating isolation portion 301b may extend between first portions 212-1 of adjacent first insulating layers 212 and be disposed opposite to the first portions 212-1 in the stacking direction Z.

[0130] In some embodiments, the materials of the first semiconductor isolation portion 302a and the second semiconductor isolation portion 302b include polycrystalline silicon or doped polycrystalline silicon. The materials of the first insulating isolation portion 301a and the second insulating isolation portion 301b include, but are not limited to, insulating dielectric materials such as silicon oxide layers.

[0131] In other embodiments, the material of the first isolation portion 300a is an insulating dielectric material. The material of the second isolation portion 300b is an insulating dielectric material.

[0132] In some embodiments, the dimension of the second isolation portion 300b along the second direction Y is equal to the dimension of the first isolation portion 300a along the second direction Y.

[0133] In other embodiments, the dimension of the second isolation portion 300b along the second direction Y is not equal to the dimension of the first isolation portion 300a along the second direction Y. For example, the dimension of the second isolation portion 300b along the second direction Y is greater than the dimension of the first isolation portion 300a along the second direction Y.

[0134] In some implementations, in conjunction with reference Figure 6 , Figure 7 and Figure 8 The semiconductor structure also includes a second contact structure 320, which is located in the second stacked structure D2 and is connected to the portion of the gate layer 211 located between the second isolation structure 300 and the second stacked structure D2.

[0135] In some implementations, reference Figure 8The second contact structure 320 includes a second conductive layer 322, a second filling portion 323, and a third isolation layer 321. A first portion of the second conductive layer 322 extends along the stacking direction Z and is located on the sidewall of the second filling portion 323. A second portion of the second conductive layer 322 extends along the second direction Y, is located on the side of the second filling portion 323 facing the substrate layer 100, and is connected to a gate layer 211 having the same height as the second conductive layer 322 in the stacking direction Z. A third portion of the second conductive layer 322 is located on the side of the second filling portion 323 facing away from the substrate layer 100. The third isolation layer 321 is located between the first portion of the second conductive layer 322 and the second portion 212-2 of the first insulating layer 212, and between the first portion of the second conductive layer 322 and the second insulating layer 213.

[0136] In some embodiments, the material of the second conductive layer 322 includes any one or a combination of several of tungsten, cobalt, copper, and aluminum. Alternatively, the material of the second conductive layer 322 may also include semiconductor materials such as crystalline silicon or alloy materials such as silicides. The material of the second filler portion 323 includes an insulating dielectric material such as silicon oxide. The material of the third insulating layer 321 includes an insulating dielectric material such as silicon oxide.

[0137] In some implementations, reference Figure 6 The semiconductor structure also includes a third channel structure 310, which is located between the second contact structure 320 and the second isolation portion 300b. The third channel structure 310 can be a virtual channel structure.

[0138] In some embodiments, the channel structure 220, the third channel structure 310, and the support structure 230 further extend into the substrate layer 100.

[0139] In some implementations, reference Figure 5 and Figure 8 The semiconductor structure also includes a third insulating layer 250 and a fourth insulating layer 281. The fourth insulating layer 281 is located on the side of the second stacked structure D2 opposite to the substrate layer 100. The third insulating layer 250 is located between the top select gate 260 and the first stacked structure D1, and between the fourth insulating layer 281 and the second stacked structure D2. The dielectric layer 400 also extends to the side of the fourth insulating layer 281 opposite to the second stacked structure D2. The first interconnect structure 500 also penetrates the third insulating layer 250. The second isolation portion 300b penetrates the first stacked structure D1, the third insulating layer 250, the fourth insulating layer 281, and the dielectric layer 400.

[0140] In some implementations, reference Figure 8The semiconductor structure also includes a top select gate isolation structure 410, which extends through the top select gate 260 along the stacking direction Z. The material of the top select gate isolation structure 410 includes an insulating dielectric material such as silicon oxide.

[0141] In some implementations, reference Figure 8 The semiconductor structure also includes a third contact structure 520, which is located on the side of the first connection structure 500 away from the channel structure 220 and is connected to the first connection structure 500.

[0142] This application also provides a method for fabricating a semiconductor structure, such as... Figure 9 As shown, the method for fabricating a semiconductor structure may include:

[0143] Step S1: Form a first stacked structure, the first stacked structure comprising alternating layers of a first insulating layer and a gate layer;

[0144] Step S2: Forming multiple first isolation structures, wherein the multiple first isolation structures penetrate the first stacking structure along the stacking direction of the first stacking structure, extend along the first direction, and are spaced apart along the first direction; and

[0145] Step S3: Form a support structure, the support structure is located between adjacent first isolation structures along the first direction, and a portion of the first stacked structure is located between the first isolation structure and the support structure; wherein, the first direction intersects with the stacking direction.

[0146] In at least one embodiment of this application, a support structure is formed between adjacent first isolation structures along a first direction, and a portion of the first stacked structure is located between the first isolation structure and the support structure. The support structure penetrates the first insulating layer and the gate layer along the stacking direction. The support structure can support the first insulating layer and the gate layer between adjacent first isolation structures along the first direction, reducing the risk of collapse of the first insulating layer between adjacent first isolation structures along the first direction. Therefore, the gate layer can be better filled between adjacent first insulating layers.

[0147] The following will combine Figures 10 to 30 The specific processes of each step in the fabrication method of the semiconductor structure are detailed in this application.

[0148] refer to Figures 10 to 26 Step S1: Form a first stacked structure D1, which includes an alternately stacked first insulating layer 212 and a gate layer 211.

[0149] In some embodiments, the method for fabricating the semiconductor structure further includes forming a channel structure 220 (see reference). Figure 23The channel structure 220 is located on the supporting structure 230 (reference). Figure 24 In the first stacked structure D1 along the second direction Y side, the channel structure 220 extends in the first stacked structure D1 along the stacking direction Z of the first stacked structure D1.

[0150] Reference Figure 10 , Figure 11 and Figure 12 , Figure 11 For along Figure 10 Cross-sectional views of tangent lines M1-N1 and M2-N2. Figure 12 For along Figure 10 A cross-sectional view of the tangent line MN, in which, Figure 11 The diagram of the left-hand area is along Figure 10 Cross-sectional view of the tangent line M2-N2. Figure 11 The diagram of the right-hand area is along Figure 10 A cross-sectional view of the dicing line M1-N1, providing a temporary substrate 100′.

[0151] refer to Figure 10 The temporary substrate 100' includes a first substrate region B and a second substrate region A. The first substrate region B is used to form a first stacked structure, and the second substrate region A is used to form a second stacked structure. The first substrate region B may be located on the side of the second substrate region A along a first direction X and on the side of the second substrate region A along a second direction Y.

[0152] In some implementations, reference Figure 11 and Figure 12 The formation of temporary substrate 100' includes: forming a sacrificial semiconductor layer 108, a substrate isolation layer 107, and a first semiconductor layer 106, wherein the substrate isolation layer 107 is located between the first semiconductor layer 106 and the sacrificial semiconductor layer 108. The materials of the first semiconductor layer 106 and the sacrificial semiconductor layer 108 may be semiconductor materials such as polycrystalline silicon, and the material of the substrate isolation layer 107 may be an insulating dielectric material such as silicon oxide.

[0153] In other embodiments, forming a temporary substrate 100' includes forming a substrate dielectric layer and a sacrificial semiconductor layer located on one side of the substrate dielectric layer. The substrate dielectric layer may be made of an insulating dielectric material such as silicon oxide. The sacrificial semiconductor layer may be made of a semiconductor material such as polycrystalline silicon.

[0154] It should be noted that the method of forming the temporary substrate 100' is not limited to the methods listed above, and the temporary substrate 100' can also be other suitable structures.

[0155] Reference Figures 13 to 26The formation of a first stacked structure D1 includes: forming an initial stacked structure 200, the initial stacked structure 200 including alternating layers of a first insulating layer 212 and a second insulating layer 213; and replacing at least a portion of the second insulating layer 213 with a gate layer 211 to form the first stacked structure D1.

[0156] Reference Figure 13 and Figure 14 , Figure 13 In order to be in Figure 11 A basic diagram. Figure 14 In order to be in Figure 12 Based on the schematic diagram, an initial stacked structure 200 is formed, which includes an alternately stacked first insulating layer 212 and a second insulating layer 213.

[0157] In some embodiments, an initial stacked structure 200 is formed on one side of a temporary substrate 100'. The initial stacked structure 200 is located on the side of the first semiconductor layer 106 opposite to the sacrificial semiconductor layer 108.

[0158] In other embodiments, an initial stacked structure 200 is formed on one side of a temporary substrate 100'. The initial stacked structure 200 is located on the side of the sacrificial semiconductor layer facing away from the substrate dielectric layer.

[0159] The process for forming the first insulating layer 212 is a deposition process, including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The process for forming the second insulating layer 213 includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0160] The materials of the first insulating layer 212 and the second insulating layer 213 are different. During the subsequent removal of at least part of the second insulating layer 213, the second insulating layer 213 has a higher etching selectivity than the first insulating layer 212, thereby ensuring that the first insulating layer 212 has a good morphology and accurate dimensions, which in turn makes the gate layer formed subsequently have a good morphology and accurate dimensions.

[0161] In some embodiments, the material of the second insulating layer 213 may be silicon nitride, amorphous carbon, or polycrystalline silicon, and the material of the first insulating layer 212 may include silicon oxide.

[0162] Reference Figure 15 and Figure 16 , Figure 15 In order to be in Figure 13A basic diagram. Figure 16 In order to be in Figure 14 Based on the schematic diagram, a channel structure 220 is formed that penetrates the initial stacked structure 200 along the stacking direction Z; a support structure 230 is formed that penetrates the initial stacked structure 200 along the stacking direction Z.

[0163] In some embodiments, the method for fabricating the semiconductor structure further includes forming a third channel structure 310 that extends through the initial stacked structure 200 along the stacking direction Z. The third channel structure 310 may be a virtual channel structure.

[0164] In some embodiments, the channel structure 220, the support structure 230, and the third channel structure 310 are all located on one side of the first substrate region B.

[0165] In some embodiments, the support structure 230 and the third channel structure 310 are formed during the formation of the channel structure 220, which simplifies the process.

[0166] In some embodiments, there may be one or more channel structures 220. There may be one or more support structures 230. There may be one or more third channel structures 310.

[0167] In some embodiments, the channel structure 220 is located in the initial stacked structure 200 of the support structure 230 along the Y-side of the second direction, which intersects the first direction and the stacking direction, respectively.

[0168] In some implementations, reference Figure 16 The formation of the support structure 230 includes: forming an opening (not shown) in the initial stacked structure 200; and forming the support structure 230 in the opening. The process for forming the opening is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0169] In some embodiments, the structure of the support structure 230 is identical to that of the channel structure 220. Forming the support structure 230 in the opening includes: forming a first functional layer 231 on the inner wall of the opening; after forming the first functional layer 231, forming a first channel layer 232 located on the surface of the first functional layer 231 in the opening; and after forming the first channel layer 232, forming a first filling dielectric layer 233 in the opening. Further, forming the support structure 230 in the opening also includes: forming a first channel plug on the side of the first filling dielectric layer 233 facing away from the temporary substrate 100', the first channel plug being connected to the first channel layer 232. The fact that the structure of the support structure 230 is identical to that of the channel structure 220 reduces the difficulty of fabricating the opening.

[0170] In some embodiments, the step of forming a first functional layer 231 on the inner wall of the opening includes: sequentially forming a first barrier layer, a first charge trapping layer, and a first tunneling layer on the inner wall of the opening. The first barrier layer, the first charge trapping layer, and the first tunneling layer all extend along the stacking direction Z.

[0171] In some embodiments, the process for forming the first functional layer 231 includes deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process for forming the first channel layer 232 includes deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process for forming the first filling dielectric layer 233 includes deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process for forming the first channel plug includes deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0172] The materials of the first functional layer 231, the first channel layer 232, the first filling medium layer 233, and the first channel plug are the same as those described in the aforementioned embodiments and will not be detailed hereafter.

[0173] In other embodiments, forming a support structure in the opening includes depositing an insulating dielectric material in the opening. The material of the support structure is an insulating dielectric material. Exemplarily, the material of the support structure may be silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0174] In some implementations, reference Figure 15 The formation of the channel structure 220 includes: forming a first channel hole (not shown) in the initial stacked structure 200; and forming the channel structure 220 in the first channel hole. The process for forming the first channel hole is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0175] In some embodiments, forming a channel structure 220 in the first channel hole includes: forming a second functional layer on the inner wall of the first channel hole; after forming the second functional layer, forming a second channel layer located on the surface of the second functional layer in the first channel hole; and after forming the second channel layer, forming a second filling dielectric layer in the first channel hole. Further, forming the channel structure 220 in the first channel hole also includes: forming a second channel plug on the side of the second filling dielectric layer opposite to the temporary substrate 100', the second channel plug being connected to the second channel layer.

[0176] In some embodiments, the step of forming a second functional layer on the inner wall of the first channel hole includes: sequentially forming a second barrier layer, a second charge trapping layer, and a second tunneling layer on the inner wall of the first channel hole. The second barrier layer, the second charge trapping layer, and the second tunneling layer all extend along the stacking direction Z.

[0177] The materials of the second functional layer, the second channel layer, the second filling medium layer, and the second channel plug are the same as those described in the foregoing embodiments, and will not be described in detail again.

[0178] The processes for forming the second functional layer, the second channel layer, the second filling medium layer, and the second channel plug can all include deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0179] Forming a channel structure 220 that penetrates the initial stacked structure 200 along the stacking direction Z includes: forming a first channel structure 221 that penetrates the initial stacked structure 200 (reference). Figure 3 and Figure 4 ) and second channel structure 222 (reference) Figure 3 and Figure 4 ).

[0180] In some embodiments, along the first direction X, the size of the first channel structure 221 is smaller than the size of the second channel structure 222, and along the second direction Y, the size of the first channel structure 221 is larger than the size of the second channel structure 222. In this case, along the first direction X, the size of the support structure 230 is smaller than the size of the second channel structure 222, and along the second direction Y, the size of the support structure 230 is larger than the size of the second channel structure 222. Alternatively, along the first direction X, the size of the support structure 230 is larger than the size of the first channel structure 221, and along the second direction Y, the size of the support structure 230 is smaller than the size of the first channel structure 221.

[0181] In other embodiments, the dimension of the first channel structure 221 along the first direction X may be greater than or equal to the dimension of the second channel structure 222 along the first direction X. The dimension of the first channel structure 221 along the second direction Y may be less than or equal to the dimension of the second channel structure 222 along the second direction Y.

[0182] In some implementations, along the first direction X, the spacing between adjacent first channel structures 221 is greater than the spacing between adjacent second channel structures 222, which is beneficial for subsequent gate layer filling.

[0183] In other embodiments, there is no limitation on the relationship between the spacing distance between adjacent first channel structures 221 along the first direction X and the spacing distance between adjacent second channel structures 222 along the first direction X.

[0184] In some implementations, reference Figure 15The formation of the third channel structure 310 includes: forming a second channel hole (not shown) in the initial stacked structure 200; and forming the third channel structure 310 in the second channel hole. The process for forming the second channel hole is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0185] In some embodiments, forming a third channel structure 310 in the second channel hole includes: forming a third functional layer on the inner wall of the second channel hole; after forming the third functional layer, forming a third channel layer located on the surface of the third functional layer in the second channel hole; and after forming the third channel layer, forming a third filling dielectric layer in the second channel hole. Further, forming the third channel structure 310 in the second channel hole also includes: forming a third channel plug on the side of the third filling dielectric layer opposite to the temporary substrate 100', the third channel plug being connected to the third channel layer.

[0186] In some embodiments, the step of forming a third functional layer on the inner wall of the second channel aperture includes: sequentially forming a third barrier layer, a third charge trapping layer, and a third tunneling layer on the inner wall of the second channel aperture. The third barrier layer, the third charge trapping layer, and the third tunneling layer all extend along the stacking direction Z.

[0187] The materials of the third functional layer, the third channel layer, the third filling medium layer, and the third channel plug are the same as those described in the aforementioned embodiments and will not be detailed further.

[0188] The processes for forming the third functional layer, the third channel layer, the third filling medium layer, and the third channel plug can all include deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0189] In some embodiments, the opening, the first channel via, and the second channel via also extend into the temporary substrate 100'. For example, the opening, the first channel via, and the second channel via also extend into the sacrificial semiconductor layer 108, the substrate isolation layer 107, and the first semiconductor layer 106. Correspondingly, the channel structure 220, the third channel structure 310, and the support structure 230 also extend into the sacrificial semiconductor layer 108, the substrate isolation layer 107, and the first semiconductor layer 106.

[0190] In another embodiment, the temporary substrate includes a substrate dielectric layer and a sacrificial semiconductor layer located on one side of the substrate dielectric layer. Exemplarily, the opening, the first channel via, and the second channel via also extend into the substrate dielectric layer and the sacrificial semiconductor layer. Correspondingly, the channel structure 220, the third channel structure 310, and the support structure 230 also extend into the substrate dielectric layer and the sacrificial semiconductor layer.

[0191] Reference Figure 17 and Figure 18 , Figure 17 In order to be in Figure 15 A basic diagram. Figure 18 In order to be in Figure 16 Based on the schematic diagram, a top selection gate 260 is formed on one side of the initial stack structure 200, support structure 230, and channel structure 220 along the stacking direction Z. Exemplarily, the top selection gate 260 is formed on the side of a portion of the initial stack structure 200 facing away from the first substrate region B.

[0192] In some embodiments, forming the top select gate 260 includes: forming an initial top select gate on one side of the initial stack structure 200, support structure 230, and channel structure 220 along the stacking direction Z; removing the portion of the initial top select gate located on the second substrate region A and the portion of the initial top select gate located on the first substrate region B to form the top select gate 260. The process for forming the initial top select gate includes deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process for removing the portion of the initial top select gate located on the second substrate region A and the portion of the initial top select gate located on the first substrate region B includes an etching process, which includes one or a combination of dry etching and wet etching processes.

[0193] In some implementations, reference Figure 17 The method for fabricating the semiconductor structure further includes forming a top select gate isolation structure 410 that extends through the top select gate 260 along the stacking direction Z. The material of the top select gate isolation structure 410 includes an insulating dielectric material such as silicon oxide.

[0194] In some embodiments, forming the top select gate isolation structure 410 includes: forming a groove through the top select gate 260 along the stacking direction Z; and forming the top select gate isolation structure 410 in the groove. The process for forming the groove includes an etching process, which includes one or a combination of dry etching and wet etching processes. The process for forming the top select gate isolation structure 410 in the groove includes deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0195] In some implementations, in conjunction with reference Figure 17 and Figure 18 The method for fabricating the semiconductor structure further includes forming a second isolation layer 270 on the surface of the top selection gate 260 facing away from the initial stacked structure 200.

[0196] In some embodiments, the process for forming the second isolation layer 270 may include deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The material of the second isolation layer 270 is as described in the foregoing embodiments and will not be detailed further.

[0197] In some implementations, the second isolation layer 270 also covers the top selected gate isolation structure 410.

[0198] It should be noted that in other embodiments, the second isolation layer 270 may not be formed.

[0199] In some implementations, in conjunction with reference Figure 17 and Figure 18 The method for fabricating the semiconductor structure further includes: before forming the top select gate 260, forming a third insulating layer 250 on the side of the initial stacked structure 200 away from the substrate layer 100′; forming a fourth insulating layer 281 on a portion of the third insulating layer 250 away from the initial stacked structure 200, wherein the fourth insulating layer 281 is connected to the sidewall of the top select gate 260.

[0200] In some embodiments, the process for forming the third insulating layer 250 may include deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process for forming the fourth insulating layer 281 may include deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The materials for the third insulating layer 250 and the fourth insulating layer 281 are as described in the foregoing embodiments and will not be detailed further.

[0201] In some embodiments, the method of fabricating the semiconductor structure further includes forming a first connection structure 500 that extends through the top selection gate 260.

[0202] In some embodiments, forming a first connection structure 500 through the top selection gate 260 includes: forming a first opening (not shown) through the top selection gate 260; forming a first isolation layer 501 on the sidewall of the first opening; and forming a first conductive connection layer 502 in the first opening to form a connection channel structure 220.

[0203] In some embodiments, the process for forming the first opening includes an etching process, which includes one or a combination of dry etching and wet etching. The processes for forming the first isolation layer 501 and the first conductive interconnect layer 502 may include deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0204] In some embodiments, the first conductive connection layer 502 connects to the channel plug. A first isolation layer 501 is located between the first conductive connection layer 502 and the top select gate 260.

[0205] In other embodiments, a first connection structure is formed through the top selection gate 260, including: forming a first opening through the top selection gate; forming a first isolation layer on the sidewall of the first opening; and forming a first conductive connection layer and a first filler portion in the first opening, wherein the first isolation layer is located between the first conductive connection layer and the top selection gate, and the first conductive connection layer is located on the sidewall of the first filler portion and on the side surface of the first filler portion facing the channel structure.

[0206] In some embodiments, the first opening also extends into the second isolation layer 270, and correspondingly, the first connection structure 500 also extends into the second isolation layer 270.

[0207] Reference Figure 19 and Figure 20 , Figure 19 In order to be in Figure 17 A basic diagram. Figure 20 In order to be in Figure 18 Based on the schematic diagram, a first dielectric layer 280 is formed on the side of the second isolation layer 270 opposite to the top selection gate 260.

[0208] The process for forming the first dielectric layer 280 may include deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0209] In some embodiments, the first dielectric layer 280 is also formed on the side of the fourth insulating layer 281 opposite to the substrate layer 100'.

[0210] In some embodiments, the material of the second isolation layer 270 is different from the material of the first dielectric layer 280 and the material of the top selection gate 260, respectively. The materials of the first dielectric layer 280 and the second isolation layer 270 are as described in the foregoing embodiments.

[0211] Continue to refer to Figure 19 and Figure 20 A plurality of first isolation slots 243 are formed that penetrate the initial stacking structure 200 along the stacking direction Z, the plurality of first isolation slots 243 extend along the first direction X and are spaced apart along the first direction X; a second isolation slot 303 is formed that penetrates the initial stacking structure 200 and the top selection gate 260 along the stacking direction Z, the second isolation slot 303 being located on the side of the first isolation slot 243 along the second direction Y.

[0212] In some embodiments, the process of forming the first isolation trench 243 includes an etching process, which includes one or a combination of dry etching and wet etching. The process of forming the second isolation trench 303 includes an etching process, which includes one or a combination of dry etching and wet etching.

[0213] In some implementations, the second isolation trench 303 is formed during the formation of the first isolation trench 243, which simplifies the process.

[0214] In some embodiments, the second isolation groove 303 is formed after the first isolation groove 243 is formed, or the first isolation groove 243 is formed after the second isolation groove 303 is formed.

[0215] In some embodiments, forming a plurality of first isolation grooves 243 that penetrate the initial stacking structure 200 along the stacking direction Z includes forming first isolation grooves 243 that penetrate the initial stacking structure 200 and the top selection gate 260 along the stacking direction Z on both sides of the support structure 230 along the first direction X.

[0216] In some embodiments, the first isolation trench 243 also extends along the stacking direction Z through the second isolation layer 270 and the first dielectric layer 280. The second isolation trench 303 also extends along the stacking direction Z through the top selection gate 260 and the first dielectric layer 280.

[0217] In some embodiments, the dimension of the first isolation groove 243 along the first direction X is greater than the dimension of the first isolation groove 243 along the second direction Y.

[0218] In some embodiments, the dimension of the second isolation groove 303 along the first direction X is greater than the dimension of the second isolation groove 303 along the second direction Y.

[0219] In some embodiments, the dimension of the second isolation groove 303 along the first direction X is larger than the dimension of the first isolation groove 243 along the first direction X.

[0220] In some embodiments, the support structure 230 is located between adjacent first isolation grooves 243 along the first direction X.

[0221] Reference Figures 21 to 26 Replacing at least a portion of the second insulating layer 213 with the gate layer 211 includes: replacing at least a portion of the second insulating layer 213 with the gate layer 211 via the first isolation trench 243 and the second isolation trench 303.

[0222] In some embodiments, a portion of the second insulating layer 213 is replaced with the gate layer 211. In other embodiments, the entire second insulating layer is replaced with the gate layer.

[0223] The following implementation uses the replacement of a portion of the second insulating layer with the gate layer as an example.

[0224] Reference Figure 21 and Figure 22 , Figure 21 In order to be in Figure 19 A basic diagram. Figure 22 In order to be in Figure 20Based on the schematic diagram, a portion of the second insulating layer 213 is removed to form the first groove 601.

[0225] In some embodiments, the process of removing part of the second insulating layer 213 includes an etching process, which includes one or a combination of dry etching and wet etching processes.

[0226] In some embodiments, the second insulating layer 213 above the first substrate region B is removed to form the first trench 601, while the second insulating layer 213 above the second substrate region A is retained.

[0227] The first portion 212-1 of the first insulating layer 212 is disposed opposite to the first trench 601 in the stacking direction Z. The second portion 212-2 of the first insulating layer 212 is disposed opposite to the second insulating layer 213 above the second substrate region A in the stacking direction Z.

[0228] Reference Figure 23 and Figure 24 , Figure 23 In order to be in Figure 21 A basic diagram. Figure 24 In order to be in Figure 22 The schematic diagram shows that a gate layer 211 is formed in the first trench 601.

[0229] In some embodiments, the process for forming the gate layer 211 may include deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0230] At least a portion of the second insulating layer 213 is replaced with the gate layer 211 to form a first stacked structure D1. The first stacked structure D1 includes a first portion 212-1 of the alternatingly stacked gate layer 211 and first insulating layer 212.

[0231] In some embodiments, after a portion of the second insulating layer 213 is replaced with the gate layer 211, the initial stacked structure 200 also forms a second stacked structure D2, which includes a second portion 212-2 of the alternating layers of the second insulating layer 213 and the first insulating layer 212.

[0232] In some embodiments, the method for fabricating the semiconductor structure further includes forming a gate dielectric layer 214 on the inner wall of the first trench 601 before forming the gate layer 211 in the first trench 601. The gate dielectric layer 214 is located at least between the gate layer 211 and the second channel layer. For example, the gate dielectric layer 214 is located between the gate layer 211 and the second channel layer, and between the gate layer 211 and the first insulating layer 212.

[0233] In some embodiments, the process for forming the gate dielectric layer 214 may include deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0234] Reference Figure 25 and Figure 26 , Figure 25 In order to be in Figure 23 A basic diagram. Figure 26 In order to be in Figure 24 Based on the schematic diagram, a portion of the gate layer 211 is removed to form a second trench 304 and a third trench 305. The second trench 304 is connected to the second isolation trench 303. The third trench 305 is connected to the first isolation trench 243.

[0235] In some embodiments, after a portion of the gate layer 211 is removed, the gate layer 211 is recessed away from the first isolation trench 243 and the second isolation trench 303 relative to the first insulating layer 212.

[0236] In some embodiments, the process of removing a portion of the gate layer 211 includes an etching process, which includes one or a combination of dry etching and wet etching processes.

[0237] In other embodiments, the second groove 304 and the third groove 305 may not be formed.

[0238] Reference Figure 27 and Figure 28 , Figure 27 In order to be in Figure 25 A basic diagram. Figure 28 In order to be in Figure 26 Based on the schematic diagram, a first isolation structure 240 is formed in the first isolation groove 243; and a second isolation structure 300 is formed in the second isolation groove 303.

[0239] In some embodiments, during the process of forming the first isolation structure 240 in the first isolation trench 243, the second isolation structure 300 is formed in the second isolation trench 303, which simplifies the process.

[0240] In other embodiments, after the first isolation structure 240 is formed in the first isolation groove 243, the second isolation structure 300 is formed in the second isolation groove 303. Alternatively, after the second isolation structure 300 is formed in the second isolation groove 303, the first isolation structure 240 is formed in the first isolation groove 243.

[0241] In some embodiments, a first isolation structure 240 is formed in the first isolation groove 243 and the third groove 305; and a second isolation structure 300 is formed in the second isolation groove 303 and the second groove 304.

[0242] In some embodiments, forming a first isolation structure 240 in a first isolation trench 243 includes: forming a first insulating isolation layer 241 on the inner wall of the first isolation trench 243; and after forming the first insulating isolation layer 241, forming a first semiconductor isolation layer 242 in the first isolation trench 243.

[0243] In some embodiments, the first insulating layer 241 may also be formed in the third groove 305.

[0244] In some embodiments, the process for forming the first insulating isolation layer 241 and the process for forming the first semiconductor isolation layer 242 may include deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0245] In other embodiments, the material of the first isolation structure 240 is an insulating dielectric material. The process for forming the first isolation structure 240 includes deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0246] In some embodiments, forming the second isolation structure 300 in the second isolation trench 303 includes: forming a second insulating isolation layer on the inner wall of the second isolation trench 303; and after forming the second insulating isolation layer, forming a second semiconductor isolation layer in the second isolation trench 303. The materials of the second insulating isolation layer and the second semiconductor isolation layer are described in the foregoing embodiments and will not be detailed further.

[0247] In some embodiments, a second semiconductor isolation layer may also be formed in the second trench 304.

[0248] In some embodiments, the process for forming the second insulating isolation layer and the process for forming the second semiconductor isolation layer may both include deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0249] In some embodiments, the second insulating isolation layer includes a first insulating isolation portion 301a and a second insulating isolation portion 301b. The second semiconductor isolation layer includes a first semiconductor isolation portion 302a and a second semiconductor isolation portion 302b. The second isolation structure 300 includes a first isolation portion 300a and a second isolation portion 300b. The first isolation portion 300a includes a first insulating isolation portion 301a and a first semiconductor isolation portion 302a. The second isolation portion 300b includes a second insulating isolation portion 301b and a second semiconductor isolation portion 302b. The positional relationship between the first insulating isolation portion 301a and the first semiconductor isolation portion 302a, and the positional relationship between the second insulating isolation portion 301b and the second semiconductor isolation portion 302b, are described with reference to the foregoing embodiments and will not be detailed further.

[0250] In some embodiments, the first isolation portion 300a is located on the side of the first isolation structure 240 along the second direction Y. The second isolation portion 300b is located in the first stacked structure D1 on the side of the second stacked structure D2 along the second direction Y.

[0251] In other embodiments, the material of the second isolation structure 300 is an insulating dielectric material. The process for forming the second isolation structure 300 includes deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0252] In some embodiments, the dimension of the second isolation structure 300 extending along the first direction X is greater than the dimension of the first isolation structure 240 extending along the first direction X.

[0253] In some embodiments, the formed second isolation structure 300 extends along the first direction X into the portion of the first stacked structure D1 located on the side of the second stacked structure D2 along the second direction Y.

[0254] In some embodiments, the number of support structures 230 between adjacent first isolation structures 240 along the first direction X is one, or the number of support structures 230 between adjacent first isolation structures 240 along the first direction X is multiple.

[0255] In some embodiments, a plurality of first channel structures 221 are located on both sides of the first isolation structure 240 along the second direction Y and are adjacent to the first isolation structure 240, and a second channel structure 222 is located on the side of the first channel structure 221 away from the first isolation structure 240.

[0256] Reference Figure 29 and Figure 30 , Figure 29 In order to be in Figure 27 A basic diagram. Figure 30 In order to be in Figure 28 The schematic diagram shows that a second dielectric layer 290 is formed on the side of the first dielectric layer 280 opposite to the temporary substrate 100'. The first dielectric layer 280 and the second dielectric layer 290 constitute dielectric layer 400.

[0257] In some embodiments, the process for forming the second dielectric layer 290 includes deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The material of the second dielectric layer 290 is as described in the foregoing embodiments.

[0258] In some implementations, in conjunction with reference Figure 29 and Figure 30 The method for fabricating the semiconductor structure further includes forming a first contact structure 510 connecting the top selection gate 260 on the side of the top selection gate 260 away from the first insulating layer 212.

[0259] In some embodiments, a first contact structure 510 for connecting the top selection gate 260 is formed on the side of the top selection gate 260 opposite to the first insulating layer 212, including forming the first contact structure 510 in the dielectric layer 400 and the second isolation layer 270.

[0260] In some embodiments, forming a first contact structure 510 in the dielectric layer 400 and the second isolation layer 270 includes: forming a first contact hole in the dielectric layer 400 and the second isolation layer 270; and forming the first contact structure 510 in the first contact hole.

[0261] In some embodiments, the second isolation layer 270 and the dielectric layer 400 are made of different materials. During the formation of the first contact hole, the etching rate of the second isolation layer 270 is lower than that of the dielectric layer 400, thereby reducing over-etching and reducing etching loss on the top select gate 260.

[0262] In some embodiments, forming the first contact structure 510 in the first contact hole includes: forming a first adhesive layer on the inner wall of the first contact hole; and forming a first conductive layer in the first contact hole. The processes for forming the first adhesive layer and the first conductive layer may include deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The materials of the first conductive layer and the first adhesive layer are as described in the foregoing embodiments.

[0263] In some implementations, reference Figure 29 The method for fabricating the semiconductor structure further includes: forming a second contact structure 320 in the second stacked portion D2, wherein the second contact structure 320 is connected to the portion of the gate layer 211 located between the second isolation structure 300 and the second stacked structure D2.

[0264] In some implementations, reference Figure 29 The formation of the second contact structure 320 includes: forming a second contact hole in the second stack portion D2; and forming the second contact structure 320 in the second contact hole.

[0265] In some embodiments, forming a second contact structure 320 in a second contact hole includes forming a second conductive layer 322, a second filler portion 323, and a third insulating layer 321 in the second contact hole. The positional relationship of the second conductive layer 322, the second filler portion 323, and the third insulating layer 321 is as described in the foregoing embodiments. The materials of the second conductive layer 322, the second filler portion 323, and the third insulating layer 321 are as described in the foregoing embodiments. The processes for forming the second conductive layer 322, the second filler portion 323, and the third insulating layer 321 may all include deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0266] The third channel structure 310 is located between the second contact structure 320 and the second isolation part 300b.

[0267] Reference Figure 29 , Figure 30 , Figure 5 and Figure 8 , Figure 8 In order to be in Figure 29 A basic diagram. Figure 5 In order to be in Figure 30 Based on the schematic diagram, at least a portion of the temporary substrate 100' is removed to expose a portion of the channel structure 220; the second functional layer in the exposed channel structure 220 is removed and a portion of the second channel layer of the channel structure 220 is exposed; a substrate layer 100 is formed on the side of the first stacked structure D1 and the second stacked structure D2 away from the dielectric layer 400.

[0268] In some embodiments, the temporary substrate 100' includes a sacrificial semiconductor layer 108, a substrate isolation layer 107, and a first semiconductor layer 106. Removing at least a portion of the temporary substrate 100' includes removing the sacrificial semiconductor layer 108 and the substrate isolation layer 107 until the first semiconductor layer 106 and a portion of the channel structure 220 are exposed. Forming the substrate layer 100 on the side of the first stacked structure D1 and the second stacked structure D2 away from the dielectric layer 400 includes: forming a second semiconductor layer 101 on the side of the first semiconductor layer 106 away from the first stacked structure D1 and the second stacked structure D2, the second semiconductor layer 101 and the first semiconductor layer 106 constituting the substrate semiconductor layer, the second semiconductor layer 101 contacting the second channel layer; forming a substrate dielectric layer 102 on the side of the substrate semiconductor layer away from the first stacked structure D1 and the second stacked structure D2; forming an interconnect layer 103 on the side of the substrate dielectric layer 102 away from the substrate semiconductor layer; and forming a contact structure in the substrate dielectric layer 102 and a portion of the second semiconductor layer 101, the contact structure being connected to the interconnect layer 103.

[0269] In some embodiments, the temporary substrate includes: a substrate dielectric layer, and a sacrificial semiconductor layer located between the substrate dielectric layer and the first stacked structure D1 and between the substrate dielectric layer and the second stacked structure D2. Removing at least a portion of the temporary substrate to expose a portion of the channel structure includes: removing the sacrificial semiconductor layer to form a trench, the trench exposing a portion of the channel structure. Forming a substrate layer on the side of the first stacked structure D1 and the second stacked structure D2 opposite to the dielectric layer 400 includes: forming a substrate semiconductor layer in the trench, the substrate semiconductor layer contacting the second channel layer.

[0270] Another embodiment of this application also provides a memory, referenced... Figure 31 It includes: a memory cell array 402, which includes the semiconductor structure provided in the above embodiments of this application; and a peripheral circuit 401 coupled to the memory cell array 402.

[0271] The memory cell array 402 can be a 3D NAND flash memory cell array.

[0272] The semiconductor structure may be the same as the semiconductor structure described in any of the embodiments above, and will not be described again in the embodiments of this application.

[0273] In some implementations, peripheral circuitry 401 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of memory cell array 402. For example, peripheral circuitry 401 may include page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or one or more of any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0274] Another embodiment of this application also provides a memory system 30000, see reference. Figure 32 The memory system 30000 includes a controller 32200 and a memory 32100 provided in the above embodiments of this application. The controller 32200 is coupled to the memory 32100 and is used to control the memory 32100 to store data.

[0275] The memory system 30000 can be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a storage device located therein). Figure 32 As shown, the memory system 30000 also includes a host 31000. The host 31000 may be a processor of an electronic device, such as a central processing unit (CPU), or it may be a system-on-chip (SoC), such as an application processor (AP). The host 31000 may be configured to send or receive data to and from the memory 32100.

[0276] According to some embodiments, controller 32200 is coupled to memory 32100 and host 31000, and is configured to control memory 32100. Controller 32200 can manage data stored in memory 32100 and communicate with host 31000. In some embodiments, controller 32200 is designed to operate in a low duty cycle environment, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, controller 32200 is designed to operate in a high duty cycle environment, such as SSDs or embedded multi-media cards (eMMC) used as data storage devices in mobile devices such as smartphones, tablets, laptops, etc. Controller 32200 can be configured to control operations of memory 32100, such as read, erase, and program operations. The controller 32200 can also be configured to manage various functions related to data stored in or to be stored in the memory 32100, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the controller 32200 is further configured to process error correction codes (ECCs) related to data read from or written to the memory 32100. The controller 32200 can also perform any other appropriate functions, such as formatting the memory 32100. The controller 32200 can communicate with external devices (e.g., the host 31000) according to a specific communication protocol.For example, the controller 32200 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnection (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0277] Although exemplary fabrication methods and structures of semiconductor structures have been described herein, it is understood that one or more features may be omitted, substituted, or added from the structure of the semiconductor structure. Furthermore, the materials of the exemplified layers are merely exemplary.

[0278] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to the technical solutions formed by the selected combination of the above-described technical features, but should also cover other technical solutions formed by any combination of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor structure, wherein, include: The first stacked structure includes alternating layers of first insulating layer and gate layer; Multiple first isolation structures are arranged at intervals along the stacking direction of the first stacking structure, extending along a first direction and passing through the first stacking structure. as well as A support structure is located between adjacent first isolation structures along the first direction, and a portion of the first stacked structure is located between the first isolation structure and the support structure; Wherein, the first direction intersects with the stacking direction.

2. The semiconductor structure according to claim 1, wherein, The semiconductor structure also includes: A channel structure is located in the first stacked structure on the side of the support structure along the second direction; The structure of the support structure is the same as that of the channel structure; The second direction intersects with both the first direction and the stacking direction.

3. The semiconductor structure according to claim 2, wherein, The support structure includes a first functional layer and a first channel layer extending along the stacking direction, wherein the first functional layer is located between the first channel layer and the gate layer.

4. The semiconductor structure according to claim 1, wherein, The material of the supporting structure is an insulating dielectric material.

5. The semiconductor structure according to claim 1, wherein, The number of supporting structures between adjacent first isolation structures is one; or the number of supporting structures between adjacent first isolation structures is multiple.

6. The semiconductor structure according to claim 1, wherein, The semiconductor structure further includes: a first channel structure and a second channel structure; The first channel structures are located in the first stacked structures on both sides of the first isolation structure along the second direction and are adjacent to the first isolation structure. The second channel structure is located in the first stacked structure on the side of the first channel structure away from the first isolation structure. Wherein, along the first direction, the size of the first channel structure is smaller than the size of the second channel structure, and along the second direction, the size of the first channel structure is larger than the size of the second channel structure; The second direction intersects with both the first direction and the stacking direction.

7. The semiconductor structure according to claim 6, wherein, Along the first direction, the size of the support structure is smaller than the size of the second channel structure, and along the second direction, the size of the support structure is larger than the size of the second channel structure.

8. The semiconductor structure according to claim 6, wherein, Along the first direction, the size of the support structure is larger than the size of the first channel structure, and along the second direction, the size of the support structure is smaller than the size of the first channel structure.

9. The semiconductor structure according to claim 6, wherein, Along the first direction, the spacing between adjacent first channel structures is greater than the spacing between adjacent second channel structures.

10. The semiconductor structure according to claim 6, wherein, The spacing between the first channel structures on both sides of the first isolation structure along the second direction is greater than the spacing between adjacent first isolation structures.

11. The semiconductor structure according to claim 1, wherein, The semiconductor structure also includes: A channel structure extends through the first stacked structure; and A top selection gate is located on one side of the first stacking structure, the support structure, and the channel structure along the stacking direction; The first isolation structure also extends through the top selection gate.

12. The semiconductor structure according to claim 11, wherein, The portion of the first isolation structure that penetrates the top selection gate also extends to one side of a portion of the first stacked structure along the stacking direction.

13. The semiconductor structure according to claim 11, wherein, The semiconductor structure further includes a first connection structure extending through the top selection gate, the first connection structure comprising: A first conductive connection layer, connecting the channel structure; and A first isolation layer is located between the first conductive connection layer and the top selection gate.

14. The semiconductor structure according to claim 11, wherein, The semiconductor structure also includes: The first contact structure is located on the side of the top selection gate opposite to the first stacked structure and is connected to the top selection gate.

15. The semiconductor structure according to claim 14, wherein, The semiconductor structure also includes: A second isolation layer is located on the side of the top selection gate opposite to the first stacked structure; and A dielectric layer is located on the side of the second isolation layer opposite to the top selection gate; The material of the second isolation layer is different from the material of the dielectric layer and the material of the top selection gate, respectively; The first contact structure is located in the dielectric layer and penetrates the second isolation layer.

16. The semiconductor structure according to claim 11, wherein, The semiconductor structure also includes: A second isolation structure is located on the side of the first isolation structure along the second direction and extends through the first stack structure and the top selection gate; wherein, along the first direction, the second isolation structure extends in a larger dimension than the first isolation structure extends in a larger dimension. The second direction intersects with both the first direction and the stacking direction.

17. The semiconductor structure according to claim 16, wherein, The first stacked structure includes a first portion of the first insulating layer; The semiconductor structure also includes: The second stacked structure includes a second portion of the first insulating layer and a second insulating layer that are alternately stacked; Wherein, the second isolation structure extends along the first direction into the portion of the first stacked structure located on the side of the second stacked structure along the second direction; The semiconductor structure further includes: The second contact structure is located in the second stacked structure and is connected to the portion of the gate layer located between the second isolation structure and the second stacked structure.

18. A method for fabricating a semiconductor structure, wherein, include: A first stacked structure is formed, the first stacked structure comprising alternating layers of a first insulating layer and a gate layer; Multiple first isolation structures are formed, and the multiple first isolation structures penetrate the first stacking structure along the stacking direction of the first stacking structure, extend along the first direction, and are spaced apart along the first direction. as well as A support structure is formed, the support structure being located between adjacent first isolation structures along the first direction, and a portion of the first stacked structure being located between the first isolation structure and the support structure; Wherein, the first direction intersects with the stacking direction.

19. The preparation method according to claim 18, wherein, Forming the first stacked structure includes: An initial stacked structure is formed, the initial stacked structure comprising alternating layers of first and second insulating layers; At least a portion of the second insulating layer is replaced with a gate layer to form the first stacked structure; The first isolation structure is formed in multiple ways, including: Forming a plurality of first isolation slots extending through the initial stacking structure along the stacking direction of the initial stacking structure, the plurality of first isolation slots extending along a first direction and spaced apart along the first direction; and After at least a portion of the second insulating layer is replaced with the gate layer, the first isolation structure is formed in the first isolation trench; The method of replacing at least a portion of the second insulating layer with the gate layer includes: replacing at least a portion of the second insulating layer with the gate layer via the first isolation trench; The supporting structure includes: Before forming the first isolation groove, a support structure is formed through the initial stacking structure along the stacking direction of the initial stacking structure; the support structure is located between the first isolation grooves adjacent to each other along the first direction.

20. The preparation method according to claim 18, wherein, The preparation method further includes: A channel structure is formed, the channel structure being located in the first stacked structure along the second direction side of the support structure; The structure of the support structure is the same as that of the channel structure; The second direction intersects with both the first direction and the stacking direction.

21. The preparation method according to claim 18, wherein, The material forming the support structure is an insulating dielectric material.

22. The preparation method according to claim 18, wherein, The number of supporting structures between adjacent first isolation structures along the first direction is one, or the number of supporting structures between adjacent first isolation structures along the first direction is multiple.

23. The preparation method according to claim 19, wherein, The preparation method further includes: Before forming the first isolation trench, a first channel structure and a second channel structure are formed, both penetrating the initial stacked structure; The first channel structures are located on both sides of the first isolation structure along the second direction and are adjacent to the first isolation structure, while the second channel structure is located on the side of the first channel structure away from the first isolation structure. Wherein, along the first direction, the size of the first channel structure is smaller than the size of the second channel structure, and along the second direction, the size of the first channel structure is larger than the size of the second channel structure; The second direction intersects with both the first direction and the stacking direction.

24. The preparation method according to claim 23, wherein, Along the first direction, the size of the support structure is smaller than the size of the second channel structure, and along the second direction, the size of the support structure is larger than the size of the second channel structure; Alternatively, along the first direction, the size of the support structure is larger than the size of the first channel structure, and along the second direction, the size of the support structure is smaller than the size of the first channel structure.

25. The preparation method according to claim 19, wherein, The preparation method further includes: Forming a channel structure that extends through the initial stacking structure along the stacking direction; and A top selection gate is formed on one side of the initial stacking structure, the support structure, and the channel structure along the stacking direction; The formation of a plurality of first isolation grooves extending through the initial stacking structure along the stacking direction includes: First isolation grooves are formed on both sides of the support structure along the first direction, penetrating the initial stacked structure and the top selection gate along the stacking direction.

26. The preparation method according to claim 25, wherein, The preparation method further includes: Forming a first connection structure through the top selection gate includes: Forming a first opening through the top selection gate; A first isolation layer is formed on the sidewall of the first opening; and A first conductive connection layer connecting the channel structure is formed in the first opening; The first isolation layer is located between the first conductive connection layer and the top selection gate.

27. The preparation method according to claim 25, wherein, The preparation method further includes: A first contact structure for connecting the top selection gate is formed on the side of the top selection gate opposite to the first insulating layer.

28. The preparation method according to claim 27, wherein, The preparation method further includes: A second isolation layer is formed on the surface of the top selected gate that is opposite to the initial stacked structure; A dielectric layer is formed on the side of the second isolation layer opposite to the top selection gate; The material of the second isolation layer is different from the material of the dielectric layer and the material of the top selection gate, respectively; The formation of a first contact structure connecting the top selection gate on the side of the top selection gate away from the first insulating layer includes: forming the first contact structure in the dielectric layer and the second isolation layer.

29. The preparation method according to claim 25, wherein, The preparation method further includes: A second isolation groove is formed along the stacking direction, penetrating the initial stacking structure and the top selection gate, wherein the second isolation groove is located on the side of the first isolation groove along the second direction; and A second isolation structure is formed in the second isolation groove, wherein the dimension of the second isolation structure extending along the first direction is greater than the dimension of the first isolation structure extending along the first direction. Wherein, at least a portion of the second insulating layer is also replaced with a gate layer via the second isolation trench; The second direction intersects with both the first direction and the stacking direction.

30. The preparation method according to claim 29, wherein, The first stacked structure includes a first portion of the first insulating layer; Wherein, after partially replacing the second insulating layer with the gate layer, the initial stacked structure further forms a second stacked structure, the second stacked structure comprising: The second portion of the first insulating layer and the second insulating layer are alternately stacked; The second isolation structure extends along the first direction into the portion of the first stacked structure located on the side of the second stacked structure along the second direction; The preparation method further includes: forming a second contact structure in the second stacked portion, wherein the second contact structure is connected to the portion of the gate layer located between the second isolation structure and the second stacked structure.

31. A memory, wherein, include: A memory cell array, comprising the semiconductor structure as described in any one of claims 1 to 17; as well as The peripheral circuitry is coupled to the memory cell array.

32. A memory system, wherein, include: The memory as described in claim 31; as well as A controller, coupled to the memory, is used to control the memory to store data.

Images