Semiconductor device including neuromorphic device and method of manufacture

Abstract

The invention relates to a semiconductor device including a neuromorphic device and a method of manufacture. A semiconductor device may include: a first electrode; a switching layer on the first electrode; the oxygen storage layer is positioned on the switching layer; a second electrode on the oxygen storage layer; the heating electrode is positioned on the side wall of the switching layer; and an insulating spacer between the heating electrode and the switching layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0063694, filed on May 16, 2024, with the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to an electronic device, and more specifically, to a semiconductor device and a method of manufacturing the semiconductor device. Background Technology

[0004] Recently, with the miniaturization, low power consumption, performance improvements, and diversification of electronic devices, there has been a need for semiconductor devices capable of storing information in various electronic devices, such as computers and portable communication devices. In particular, interest in neuromorphic technologies that mimic the human nervous system has increased. The human nervous system comprises hundreds of billions of neurons and synapses, with synapses being the junctions between neurons. In neuromorphic technologies, the design of neuronal and synaptic circuits corresponding to these neurons and synapses aims to be implemented using semiconductor devices. Semiconductor devices used to implement neuromorphic technologies can be applied in a variety of fields, such as data classification and pattern recognition. Summary of the Invention

[0005] In one embodiment, a semiconductor device may include: a first electrode; a switching layer on the first electrode; an oxygen storage layer on the switching layer; a second electrode on the oxygen storage layer; a heating electrode on the sidewall of the switching layer; and an insulating spacer between the heating electrode and the switching layer.

[0006] In one embodiment, a method of manufacturing a semiconductor device may include: forming a memory stack by stacking a first electrode, a switching layer, an oxygen storage layer, and a second electrode; forming an insulating layer along the contour of the memory stack; forming a conductive layer on the insulating layer; forming heating electrodes surrounding the sidewalls of the memory stack by etching the conductive layer; and forming insulating spacers surrounding the sidewalls of the memory stack by etching the insulating layer. Attached Figure Description

[0007] Figure 1 This is a diagram used to describe a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2A and Figure 2B This is a diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 3A and Figure 3B This is a diagram illustrating the structure of a semiconductor device according to an embodiment.

[0010] Figure 4 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figures 5A to 5C This is a diagram illustrating a method for manufacturing a semiconductor device according to embodiments of the present disclosure. Detailed Implementation

[0012] Various embodiments relate to semiconductor devices having stable structures and improved properties, as well as methods of manufacturing such semiconductor devices.

[0013] The disclosed invention can improve the linearity of synapses and enhance the operational characteristics of neuromorphic devices.

[0014] The following description, with reference to the accompanying drawings, describes embodiments in accordance with the technical spirit of this disclosure.

[0015] Figure 1 This is a diagram used to describe a semiconductor device according to an embodiment of the present disclosure.

[0016] refer to Figure 1 The semiconductor device can be a neuromorphic device and can include multiple presynaptic neurons 10, multiple postsynaptic neurons 20, and synaptic units 30.

[0017] The semiconductor device may also include row lines 12 and column lines 22. Presynaptic neurons 10 and synaptic units 30 can be interconnected via row lines 12, while postsynaptic neurons 20 and synaptic units 30 can be interconnected via column lines 22. Row lines 12 may correspond to the axons of presynaptic neurons 10, while column lines 22 may correspond to the dendrites of postsynaptic neurons 20.

[0018] Synaptic units 30 can be positioned at each intersection between row lines 12 and column lines 22. Synaptic units 30 can be connected between presynaptic neurons 10 and postsynaptic neurons 20 via row lines 12 and column lines 22.

[0019] The presynaptic neuron 10 can generate a signal corresponding to specific data and transmit the generated signal to the row line 12. The postsynaptic neuron 20 can receive and process the synaptic signal that has passed through the synaptic unit 30 via the column line 22. As a non-limiting example, the presynaptic neuron 10 and the postsynaptic neuron 20 can be implemented using various circuits such as complementary metal-oxide-semiconductor (CMOS).

[0020] Synaptic unit 30 is an element whose conductivity or weight varies according to an electrical pulse (such as voltage or current) applied to its ends. As an example, synaptic unit 30 may be a variable resistive element or a resistive storage cell. A variable resistive element can switch between different resistance states depending on the voltage or current applied to its ends. The variable resistive element may include a switching layer that can have multiple resistance states. The switching layer may be a resistance switching layer. For example, the switching layer may include metal oxides (e.g., transition metal oxides and perovskite-based materials), phase change materials (e.g., chalcogenide-based materials), ferroelectric materials, and ferromagnetic materials, etc.

[0021] Synaptic unit 30 can change from a high-resistance state to a low-resistance state through a set operation, and from a low-resistance state to a high-resistance state through a reset operation. The weights of the synaptic states can be stored in synaptic unit 30 through set / reset operations. To store accurate weights, synaptic unit 30 can have analog characteristics, meaning its resistance changes proportionally to the applied voltage without sudden changes in resistance during set / reset operations. This analog characteristic allows for changes in conductivity (i.e., the weights of synaptic unit 30) and enables matrix multiplication calculations, i.e., multiplying the external input voltage by the weights.

[0022] Figure 2A and Figure 2B This is a diagram illustrating the configuration of a semiconductor device according to an embodiment. In the following description, for clarity, content overlapping with the previously described material may be omitted.

[0023] refer to Figure 2A The resistive storage cell 200A may include a first electrode 210, a second electrode 220, a switching layer 230, and an oxygen storage layer 240. The switching layer 230 may be located between the first electrode 210 and the second electrode 220, while the oxygen storage layer 240 may be located between the switching layer 230 and the second electrode 220.

[0024] The switching layer 230 may have variable resistance characteristics, wherein the switching layer exhibits different resistance states depending on the voltage or current supplied through the first electrode 210 and the second electrode 220. As an example, the switching layer 230 may have analog characteristics, wherein its resistance varies variably depending on the degree of generation of conductive filaments. The filaments electrically connect the first electrode 210 and the second electrode 220 to each other and can be generated, partially generated, or disappear depending on the movement of oxygen vacancies. Here, oxygen vacancies can be lattice defects generated when oxygen escapes from a location where oxygen should be bonded, and lattice defects can exhibit the same behavior as positively charged particles (e.g., holes). Filaments can be generated when oxygen vacancies connect to each other, and filaments can disappear when oxygen vacancies disconnect from each other. The switching layer 230 may include a metal oxide, and the metal included in the switching layer 230 may be a transition metal. As an example, the switching layer 230 may include metals such as Al, Si, Ti, Cr, Mn, Ni, Cu, Zn, Y, Zr, Nb, Hf, Ta, or W. The switching layer 230 may include HfO2, TiO2, Al2O3, or ZrO2, etc.

[0025] The oxygen storage layer 240 may include and store oxygen vacancies required for filament generation, and may also receive oxygen vacancies. During resistive switching of the resistive memory cell 200A, oxygen ions and / or oxygen vacancies may be exchanged between the switching layer 230 and the oxygen storage layer 240. As an example, during a set operation, a filament may be generated in the switching layer 230 due to oxygen vacancies provided from the oxygen storage layer 240, thereby reducing the resistance of the switching layer 230. During a reset operation, oxygen vacancies of the filament may be transferred to the oxygen storage layer 240, causing the filament to disappear and increasing the resistance of the switching layer 230. The oxygen storage layer 240 may include a metal or a metal oxide. As an example, the oxygen storage layer 240 may include Ti, Ta, or Hf, etc.

[0026] See Figure 2B The resistive memory cell 200 may include a first electrode 210, a second electrode 220, a switching layer 230, an oxygen storage layer 240, an insulating spacer 250, and a heating electrode 260. The heating electrode 260 may be located on and extend along the sidewall of the insulating spacer 250. As an example, the heating electrode 260 may be positioned shared with respect to the sidewalls of the first electrode 210, the second electrode 220, the switching layer 230, and the oxygen storage layer 240, with the insulating spacer 250 located between the sidewall of the switching layer 230 and the heating electrode 260. The insulating spacer 250 may also extend between the sidewalls of the first electrode 210 and the heating electrode 260, between the sidewalls of the oxygen storage layer 240 and the heating electrode 260, and between the sidewalls of the second electrode 220 and the heating electrode 260.

[0027] The heating electrode 260 can be an electrode that generates heat using Joule heating. The heat generated by the heating electrode 260 can be transferred to the switching layer 230 through the insulating spacer 250. The transferred heat affects the generation of filaments in the switching layer 230. See also Figure 2A Because the resistive memory cell 200A does not include a heating electrode, the oxygen vacancy mobility is low, and the oxygen vacancy accumulates in localized locations within the switching layer 230. These interconnected oxygen vacancy sites create individual strong filaments within the switching layer 230, resulting in more drastic resistance changes. Consequently, the analog characteristics of the resistive memory cell 200A deteriorate, and it becomes difficult to store accurate synaptic weights within it. See also... Figure 2B Since the resistive memory cell 200 includes a heating electrode 260, heat can be transferred to the switching layer 230. This transferred heat activates oxygen vacancies, and these thermally activated oxygen vacancies can be uniformly distributed throughout the switching layer 230. These uniformly distributed oxygen vacancies can interconnect, thereby generating multiple weak filaments within the switching layer 230. Therefore, the resistance change in the switching layer 230 can be more gradual.

[0028] According to the above structure, heat can be transferred to the switching layer 230 through the heating electrode 260, and the resistive memory cell 200 can have analog characteristics. Therefore, it is possible to provide a resistive memory cell 200 suitable for analog computing (ACiM) in memory.

[0029] Figure 3A and Figure 3B This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. Figure 3B It can be Figure 3A An enlarged view of the resistive memory cell 340. For clarity, content overlapping with the previously described material may be omitted below.

[0030] refer to Figure 3A The semiconductor device may include a substrate 300, a resistive memory cell 340, a transistor TR, a device isolation layer 304, an interconnect structure IC, and an interlayer insulating layer 330. The transistor TR can be a switching element of the resistive memory cell 340. The device isolation layer 304 may be located in the substrate 300, and the transistor TR may be located in the active region defined by the device isolation layer 304. The transistor TR may include a gate insulating layer 301, a gate electrode 302, and a junction 303. The switching element is not limited to the transistor TR and may be a diode, a bipolar junction transistor, etc.

[0031] The interconnect structure IC can be connected to the junction 303 and / or gate electrode 302 of the transistor TR. The interconnect structure IC can be located in the interlayer insulating layer 330 and can include contact plugs 320 and wiring 310. The contact plugs 320 and wiring 310 can be arranged in multiple layers. The resistive memory cell 340 can be connected to the transistor TR through the interconnect structure IC. Figure 3A The image shows a contact plug 320 connected to the upper and lower parts of the resistive memory cell 340 for reference, but in other embodiments, multiple contact plugs 320 may be connected to the upper and lower parts of the resistive memory cell 340 respectively.

[0032] See Figure 3B The resistive storage cell 340 may include a first electrode 341, a second electrode 342, a switching layer 343, an oxygen storage layer 344, an insulating spacer 345, and a heating electrode 346. The insulating spacer 345 may be located on the sidewalls of the first electrode 341, the second electrode 342, the switching layer 343, and the oxygen storage layer 344. The heating electrode 346 may be located on the sidewall of the insulating spacer 345.

[0033] The first wiring 311 and the first contact plug 321 can be connected to the first electrode 341. The second contact plug 322 and the second wiring 312 can be connected to the second electrode 342. During operation of the resistive memory cell 340, current can flow through the second wiring 312, the second contact plug 322, the resistive memory cell 340, the first contact plug 321, and the first wiring 311.

[0034] The third contact plug 323, the third wiring 313, the fourth contact plug 324, and the fourth wiring 314 can be connected to the heating electrode 346. During switching operations of the resistive memory cell 340, a voltage can be applied to the heating electrode 346. As an example, the voltage can be applied to the heating electrode 346 only during a set operation, and optionally during a reset operation. When a heating voltage is applied to the heating electrode 346 during a set operation, current can flow through the third wiring 313, the third contact plug 323, the heating electrode 346, the fourth contact plug 324, and the fourth wiring 314. Here, the path of current flowing through the heating electrode 346 and the path of current flowing through the resistive memory cell 340 can be separated from each other by an insulating spacer 345.

[0035] The resistive memory cell 340 with the above structure can be connected to the transistor TR. The third wiring 313 can be connected to the heating electrode 346, and a heating voltage can be applied to the heating electrode 346 through the third wiring 313 and the third contact plug 323. Therefore, the heating electrode 346 can generate heat and can transfer the generated heat to the switching layer 343.

[0036] Figure 4 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. In the following text, content overlapping with the previously described content may be omitted.

[0037] refer to Figure 4 The resistive storage cell 400 may include a first electrode 410, a second electrode 420, a switching layer 430, an oxygen storage layer 440, an insulating spacer 450, and a heating electrode 460.

[0038] The switching layer 430, the oxygen storage layer 440, and the second electrode 420 can be stacked on the first electrode 410. The stacked first electrode 410, switching layer 430, oxygen storage layer 440, and second electrode 420 can constitute a storage stack MS, and the storage stack MS can have a shape such as circular, elliptical, or polygonal in a plan view.

[0039] The insulating spacer 450 may surround the sidewall of the switching layer 430. The insulating spacer 450 may surround the sidewall of the oxygen storage layer 440, the sidewall of the first electrode 410, and the sidewall of the second electrode 420.

[0040] The insulating spacer 450 is used to insulate the storage stack from the heating electrode 460 and may comprise an insulating material such as silicon oxide or silicon nitride. Since heat generated from the heating electrode 460 is transferred to the switching layer 430 through the insulating spacer 450, the insulating spacer 450 may have a thickness T suitable for heat transfer and may be formed of a material suitable for heat transfer. The thickness of the insulating spacer 450 may be less than that of the heating electrode 460. However, when the thickness of the insulating spacer 450 is too small, current may flow from the heating electrode 460 to the storage stack MS through direct tunneling. Therefore, the thickness T of the insulating spacer 450 may be set to exceed a minimum predetermined value so that electrical reactions such as direct tunneling do not occur. Furthermore, the insulating spacer 450 may be formed of a material with low electrical conductivity and high thermal conductivity. When the insulating spacer 450 is formed of a material with high thermal conductivity, heat loss during heat transfer from the heating electrode 460 to the switching layer 430 can be minimized.

[0041] The heating electrode 460 is used to generate heat by Joule heating and may comprise a metal or a material with high electrical resistance, such as titanium nitride. The heating electrode 460 may surround the insulating spacer 450, thereby surrounding or covering the sidewalls of the first electrode 410, the switching layer 430, the oxygen storage layer 440, and the second electrode 420. The heating electrode 460 may completely or only partially surround the sidewalls of the storage stack MS. When the heating electrode 460 completely surrounds the sidewalls of the storage stack MS, for example, when it surrounds the sidewalls of the storage stack MS at 360° in plan view, the heat generated from the heating electrode 460 can be effectively transferred to the switching layer 430.

[0042] According to the above structure, a heating voltage can be applied to the heating electrode 460 during the set operation, and the heat generated from the heating electrode 460 can be transferred to the switching layer 430 through the insulating spacer 450. Here, the heating voltage can have the same polarity as the set voltage and can have a higher voltage level than the set voltage. During the reset operation, the heating voltage may not be applied to the heating electrode 460.

[0043] Figures 5A to 5C This is a diagram illustrating a method for manufacturing a semiconductor device according to embodiments of the present disclosure. In the following text, for clarity, content overlapping with the previously described content may be omitted.

[0044] See Figure 5A A memory stack MS can be formed on a substrate 500. The substrate 500 may include an understructure (not shown), such as a substrate, transistors, interconnect structures, and interlayer insulating layers. The memory stack MS may include a first electrode 510, a switching layer 530, an oxygen storage layer 540, and a second electrode 520. As an example, the memory stack MS can be formed by sequentially stacking the first electrode layer, the switching layer, the oxygen storage layer, and the second electrode layer on the substrate 500, and then etching the stacked layers. Depending on the physical properties of the stacked layers and the etching conditions, the sidewalls of the memory stack MS may have a vertical profile or a slanted profile. The memory stack MS may be linear, extending along a direction parallel to the surface of the substrate 500. Alternatively, the memory stack MS may have an island shape in plan view, and multiple memory stack MSs may be arranged in a matrix shape in plan view.

[0045] refer to Figure 5BAn insulating layer 550 can be formed on a storage stack MS. As an example, the insulating layer 550 can be formed along the contour of the storage stack MS using a deposition method such as atomic layer deposition (ALD). The insulating layer 550 can be formed along the inclined sidewalls of the storage stack MS. Subsequently, a conductive layer 560 can be formed on the insulating layer 550. As an example, the conductive layer 560 can be formed along the contour of the insulating layer 550 using a deposition method such as ALD. The conductive layer 560 can be formed along the inclined sidewalls of the storage stack MS. The conductive layer 560 may include a metal.

[0046] See Figure 5C The heating electrode 560A and the insulating spacer 550A can be formed by etching the conductive layer 560 and the insulating layer 550. The conductive layer 560 formed on the upper surface of the memory stack MS and the surface of the substrate 500 can be removed by the etching process, while the conductive layer 560 retained on the sidewall of the memory stack MS can be the heating electrode 560A. The insulating layer 550 formed on the upper surface of the memory stack MS and the surface of the substrate 500 can be removed by the etching process, while the insulating layer 550 retained on the sidewall of the memory stack MS can be the insulating spacer 550A. Thus, a resistive memory cell including a first electrode 510, a switching layer 530, an oxygen storage layer 540, a second electrode 520, an insulating spacer 550A, and a heating electrode 560A can be formed.

[0047] According to the manufacturing method described above, the heating electrode 560A can be formed to surround or cover the sidewall of the storage stack MS. Therefore, a resistive storage cell can be formed in which heat is transferred from the heating electrode 560A to the switching layer 530 through the insulating spacer 550A.

[0048] Although embodiments based on the technical concept of this disclosure have been described above with reference to the accompanying drawings, this is only for explaining embodiments based on the concept of this disclosure, and this disclosure is not limited to the above embodiments. Those skilled in the art to which this disclosure pertains can make various types of substitutions, modifications, changes, and combinations to the embodiments without departing from the technical concept of this disclosure as defined in the following claims, and it should be understood that such substitutions, modifications, changes, and combinations are within the scope of this disclosure.

Claims

1. A semiconductor device, comprising: First electrode; A switching layer is located on the first electrode; An oxygen storage layer is located on the switching layer; The second electrode is located on the oxygen storage layer; The heating electrode is located on the sidewall of the switching layer; as well as An insulating spacer is located between the heating electrode and the switching layer.

2. The semiconductor device according to claim 1, wherein, The insulating spacer extends to the sidewalls of the oxygen storage layer, the sidewalls of the first electrode, and the sidewalls of the second electrode.

3. The semiconductor device according to claim 1, wherein, The heating electrode surrounds the sidewall of the switching layer.

4. The semiconductor device according to claim 1, further comprising: The first wiring is connected to the first electrode; The second wiring is connected to the second electrode; as well as A third wiring is connected to the heating electrode and electrically disconnected from the first and second wirings.

5. The semiconductor device according to claim 4, wherein, When a heating voltage is applied to the heating electrode through the third wiring, the heating electrode is heated by Joule heating.

6. The semiconductor device according to claim 5, wherein, The switching layer is heated by heat from the heating electrode through the insulating spacer.

7. The semiconductor device according to claim 1, wherein, The heating electrode is heated during the positioning operation.

8. The semiconductor device according to claim 1, further comprising: Multiple conductive filaments in the switching layer during a setting operation in which a voltage is applied through the first electrode and the second electrode.

9. The semiconductor device according to claim 1, wherein, The switching layer includes inclined sidewalls, and the heating electrodes are disposed along the inclined sidewalls.

10. The semiconductor device according to claim 1, wherein, The insulating spacer includes silicon oxide or silicon nitride.

11. The semiconductor device according to claim 1, wherein, The heating electrode comprises titanium nitride.

12. A method for manufacturing a semiconductor device, the method comprising: A storage stack is formed by stacking a first electrode, a switching layer, an oxygen storage layer, and a second electrode; An insulating layer is formed along the contour of the storage stack; A conductive layer is formed on the insulating layer; Heating electrodes are formed around the sidewalls of the memory stack by etching the conductive layer; as well as Insulating spacers are formed around the sidewalls of the storage stack by etching the insulating layer.

13. The manufacturing method of claim 12 further includes forming wiring connected to the heating electrode.

14. The manufacturing method according to claim 12, wherein, The storage stack includes inclined sidewalls, and the heating electrode is formed along the inclined sidewalls.

15. The manufacturing method according to claim 12, wherein, The insulating spacer includes silicon oxide or silicon nitride.

16. The manufacturing method according to claim 12, wherein, The heating electrode comprises titanium nitride.

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