PIN rectifier diode with low forward voltage drop and preparation method thereof

Abstract

The invention discloses a PIN rectifier diode with low forward voltage drop and a preparation method thereof, and realizes breakthrough on the premise of not changing epitaxial parameters through aluminum-based ohmic contact innovation. Aluminum (the work function is 4.1-4.3 eV) is adopted to be in contact with heavily-doped P-type silicon (5.0-5.2 eV), a 100-angstrom Al-Si alloy layer is generated through high-temperature alloying, the contact potential barrier is reduced to 0.3-0.5 eV from 0.8-1.2 eV through the high-doping compensation effect, and the interface resistance is greatly reduced. According to the performance, under the 12.5 A test condition, the size VF of 165 mil in the prior art is 0.92 V, the size VF of 140 mil reaches 0.875 V, the size is reduced by 15.1%, and the performance is better. In the aspect of cost, the size is reduced, the grain number of a single wafer is increased by 40%, the cost of an aluminum material is only 1 / 20 of that of gold and silver, and the unit cost is remarkably reduced. The technology is compatible with the existing production line, is suitable for household appliances, power supplies and other scenes, can improve the power efficiency, reduces the consumption of noble metals, and has performance and cost advantages.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a low forward voltage drop PIN rectifier diode and its fabrication method. Background Technology

[0002] A diode is a two-terminal semiconductor device with a PN junction, containing an anode and a cathode. It exhibits unidirectional conductivity, allowing current to flow only from the anode to the cathode while preventing reverse flow. Its main functions include rectifying alternating current (AC) to direct current (DC), achieving unidirectional signal conversion, and serving as a switching element in circuits.

[0003] A PIN rectifier diode is a special type of semiconductor diode, named for its three-layer structure: a P-type layer, an intrinsic semiconductor layer (I-layer), and an N-type layer. It achieves unique electrical characteristics by introducing a lightly doped intrinsic semiconductor layer (I-layer) and is primarily used in high-frequency rectification, radio frequency switching, and signal control.

[0004] With the continuous development of electronic technology, the application of PIN rectifier diodes is becoming increasingly widespread. Currently, however, significant issues remain regarding the voltage drop (VF) of PIN rectifier diodes. Conventional PIN rectifier diode designs exhibit high forward voltage drops, leading to high operating losses and low efficiency. In applications with stringent low-power requirements, the increased temperature rise of these traditional designs severely impacts equipment performance and lifespan, demonstrating significant drawbacks.

[0005] Therefore, how to effectively reduce the forward voltage drop of PIN rectifier diodes and improve their working efficiency while maintaining high reliability is a technical challenge that the industry urgently needs to solve. Summary of the Invention

[0006] To address the above problems, this invention provides a low forward voltage drop PIN rectifier diode and its fabrication method that effectively reduces the forward voltage drop and improves the operating efficiency of the PIN rectifier diode while maintaining high reliability.

[0007] The technical solution of this invention is: A method for fabricating a low forward voltage drop PIN rectifier diode includes the following steps: Step 1, oxidation before ion implantation: An oxide film is grown on the surface of the N-epitaxial layer; Step 2, Oxidation Propulsion: P-type impurities implanted by ion implantation are implanted into the N- epitaxial layer, and high-temperature oxidation is performed to promote the formation of P+ implantation regions; Step 3, selective lithography: The wafer is divided into grains, and the area to be etched is exposed on the surface of the grains, while the rest is protected with photoresist. Step 4, trench etching: The silicon region exposed by the P+ implantation region is etched to form a trench extending into the N- epitaxial layer; Step 5: Deposit insulating polycrystalline silicon thin film: Insulating polycrystalline silicon was deposited on the upper surface using LPCVD; Step Six: Selective Photolithography and Sintering of the Glass Melt: Selective photolithography is performed on the wafer to form a photoresist glass, followed by sintering and glass melting to form a glass passivation layer on insulating polycrystalline silicon. Step 7, Deposit LTO thin film: A SiO2 protective layer was deposited on the wafer surface and the glass passivation layer using LPCVD. Step 8, selective photolithography and electrode oxide film: The passivation layer inside the grain trench is protected with photoresist, exposing the passivation film on the mesa and dicing surface; the passivation film on the surface of the grain mesa and dicing surface is removed to prepare for PVD sputtering. Step 9, PVD thin film sputtering: A layer of Al metal was sputtered using PVD and then high-temperature alloyed to form an ohmic contact region. Step 10, Metallization: Metal is deposited on the front and back of the chip using a vapor deposition station, and the process is complete.

[0008] Specifically, in step one, the thickness of the oxide film on the surface of the N-epitaxial layer is 300-900 angstroms.

[0009] Specifically, the PN junction etched in step four has a depth of 90-110um and a width of 330-380um.

[0010] Specifically, the thickness of the semi-insulating polycrystalline silicon grown in step five is 3000-8000 angstroms.

[0011] Specifically, in step six, the glass passivation layer extends downward from the top of the insulating polycrystalline silicon to the side region of the N-epitaxial layer.

[0012] Specifically, the thickness of the glass passivation layer mentioned in step six is ​​50-80 μm.

[0013] Specifically, the thickness of the SiO2 protective layer mentioned in step seven is 3000-9000 angstroms.

[0014] Specifically, the thickness of the metal layer formed by sputtering in step nine is 200-500 angstroms.

[0015] A low forward voltage drop PIN rectifier diode includes, from bottom to top, a back metal layer, an N+ substrate, an N- epitaxial layer, a P+ implantation region, an ohmic contact region, and a front metal layer; The cross-sectional length of the ohmic contact region and the front metal layer is smaller than the cross-sectional length of the P+ injection region; The N-epilithographic layer and the P+ implantation region are respectively provided with trenches; the trenches are provided with: Insulating polycrystalline silicon extends downward from the top surface of the P+ implantation region along the trench to the N- epitaxial layer; The SiO2 protective layer extends upward from the top surface of the insulating polycrystalline silicon and falls to the side of the N-epitaxial layer, where it connects with the insulating polycrystalline silicon. A glass passivation layer is disposed between the SiO2 protective layer and the insulating polycrystalline silicon.

[0016] The resistivity of the N+ substrate is 3-10 Ω·cm, and the thickness is 10-30 μm.

[0017] Beneficial effects of this invention: This invention achieves a breakthrough without changing epitaxial parameters through innovative aluminum-based ohmic contacts. It uses aluminum (work function 4.1-4.3 eV) and heavily doped p-type silicon (5.0-5.2 eV) to form a contact, which is then alloyed at high temperature to form a 100 angstrom Al-Si alloy layer. Through the high-doping compensation effect, the contact barrier is reduced from 0.8-1.2 eV to 0.3-0.5 eV, significantly reducing the interface resistance. In terms of performance, under 12.5A testing conditions, the existing technology with a 165mil wafer has a VF of 0.92V, while this invention with a 140mil wafer achieves a VF of 0.875V, representing a 15.1% size reduction and superior performance. Regarding cost, the size reduction increases the number of chips per wafer by 40%, and the cost of aluminum is only 1 / 20th that of gold and silver, resulting in a significant reduction in unit cost.

[0018] This technology is compatible with existing production lines and is suitable for scenarios such as home appliances and power supplies. It can improve power efficiency, reduce the consumption of precious metals, and has both performance and cost advantages. Attached Figure Description

[0019] Figure 1 This is a structural schematic diagram of step one of the present invention; Figure 2 This is a structural schematic diagram of step two of the present invention; Figure 3 This is a structural schematic diagram of step three of the present invention; Figure 4 This is a structural schematic diagram of step four of the present invention; Figure 5 This is a structural schematic diagram of step five of the present invention; Figure 6 This is a structural schematic diagram of step six of the present invention; Figure 7 This is a structural schematic diagram of step seven of the present invention; Figure 8 This is a structural schematic diagram of step eight of the present invention; Figure 9 This is a structural schematic diagram of step nine of the present invention; Figure 10 This is a structural schematic diagram of step ten of the present invention; Figure 11 This is a structural schematic diagram of step eleven of the present invention; In the figure, 1 is insulating polycrystalline silicon, 2 is glass passivation layer, 3 is SiO2 protective layer, 4 is ohmic contact region, 5 is front metal layer, 6 is P+ implantation region, 7 is N- epitaxial layer, 8 is N+ substrate, and 9 is back metal layer. Detailed Implementation

[0020] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0021] In the description of this invention, it should be understood that the terms "upper," "lower," "left," "right," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0022] The following is for reference. Figure 1-11 Describe the present invention; A method for fabricating a low forward voltage drop PIN rectifier diode includes the following steps: Step 1, oxidation before ion implantation: like Figure 1 As shown, a dense oxide film with a thickness of 300-900 angstroms is grown on the surface of the N-epitaxial layer; Step 2, Oxidation Propulsion: P-type impurities (B13+) are implanted into the N-epitaxial layer via ion implantation, and high-temperature oxidation is performed to further form the P+ implantation region, such as... Figure 2 As shown; the junction depth formed after oxidation must not be less than 13 μm.

[0023] Compared to diffusion-formed P+ regions, ion implantation creates deeper P+ junctions, resulting in high-concentration, steeply distributed P⁺ regions that balance low contact resistance and clear PIN interfaces. Furthermore, it offers higher doping uniformity and depth controllability, leading to better device parameter consistency. It also causes less damage to the intermediate I-region, ensuring the reverse breakdown voltage and leakage current characteristics of the PIN diode.

[0024] Step 3, selective lithography: Selective photolithography is performed on the top surface of the P+ implantation region to regionalize the wafer into grains. The areas to be etched are exposed on the surface of the grains, while the remaining areas are protected with photoresist. Figure 3 As shown; Step 4, trench etching: The silicon region exposed by the P+ implantation region is etched to form trenches extending into the N- epitaxial layer, such as... Figure 4 As shown; The etched PN junction has a depth of 90-110um and a width of 330-380um.

[0025] Step 5: Deposit insulating polycrystalline silicon thin film: Insulating polycrystalline silicon (SiPOS) is deposited on the upper surface using LPCVD, such as Figure 5 As shown; the thickness of the grown semi-insulating polycrystalline silicon (SiPOS) is 3000-8000 angstroms.

[0026] Step Six: Selective Photolithography and Sintering of the Glass Melt: like Figure 6 As shown, selective photolithography is performed on the wafer using photoresist glass, followed by sintering and glass fusion to form a glass passivation layer on silicon insulated polycrystalline silicon (SiPOS). The glass passivation layer extends downwards from the top of the silicon insulated polycrystalline silicon to the side region of the N-epitaxial layer, i.e. Figure 6 The area between the center line and the insulating polycrystalline silicon; the thickness of the glass passivation layer grown in this case is 50-80um.

[0027] Step 7, Deposit LTO thin film: like Figure 7 As shown, a SiO2 protective layer (LTO) is deposited on the wafer surface and the glass passivation layer using LPCVD. The thickness of the SiO2 protective layer is 3000-9000 angstroms.

[0028] The three-layer passivation structure (SIPOS + glass + LTO) of the mesa process solves reliability problems such as surface states, electric field concentration, and contamination erosion of semiconductor mesa from the inside out through the synergistic effect of defect passivation, physical isolation, ion trapping, stress buffering and sealing protection. Ultimately, it achieves the stability and resistance to environmental interference of the device in long-term use, thus significantly improving reliability.

[0029] Step 8, selective photolithography and electrode oxide film: The passivation layer within the grain trenches is protected with photoresist, exposing the passivation film on the mesa and dicing surfaces. The passivation film on the mesa and dicing surfaces is then removed to prepare for PVD sputtering. Figure 8 As shown; Step 9, PVD thin film sputtering: A layer of Al metal is sputtered using PVD, and a high-temperature alloy is then formed to create an ohmic contact region, such as... Figure 9 As shown, the thickness of the sputtered metal layer is 200-500 angstroms.

[0030] The ohmic contact formed between aluminum and the P⁺ implanted region eliminates the contact barrier through the tunneling effect, reduces interface defects through alloying, and accelerates carrier transport through high conductivity, significantly reducing the resistance and voltage loss of current passing through the metal-semiconductor interface, ultimately achieving a reduction in on-state voltage drop (V_F). This mechanism is one of the key processes for optimizing the forward characteristics of devices such as power diodes and rectifiers. The test data for unsputtered aluminum and aluminum-formed aluminum are 0.92V and 0.875V, respectively.

[0031] Step 10, Metallization: Metal is deposited on the front and back sides of the chip using a vapor deposition station to form a front metal layer and a back metal layer, respectively, and the processing is complete.

[0032] In this case, the front metal layer is connected to the ohmic contact area, and the back metal layer is connected to the bottom surface of the N+ substrate. The front metal layer includes Ti, Al, Ti, and Ni layers, and the back metal layer includes Ti, Ni, and Ag layers.

[0033] A low forward voltage drop PIN rectifier diode is fabricated by the fabrication method of a low forward voltage drop PIN rectifier diode according to claim 1, comprising a back metal layer 9, an N+ substrate 8, an N- epitaxial layer 7, a P+ implantation region 6, an ohmic contact region 4 and a front metal layer 5 arranged sequentially from bottom to top; The cross-sectional lengths of the ohmic contact area 4 and the front metal layer 5 (assuming...) Figure 11 The horizontal section length is less than the section length of the P+ injection zone 6; Trenches are provided on the sides of the N-epitaxy layer 7 and the P+ implantation region 6, respectively; the trenches are provided with: Insulating polycrystalline silicon 1 extends downward from the top surface of P+ implantation region 6 along the trench to N- epitaxial layer 7; The SiO2 protective layer 3 extends upward from the top surface of the insulating polysilicon 1 and falls to the side of the N-epitaxial layer 7, and is connected to the insulating polysilicon 1. The SiO2 protective layer 3 in this case includes a projectile portion and an adhesive portion connected in sequence; The ejection section extends upward from the top surface of the insulating polycrystalline silicon 1 and then falls to the side of the N-epitaxial layer 7; The bonding portion is located on the side of the N-epipolar layer 7 and is connected to the insulating polysilicon 1.

[0034] Traditional PIN diodes exhibit electric field distortion at the PN junction edge, leading to increased reverse leakage current (up to 50-100 nA) and decreased breakdown voltage. This invention addresses this by creating a bonding portion on the N-epitaxial layer 7 side, reducing the edge electric field strength by 30%. Through the electric field shielding effect of the dielectric materials (SiO2 and glass), the electric field peak is transferred from the junction edge to the interior of the passivation layer, effectively suppressing avalanche breakdown.

[0035] Meanwhile, traditional planar passivation layers are prone to ion migration due to etching damage or material defects, resulting in a significant increase in leakage current during high-temperature reverse bias testing. The bonding design in this case creates a three-dimensional encapsulation structure between the glass passivation layer and the insulating polycrystalline silicon. Combined with a 3000-9000 Å SiO2 protective layer deposited by LPCVD, a dual ion-blocking barrier is constructed, extending the migration distance of mobile ions from <1 μm in traditional designs to >5 μm.

[0036] A glass passivation layer 2 is disposed between the SiO2 protective layer 3 and the insulating polycrystalline silicon 1.

[0037] In this case, the glass passivation layer 2 is disposed on the top corner of the insulating polycrystalline silicon 1.

[0038] The small radius of curvature (typically <1μm) at the top corner of insulating polycrystalline silicon leads to dense electric field lines. In traditional designs, the electric field strength in this region can reach over 1.2 MV / cm, easily causing avalanche breakdown and increased leakage current. This design utilizes the field plate effect of the glass passivation layer to transfer the peak electric field from the silicon surface to the interior of the passivation layer, reducing the electric field strength at the corner by more than 30%. The stepped extension of the glass passivation layer at the corner (from the top of the insulating polycrystalline silicon to the side of the N-epitaxial layer) forms a stress buffer zone.

[0039] In this case, the resistivity of the N+ substrate 8 is 3-10 Ω·cm, and the thickness is 10-30 μm.

[0040] The resistivity of the N-epitaxial layer 7 is 25-50 Ω·cm, and the thickness is 30-80 μm.

[0041] The doping concentration of P+ implantation region 6 is 10. 15 -10 18 cm -3 The thickness is 8-16um. The thickness of the insulating polycrystalline silicon 1 is 3000-8000 angstroms, the thickness of the glass passivation layer 2 is 50-80 μm, and the thickness of the LTO (SiO2 protective layer 3) film is 3000-9000 angstroms.

[0042] This invention utilizes ion implantation to form the P+ implantation region 6. Before evaporating the metal, a layer of aluminum is deposited using thin-film sputtering. An alloy is then used to create a stable ohmic contact region 4 between this metal layer and the P+ implantation region 6. This innovative design significantly reduces the forward voltage drop (VF) of the device, thereby effectively reducing operating losses and improving efficiency. Furthermore, this invention combines a SiPOS film, a glass passivation layer 2, and an LTO three-layer passivation process, significantly enhancing the reliability and stability of the product, enabling it to perform exceptionally well in low-power, high-efficiency applications.

[0043] Regarding the information disclosed in this case, the following points need to be clarified: (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design. (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments; The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A method of fabricating a low forward voltage drop PIN rectifier diode, characterized by, The method comprises the following steps: Step one: oxidation before ion implantation Growing an oxide film on the surface of the N-epitaxial layer (7); Step two: oxidation promotion Implanting P-type impurities into the N-epitaxial layer (7) and promoting oxidation at high temperature to form a P+ implantation region (6); Step three: selective photoetching Dividing the wafer into dies and exposing the areas to be etched on the surface of the dies, and protecting the rest with photoresist; Step four: trench etching Etching the exposed silicon area of the P+ implantation region (6) to form a trench extending to the N-epitaxial layer (7); Step five: depositing an insulating polysilicon film Depositing an insulating polysilicon (1) on the upper surface using LPCVD; Step six: selective photoetching and sintering glass melting Performing selective photoetching and sintering glass melting on the wafer to form a glass passivation layer (2) on the insulating polysilicon; Step seven: depositing an LTO film Depositing a SiO2 protective layer (3) on the surface of the wafer and the glass passivation layer using LPCVD, Step eight: selective photoetching and electrode surface oxide film Protecting the passivation layer in the die trench with photoresist, exposing the passivation film on the mesa and the cutting channel, and removing the passivation film on the surface of the mesa and the cutting channel to prepare for PVD sputtering; Step nine: PVD thin film sputtering Sputtering an Al metal layer using PVD and forming an ohmic contact region (4) by high-temperature alloying; Step ten: metallization Using an evaporation table to evaporate metal on the front and back surfaces of the chip, and completing the processing.

2. The method of claim 1, wherein the low forward voltage drop PIN rectifier diode is prepared by the steps of: The thickness of the oxide film on the surface of the N-epitaxial layer (7) is 300-900 angstroms.

3. The method of claim 1, wherein the low forward voltage drop PIN rectifier diode is prepared by the steps of: The depth of the PN junction etched in step four is 90-110 um, and the width is 330-380 um. ​ 4. The method of claim 1, wherein the low forward voltage drop PIN rectifier diode is prepared by the steps of: The thickness of the semi-insulating polysilicon (1) grown in step five is 3000-8000 angstroms. ​ 5. The method of claim 1, wherein the low forward voltage drop PIN rectifier diode is prepared by the steps of: The glass passivation layer (2) in step six extends from the top of the insulating polysilicon (1) to the side area of the N-epitaxial layer (7). ​ 6. The method of claim 1, wherein the low forward voltage drop PIN rectifier diode is formed by the steps of: The thickness of the glass passivation layer (2) in step six is 50-80 um. ​ 7. The method of claim 1, wherein the low forward voltage drop PIN rectifier diode is formed by the steps of: The thickness of the SiO2 protective layer (3) in step seven is 3000-9000 angstroms. ​ 8. The method of claim 1, wherein the low forward voltage drop PIN rectifier diode is formed by the steps of: The thickness of the metal layer sputtered in step nine is 200-500 angstroms. ​ 9. A low forward voltage PIN rectifier diode prepared by the method of claim 1, wherein The back metal layer (9), N+ substrate (8), N-epitaxial layer (7), P+ implantation region (6), ohmic contact region (4), and front metal layer (5) are sequentially arranged from bottom to top; The cross-sectional length of the ohmic contact region (4) and the front metal layer (5) is less than the cross-sectional length of the P+ implantation region (6); The N-epitaxial layer (7) and the P+ implantation region (6) are respectively provided with trenches on the sides; the trenches are provided with: An insulating polysilicon (1) extending from the top surface of the P+ implantation region (6) along the trench to the N-epitaxial layer (7); A SiO2 protective layer (3) extending from the top surface of the insulating polysilicon (1) upward and then falling to the side of the N-epitaxial layer (7) and connecting with the insulating polysilicon (1); A glass passivation layer (2) arranged between the SiO2 protective layer (3) and the insulating polysilicon (1).

10. A low forward voltage drop PIN rectifier diode according to claim 9, wherein, The resistivity of the N+ substrate (8) is 3-10 Ω·cm, and the thickness is 10-30 um.

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