Semiconductor device and method for forming a semiconductor device

Abstract

Embodiments of the present disclosure provide a method of providing a method of using a substrate having (551) / lt; 110gt, 110gt; the invention discloses a GAA device manufactured by a substrate on a top surface. Selecting (551) / lt; 110gt, 110gt; the substrate enables channel height scaling and improved hole mobility without sacrificing electron mobility. The embodiment of the invention also relates to a semiconductor device and a method for forming the semiconductor device.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to semiconductor devices and methods for forming semiconductor devices. BACKGROUND

[0002] The semiconductor industry has experienced continuous rapid growth due to the increasing improvement in the integration density of various electronic components. In most cases, this improvement in integration density comes from repeated reductions in the minimum component size, allowing more components to be integrated into a given chip area. As the minimum component size is reduced, the trade-off between hole and electron mobility in the channel region becomes a challenge that affects device performance. SUMMARY

[0003] Embodiments of the present disclosure provide a semiconductor device, comprising: a first source / drain region; a second source / drain region; two or more semiconductor layers disposed between and coupled with the first source / drain region and the second source / drain region, wherein the two or more semiconductor layers are formed on a (551) plane; and a gate structure wrapping the two or more semiconductor layers.

[0004] Another embodiment of the present disclosure provides a semiconductor device, comprising: two or more semiconductor layers, wherein each of the two or more semiconductor layers comprises a first end portion having a first surface roughness, a second end portion, and a center portion connecting the first end portion and the second end portion, the center portion having a second surface roughness different from the first surface roughness; a gate structure wrapping the center portion of the two or more semiconductor layers; a first source / drain region disposed on the first end portion of the two or more semiconductor layers; and a second source / drain region disposed on the second end portion of the two or more semiconductor layers.

[0005] Yet another embodiment of the present disclosure provides a method for forming a semiconductor device, comprising: selecting a substrate having a top surface with a surface orientation (551); epitaxially growing a semiconductor stack from the top surface of the substrate, wherein the semiconductor stack comprises two or more first semiconductor layers and two or more second semiconductor layers, and the two or more first semiconductor layers and the two or more second semiconductor layers are alternately stacked; forming a fin structure from the semiconductor stack and the substrate; forming a sacrificial gate structure over the fin structure; etching back the fin structure along sidewalls of the sacrificial gate structure; epitaxially growing source / drain regions from the two or more second semiconductor layers; depositing a contact etch stop layer (CESL) over the source / drain regions; depositing an interlayer dielectric (ILD) layer over the contact etch stop layer; removing the sacrificial gate structure to expose the fin structure; removing the two or more first semiconductor layers; and forming a replacement gate structure around the two or more second semiconductor layers. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noted that, in accordance with standard practice, the various drawings are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a flowchart of a method for fabricating a semiconductor device according to embodiments of the present disclosure.

[0008] Figure 2 , Figure 2A , Figure 3 , Figure 4 , Figure 4A and Figures 5-10 illustrate various stages of fabricating a semiconductor device according to embodiments of the present disclosure.

[0009] Figure 11A , Figure 11B , Figure 11C , Figure 11D and Figure 11E illustrate a gate region of a GAA device according to embodiments of the present disclosure.

[0010] Figures 12A-12B illustrates electron mobility of a GAA device according to embodiments of the present disclosure.

[0011] Figure 13 illustrates a semiconductor device according to embodiments of the present disclosure.

[0012] Figure 14 illustrates a semiconductor device according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the disclosure in any way. For example, in the following description, a first component forming over or on a second component can include embodiments where the first component and the second component are in direct contact, and can also include embodiments where additional components can be formed between the first component and the second component such that the first component and the second component can not be in direct contact. Furthermore, the present disclosure can refer to a number of examples using corresponding reference numerals in various examples. This repetition is for the purpose of simplicity and clarity and does not itself serve as an indication that one example group, or set of components, is related to another example group, or set of components.

[0014] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", "top", "bottom" and the like, can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 64 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0015] The foregoing generally outlines some aspects of the embodiments described in this disclosure. While some embodiments described herein are described in the context of nanosheet channel FETs, implementations of some aspects of this disclosure can be used in other processes and / or other devices, such as planar FETs, FinFETs, horizontal all-around gate (HGAA) FETs, vertical all-around gate (VGAA) FETs, and other suitable devices. One of ordinary skill in the art will readily understand that other modifications can be made within the scope of the present disclosure. Furthermore, while method embodiments can be described in a particular order, various other method embodiments can be performed in any logical order, and can include fewer or more steps than described herein. In this disclosure, source / drain refers to source and / or drain. Source and drain are used interchangeably.

[0016] The fins can be patterned by any suitable method. For example, the fins can be patterned using one or more photolithography processes, including a double patterning or multiple patterning process. Generally, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing for the creation of patterns having, for example, smaller pitches than would otherwise be obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins.

[0017] The GAA nanosheet channel structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including a double patterning or multiple patterning process. Generally, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing for the creation of patterns having, for example, smaller pitches than would otherwise be obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0018] Horizontally stacked GAA nanosheet channel structures provide excellent short channel control and increased effective channel width (Weff) per footprint. There is a high demand for further nanosheet height scaling and performance improvement for successive technology nodes.

[0019] In current technologies, GAA nanosheet channels are formed in a (100) substrate surface orientation with the channel along a <110> direction (hereinafter referred to as a (100) / <110> channel), or in a (110) substrate surface orientation with the channel along a <110> direction (hereinafter referred to as a (110) / <110> channel). As the channel height is reduced, the (100) / <110> channel experiences a significant hole mobility loss, while the electron mobility increases slightly. On the other hand, the (110) / <110> channel experiences some electron mobility loss as the channel height is reduced, while the hole mobility increases somewhat. Thus, further scaling of the channel height under current technologies inevitably faces a trade-off between hole mobility loss or electron mobility loss.

[0020] In addition, it has been observed that various other factors, such as surface roughness scattering (SRS), remote phonon scattering (RPS), acoustic deformation potential (ADP), and remote coulomb scattering (RCS), also contribute to electron mobility loss, particularly as the channel width is scaled down. Among these factors, the surface roughness scattering factor dominates the performance of (110) / <110> electron mobility.

[0021] Embodiments of the present disclosure provide thin channel nanosheet devices and methods for forming devices by selecting (551) / <110> substrates as starting materials. The (551) surface is tilted 8 degrees from the (110) surface towards the (100) surface and has similar band structure and other scattering factors as the (110) surface. Thus, as the sheet height is scaled down, the (551) surface provides the same gain in high hole mobility as the (110) surface. In addition, the (551) / <110> channel exhibits (100) / <110> channel-like electron mobility, i.e., does not suffer from electron mobility loss as the channel height is scaled down.

[0022] Thus, like the (110) / <110> channel, GAA devices with (551) / <110> channels according to the present disclosure provide improved hole mobility without affecting electron mobility.

[0023] In addition, the (551) silicon surface has the potential to achieve lower surface roughness. In some embodiments, the (551) surface is subjected to surface roughness treatment to reduce the SRS factor and improve electron mobility. In summary, the (551) / <110> channel according to the present disclosure provides a gain in hole mobility without sacrificing electron mobility as the channel height is reduced.

[0024] Figure 1 is a flowchart of a method 100 for fabricating a semiconductor device according to embodiments of the present disclosure. Figure 2 、 Figure 2A 、 Figure 3 、 Figure 4 、 Figure 4A and Figures 5-10 various stages of fabricating an exemplary semiconductor device 200 according to embodiments of the present disclosure are schematically illustrated. In particular, the semiconductor device 200 can be fabricated according to the method 100 of Figure 1

[0025] At operation 102 of the method 100, a substrate 202 having a (551) surface orientation is selected to form the semiconductor device 200 thereon. Figure 2A ​is a schematic plan view of a substrate 202 according to the present disclosure. A top surface 202t of the substrate 202 is a (551) oriented small planar surface. In particular, the (511) surface is tilted 8 degrees from the (110) surface towards the <100> direction. As Figure 2 and Figure 2A The substrate 202 has a <110> direction along the x-direction, as shown.

[0026] In some embodiments, the substrate 202 can include a single-crystalline semiconductor material such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP.

[0027] Depending on the circuit design, the substrate 202 can include various doping configurations. For example, the substrate 202 can include a p-doped region or p-well and an n-doped region or n-well. One or more n-type devices (such as nFETs) will be formed above and / or within the p-well. One or more p-type devices (such as pFETs) will be formed above and / or within the n-well.

[0028] At operation 104 of the method 100, a semiconductor stack including alternating first semiconductor layers 206 and second semiconductor layers 208 is formed on the substrate 202 to facilitate formation of nanosheet channels in a multi-gate n-type device (such as a nanosheet channel FET). The first semiconductor layers 206 and the second semiconductor layers 208 can be epitaxially grown from the top surface 202t of the substrate 202. Due to the nature of epitaxial growth, the first semiconductor layers 206 and the second semiconductor layers 208 also have a (551) surface orientation.

[0029] The first semiconductor layers 206 and the second semiconductor layers 208 have different compositions. In some embodiments, the two semiconductor layers 206 and 208 provide different oxidation rates and / or different etch selectivity. At a later stage of fabrication, portions of the second semiconductor layers 208 form nanosheet channels in the multi-gate device. As an example, as shown, Figure 2 three first semiconductor layers 206 and three second semiconductor layers 208 are arranged alternately. Depending on the desired number of channels in the semiconductor device to be formed, more or fewer semiconductor layers 206 and 208 can be included. In some embodiments, the number of semiconductor layers 206 and 208 is between 1 and 10.

[0030] For an n-type device or nFET, the first semiconductor layer 206 can include silicon germanium (SiGe). The first semiconductor layer 206 can be a SiGe layer that includes Ge at a molar ratio greater than 25%. For example, the first semiconductor layer 206 can be a SiGe layer that includes Ge at a molar ratio between 25% and 50%. For an n-type device or nFET, the second semiconductor layer 208 can include silicon. In some embodiments, the second semiconductor layer 208 is a silicon layer.

[0031] For a p-type device or pFET, the first semiconductor layer 206 can include silicon germanium (SiGe). The first semiconductor layer 206 can be a SiGe layer that includes Ge at a molar ratio greater than 25%. For example, the first semiconductor layer 206 can be a SiGe layer that includes Ge at a molar ratio between 25% and 50%. For a p-type device or pFET, the second semiconductor layer 208 can include silicon, Ge, a compound semiconductor (such as SiC, GeAs, GaP, InP, InAs, and / or InSb), an alloy semiconductor (such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP), or a combination thereof. In some embodiments, the second semiconductor layer 208 is a silicon layer.

[0032] The semiconductor layers 206, 208 can be formed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. The semiconductor stacks for n-type devices and p-type devices can be formed separately using patterning techniques.

[0033] At operation 106 of the method 100, as shown in Figure 3 , Figure 3 is a schematic perspective view of the semiconductor device 200 with a fin structure 210 formed by etching portions of the semiconductor stack and the underlying substrate 202, respectively. As shown in Figure 3 , the fin structure 210 is formed along the x-direction. In other words, the fin structure 210 is formed along the <110> direction.

[0034] As shown in Figure 3 , after the fin structure 210 is formed, each semiconductor layer 208 has two horizontal channel surfaces 208xys that are parallel to the top surface 202t of the substrate 202. The horizontal channel surfaces 208xys have a (551) surface orientation. Each semiconductor layer 208 also has two vertical channel surfaces 208xzs along the x-direction. At the ends of the fin structure 210, the semiconductor layer 208 has two channel end surfaces 208yzs. In some embodiments, the channel end surfaces 208yzs have a (110) surface orientation.

[0035] In some embodiments, each fin structure 210 has a width Wl along the y-direction. The width Wl can be selected according to the circuit design. In some embodiments, the width Wl can be in a range between about 10 nm to about 200 nm. Portions of the semiconductor layer 208 serve as channel regions connecting between source / drain components in a semiconductor device to be formed. Each semiconductor layer 208 can have a channel height CH along the z-direction. In some embodiments, the channel height CH is in a range between about 2 nm and about 10 nm. The semiconductor layer 206 serves to define a vertical distance between adjacent channel regions formed by the semiconductor layer 208 for a subsequently formed device. Each semiconductor layer 206 can have a gate height GH along the z-direction. In some embodiments, the gate height GH of the semiconductor layer 206 is equal to or greater than the channel height CH of the semiconductor layer 208. In some embodiments, the gate height GH is in a range between about 2 nm and about 10 nm. The channel spacing CS (a combined distance of the gate height GH and the channel height CH) can be in a range between 4 nm and 20 nm. It should be noted that as portions of the semiconductor layer 206 can be removed along with the semiconductor layer 208 during a subsequent replacement gate process, the channel height CH will decrease and the gate height GH will increase. However, the channel spacing CS remains substantially unchanged.

[0036] As Figure 4 shown, Figure 4 is a schematic view of the semiconductor device 200, after the formation of the fin structures, an isolation layer 212 is formed. The isolation layer 212 fills in the trenches between the fin structures 210 and is then etched back under the semiconductor stacks of the fin structures 210. The isolation layer 212 can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), or other suitable deposition processes. In some embodiments, the isolation layer 212 can include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof. In some embodiments, the isolation layer 212 is formed by a suitable deposition process to cover the fin structures 210, to fill in the trenches between the fin structures 210, and then recess etching using a suitable anisotropic etching process to expose the active portions of the fin structures 210.

[0037] At operation 108, as Figure 4 shown, Figure 4 is a schematic perspective view of the semiconductor device 200, a sacrificial gate structure 214 is formed over the isolation layer 212 and over the exposed portions of the fin structures 210. The sacrificial gate structure 214 is formed over the portions of the fin structures 210 that are to become channel regions. Figure 4A is a schematic plan view of the substrate 202 showing the orientation of the fin structures 210 and the sacrificial gate structure 214. AsFigure 4A As shown, fin structure 210 along <110> The orientation is formed, and the sacrificial gate structure 214 is perpendicular to the fin structure 210.

[0038] The sacrificial gate structure 214 may include a sacrificial gate dielectric layer 218, a sacrificial gate electrode layer 220, a pad layer 222, and a mask layer 224.

[0039] The sacrificial gate dielectric layer 218 may be conformally formed over the fin structure 210 and the isolation layer 212. In some embodiments, the sacrificial gate dielectric layer 218 may be deposited by a CVD process, a subatmospheric pressure CVD (SACVD) process, a FCVD process, an ALD process, a PVD process, or other suitable processes. The sacrificial gate dielectric layer 218 may include one or more layers of dielectric material, such as SiO2, SiN, high-k dielectric material, and / or other suitable dielectric material.

[0040] The sacrificial gate electrode layer 220 may be blanket-deposited over the sacrificial gate dielectric layer 218. The sacrificial gate electrode layer 220 comprises silicon, such as polycrystalline silicon or amorphous silicon. The thickness of the sacrificial gate electrode layer is in the range of about 42 nm to about 200 nm. In some embodiments, the sacrificial gate electrode layer 220 undergoes a planarization operation. The sacrificial gate electrode layer 220 may be deposited using CVD (including LPCVD and PECVD), PVD, ALD, or other suitable processes.

[0041] Subsequently, a pad layer 222 and a mask layer 224 are formed over the sacrificial gate electrode layer 220. The pad layer 222 may include silicon nitride. The mask layer 224 may include silicon oxide. Next, a patterning operation is performed on the mask layer 224, the pad layer 222, the sacrificial gate electrode layer 220, and the sacrificial gate dielectric layer 218 to form a sacrificial gate structure 214.

[0042] Then, gate sidewall spacers 216 are formed on the sidewalls of the sacrificial gate structure 214. For example... Figure 4 As shown, gate sidewall spacers 216 are formed on the sidewalls of each sacrificial gate structure 214. The gate sidewall spacers 216 are formed by blanket deposition of one or more layers of insulating material. The insulating material can be deposited using any suitable deposition method. In some embodiments, the gate sidewall spacers 216 can be formed by ALD or CVD. In some embodiments, the insulating material of the gate sidewall spacers 216 may include one or more dielectric materials. In some embodiments, the insulating material of the gate sidewall spacers 216 may include a dielectric material selected from silicon oxide, silicon nitride (such as Si3N4), carbon-doped silicon oxide, nitrogen-doped silicon oxide, porous silicon oxide, or combinations thereof.

[0043] The gate sidewall spacers 216 have a thickness along the x-direction in a range between about 3 nm and about 12 nm and cover portions of the fin structures 210. In some embodiments, the gate sidewall spacers 216 are subjected to an anisotropic etch to remove the gate sidewall spacers 216 from horizontal surfaces, such as the top surface of the mask layer 224 and the top surface of the isolation layer 212. In other embodiments, the gate sidewall spacers 216 on the horizontal surfaces can be removed during a fin structure etch back in operation 108 discussed below.

[0044] At operation 110, as shown in Figure 5 , Figure 5 are cross-sectional views of the semiconductor device 200 along line A-A in Figure 4 , the fin structures 210 not covered by the sacrificial gate structures 214 are etched back. The fin structures 210 not covered by the sacrificial gate structures 214 and the gate sidewall spacers 216 are etched to expose the well portions of each fin structure 210 and form source / drain cavities 205. In some embodiments, a suitable dry etch and / or wet etch can be used to remove the semiconductor layers 206, 208 together or individually.

[0045] At operation 112, as shown in Figures 5-6 , the internal spacers 226 are formed. As shown in Figure 5 , to form the internal spacers 226, the semiconductor layer 206 exposed to the source / drain cavities 205 is partially etched along the horizontal direction or x-direction from the semiconductor layer 208 to form internal spacer cavities under the gate sidewall spacers 216. In some embodiments, the semiconductor layer 206 can be selectively etched by using a wet etchant, such as but not limited to ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine o-phenanthroline (EDP), or potassium hydroxide (KOH) solution.

[0046] After the internal spacer cavities are formed, the internal spacers 226 are formed in the internal spacer cavities by depositing an insulating layer conformally and then partially removing the insulating layer by an anisotropic etch process. The insulating layer can be formed by ALD or any other suitable method. The subsequent etch process removes most of the insulating layer except inside the cavities, resulting in the internal spacers 226. In some embodiments, the internal spacers 226 can include one or more dielectric materials. In some embodiments, the internal spacers 226 can include a dielectric material, such as SiO2, SiON, SiOC, or SiOCN-based dielectric materials, air gaps, or a combination thereof.

[0047] The internal spacer 226 and the gate sidewall spacer 216 may be formed of the same material or different materials to achieve desired performance. In some embodiments, the internal spacer 226 may have a lower dielectric constant k than the gate sidewall spacer 216 to obtain desired performance, such as low capacitance. In some embodiments, the internal spacer 226 may have a higher dielectric constant k than the gate sidewall spacer 216 to obtain desired performance, such as improved device reliability.

[0048] The internal spacer 226 has a thickness in the range of about 3 nm to about 12 nm along the x-direction. In some embodiments, the thickness of the internal spacer 226 is substantially similar to the thickness of the gate sidewall spacer 216.

[0049] At operation 114, such as Figure 7 As shown, an epitaxial source / drain region 232 is formed. In some embodiments, a bottom epitaxial layer 229 may be formed at the bottom of the source / drain cavity 205. The bottom epitaxial layer 229 may be an epitaxial semiconductor layer grown from the substrate 202, and therefore has the same crystal orientation as the substrate 202. The bottom epitaxial layer 229 may be a transition layer between the semiconductor substrate 202 and the crystal structure of the epitaxial source / drain region 232. In some embodiments, the bottom epitaxial layer 229 may be used as an alignment component for forming a back-side source / drain contact.

[0050] A bottom isolation layer 230 may be formed on the bottom epitaxial layer 229. The bottom isolation layer 230 may include one or more dielectric materials. The bottom isolation layer 230 may be formed by a deposition process and a subsequent etching process. The bottom isolation layer 230 may prevent leakage between the source / drain region 232 and the mesa region below the sacrificial gate structure 214.

[0051] Epitaxial source / drain regions 232 can be epitaxially grown from exposed surfaces (such as semiconductor layer 208 and substrate 202) in source / drain regions 205. Typically, epitaxial source / drain regions 232 for N-type devices and epitaxial source / drain regions 232 for P-type devices are formed separately using patterning techniques.

[0052] The epitaxial source / drain region 232 for n-type devices can include one or more layers of Si, SiP, SiC, and SiCP. The epitaxial source / drain region 232 also includes N-type dopants, such as phosphorous (P), arsenic (as), etc. In some embodiments, the epitaxial source / drain region 232 can be a layer of Si including phosphorous (P) dopants. The epitaxial source / drain region 232 for p-type devices can include one or more layers of Si, SiGe, Ge with p-type dopants, such as boron (B). In some embodiments, the epitaxial source / drain region 232 can be a SiGe material including boron as dopants.

[0053] The epitaxial source / drain region 232 grows from the channel facet 208yzs, as a result, a portion of the sidewall 232s of the source / drain region has the same surface orientation as the channel facet 208yzs. In some embodiments, the portion of the sidewall 232s in contact with the semiconductor layer 208 has a (110) surface orientation.

[0054] At operation 116, as shown in FIG. 2B, a contact etch stop layer (CESL) 236 and an interlayer dielectric (ILD) layer 238 are conformally formed over the semiconductor substrate. Figure 7

[0055] The CESL 236 can be uniformly formed over the exposed surfaces of the semiconductor device 200. The CESL 236 is formed on the exposed facet 232f of the epitaxial source / drain region 232, the exposed surfaces of the gate sidewall spacers 216, and the exposed surfaces of the isolation layer 212. The CESL 236 serves as an etch stop to provide protection for the source / drain region 232 during the formation of the source / drain contact features. The CESL 236 can include Si3N4, SiON, SiCN, or any other suitable material, and can be formed by CVD, PVD, or ALD.

[0056] The ILD layer 238 is formed over the CESL 236. The material for the ILD layer 238 includes a compound including Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials, such as polymers, can be used for the ILD layer 238. In some embodiments, the ILD layer 238 can be formed by flowable CVD (FCVD). The ILD layer 238 protects the epitaxial source / drain region 232 during the removal of the sacrificial gate structure 214. After the material for the ILD layer 238 is deposited, a planarization process, such as a CMP process, can be performed to expose the sacrificial gate structure 214 for subsequent processing.

[0057] At operation 118, as shown in FIG. 2C, the sacrificial gate structure 214 is removed to expose the epitaxial source / drain region 232. Figure 8 ​As shown, the sacrificial gate structure 214 and semiconductor layer 206 are removed to expose semiconductor layer 208. The sacrificial gate dielectric layer 218 and sacrificial gate electrode layer 220 are removed using dry etching, wet etching, or a combination thereof. Semiconductor layer 206 is exposed and subsequently removed, creating a gate cavity 240 of nanosheets surrounding semiconductor layer 208. Figure 8 As shown, the central portion 208c of each semiconductor layer 208 is exposed to the gate cavity 240, while the end portion 208e of each semiconductor layer 208 is covered by the internal spacer 226 and the gate sidewall spacer 216.

[0058] At operation 120, such as Figure 9 As shown, a roughness treatment process is performed to reduce the surface roughness of the central portion of the semiconductor layer 208.

[0059] In some embodiments, a roughening process can be performed by processing the semiconductor device 200 in a process gas. In some embodiments, a roughening process can be performed by Xe / H2 plasma, H2 annealing, H radicals, etc.

[0060] The roughening process improves the surface flatness of the exposed portion of semiconductor layer 208 (i.e., the central portion 208c of semiconductor layer 208). Figure 9A This is a partially enlarged cross-sectional view of the semiconductor layer 208 exposed to the gate cavity 240. (See attached image.) Figure 9A As shown, the horizontal channel surface 208xys and the vertical channel surface 208xzs are exposed to process chemicals.

[0061] As discussed above, the horizontal channel surface 208xys has a (551) surface orientation, which is stable in alkaline solutions and is beneficial for maintaining surface flatness and reducing surface roughness. In some embodiments, after roughening treatment, the horizontal channel surface 208xys of the central portion 208c of the semiconductor layer 208 can achieve a roughness Δ of less than about 3.0 Å. rms For example, the roughness Δ is about 1.1A, while the unexposed end portion 208e has a roughness Δ of about 5.2A. rms .

[0062] The vertical channel surface 208xzs can have a (1110) surface. Roughening treatment also improves the flatness of the vertical channel surface 208xzs, but to a lesser extent than the horizontal channel surface 208xys. In some embodiments, after roughening treatment, the vertical channel surface 208xzs of the central portion 208c of the semiconductor layer 208 can achieve a roughness Δ of less than about 5.0 Å. rms For example, in the range between about 4.2 Å and about 4.8 Å, while the unexposed end portion 208e has a roughness Δ in the range between about 5.0 Å and about 6.6 Å.rms Because the channel height CH is smaller than the channel width W1, the area of ​​the vertical channel surface 208xzs is smaller than the area of ​​the horizontal channel surface 2080xys. Therefore, the roughness reduction effect from the vertical channel surface 208xzs is less than the roughness reduction effect from the horizontal channel surface 208xys.

[0063] At operation 122, such as Figure 10 As shown, a replacement gate structure 248 is formed above the central portion 208c of the semiconductor layer 208, and the replacement gate structure 248 fills the gate cavity 240. The replacement gate structure 248 includes a gate dielectric layer 242 and a gate electrode layer 244. In some embodiments, an interface layer 243 may be formed on the semiconductor layer 208 before forming the gate dielectric layer 242. Figures 11A-11D (as shown in the image).

[0064] A gate dielectric layer 242 is formed on the exposed surface within the gate cavity. The gate dielectric layer 242 can have different compositions and dimensions for N-type and P-type devices, and is formed individually using patterned mask layers and different deposition formulations. The gate dielectric layer 242 may comprise one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 242 can be formed by CVD, ALD, or any suitable method.

[0065] A gate electrode layer 244 is formed on the gate dielectric layer 242 to fill the gate cavity. The gate electrode layer 244 may comprise one or more layers of conductive materials, such as tungsten, aluminum, copper, titanium, tantalum, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. In some embodiments, the gate electrode layer 244 may be formed by CVD, ALD, electroplating, or other suitable methods. In some embodiments, the gate electrode layer 244 may comprise different conductive materials and be formed in different processes. Optionally, the gate electrode layer 244 may comprise the same conductive material and be formed in the same process. After forming the gate electrode layer 244, a planarization process (such as a CMP process) is performed to remove excess deposition of the gate electrode material and expose the top surface of the ILD layer 238.

[0066] Subsequently, source / drain contact features 254 are formed. Contact holes can be formed through the ILD layer 238 and the CESL 236 to expose the epitaxial source / drain regions 232, and subsequently filled with a conductive material. Suitable photolithography and etching techniques are used to form the contact holes through the various layers. After forming the contact holes, a silicide layer 252 is selectively formed over the surface of the epitaxial source / drain regions 232 exposed by the contact holes. The silicide layer 252 can be formed by depositing a metal source layer to cover the exposed surfaces, including the exposed surfaces of the epitaxial source / drain regions 232, and performing a rapid thermal anneal process. In some embodiments, the metal source layer includes a metal layer selected from W, Co, Ni, Ti, Mo, and Ta, or a metal nitride layer selected from tungsten nitride, cobalt nitride, nickel nitride, titanium nitride, molybdenum nitride, and tantalum nitride. After forming the metal source layer, the rapid thermal anneal process is performed. During the rapid anneal process, portions of the metal source layer over the epitaxial source / drain regions 232 react with the silicon in the epitaxial source / drain regions 232 to form the silicide layer 252. The unreacted portions of the metal source layer are then removed. In some embodiments, the silicide layer 252 can include one or more of WSi, CoSi, NiSi, TiSi, MoSi, and TaSi.

[0067] After forming the silicide layer 252, a conductive material is deposited to fill the contact holes and form the source / drain contact features 254. Optionally, prior to forming the source / drain contact features 254, a barrier layer (not shown) can be formed in the contact holes. In some embodiments, the layer of conductive material for the gate contact can be formed by CVD, PVD, plating, ALD, or other suitable techniques. In some embodiments, the conductive material for the source / drain contact features 254 includes TiN, TaN, Ta, Ti, Hf, Zr, Ni, W, Co, Cu, Ag, Al, Zn, Ca, Au, Mg, Mo, Cr, etc. Subsequently, a CMP process is performed to remove portions of the layer of conductive material above the top surface of the ILD layer 238.

[0068] Embodiments of the present disclosure provide a solution to improve hole mobility while scaling down without sacrificing electron mobility. Figures 11A-11E A gate region of a GAA device according to embodiments of the present disclosure is shown. Figure 11A is a schematic close-up view of a NFET device according to the present disclosure. Figure 11B is a schematic close-up view of a PFET device according to the present disclosure. Figure 11C is a close-up view of the NFET device of Figure 11A is a close-up view of the NFET device of Figure 11D is a schematic cross-section along the D-D line of Figure 11C is a schematic cross-section along the D-D line of Figure 11A and Figure 11BAs shown, the channel regions of the NFET device and the PFET device have similar channel compositions. In some embodiments, both the NFET device and the PFET device have a semiconductor layer 208 that is a nanosheet channel. The semiconductor layer 208 (or channel) is formed of epitaxial silicon, with a horizontal channel surface 208xys in the (551) plane along the <110> direction, and an end channel surface 208yzs in the (110) plane along the <110> direction. In some embodiments, the source / drain regions 232n for the NFET device are formed of SiP. In some embodiments, the source / drain regions 232p for the PFET device are formed of SiGe.

[0069] In some embodiments, a central portion 208c of the semiconductor layer 208 (or channel layer) and an end portion 208e of the semiconductor layer 208 have different surface roughnesses. The central portion 208c is smoother or has a lower roughness than the end portion 208e.

[0070] Figure 11E is an XRD (x-ray diffraction) pattern of the interface in region 11E in Figure 11D . The XRD pattern indicates that the (551) silicon surface at the horizontal channel surface 208xys can be clearly observed.

[0071] Figure 12A is a graph showing electron mobility of the (110) channel surface and the (100) channel surface along the channel height. As Figure 12A shown, the electron carriers of the (110) channel surface are further from the interface (such as the interface between the semiconductor layer 208 and the interface layer 243) than the electron carriers of the (100) channel surface. In other words, the electron carriers of the (110) channel surface are more concentrated at the center of the channel layer or semiconductor layer 208 or channel sheet than the electron carriers of the (100) channel surface. The (110) channel surface is less sensitive to the surrounding gate stack (i.e., the RCS factor) than the (100) channel surface, but is more sensitive to surface roughness (i.e., the SRS factor).

[0072] Figure 12B is a graph showing after roughness processing according to the present disclosure, the (551) / <110> channel surface has similar electron mobility to the (100) channel surface. In Figure 12BIn some embodiments, curves 301, 302, 303 represent electron mobility of (110), (551), and (100) channel surfaces, respectively. (100) channel surface has the highest electron mobility. Curve set 304 demonstrates SRS factors for electron mobility of (100), (551), and (110) surfaces. Curve set 305 demonstrates RCS factors for electron mobility of (100), (551), and (110) surfaces. Curve 306 represents electron mobility of (551) surface after roughness treatment according to embodiments of the disclosure. Curve 306 shows that (551) / <110> channel surface has similar electron mobility as (100) channel surface.

[0073] Figure 13 is a schematic cross-sectional view of a semiconductor device 200a according to the disclosure. Semiconductor device 200a is similar to semiconductor device 200, except that semiconductor device 200a includes partial bottom isolation layer 230a. As a result, bottom portions of epitaxial source / drain regions 232 are grown from bottom epitaxial layer 229 having (551) surfaces. As a result, portions of bottom surface 232bs of epitaxial source / drain regions 232 have (551) surfaces.

[0074] Figure 14 is a schematic cross-sectional view of a semiconductor device 200b according to the disclosure. Semiconductor device 200b is similar to semiconductor devices 200, 200a, except that semiconductor device 200b does not include any bottom isolation layer. As a result, epitaxial source / drain regions 232 are also grown from bottom epitaxial layer 229 having (551) surfaces. As a result, bottom surface 232bs of epitaxial source / drain regions 232 has (551) surfaces.

[0075] Various embodiments or examples described herein provide a variety of advantages over the prior art. By selecting (551) / <110> substrates as starting materials, embodiments of the disclosure enable channel height scaling and improved hole mobility without sacrificing electron mobility.

[0076] Some embodiments of the disclosure provide a semiconductor device, comprising: a first source / drain region; a second source / drain region; two or more semiconductor layers disposed between and coupled with the first source / drain region and the second source / drain region, wherein the two or more semiconductor layers are formed on a (551) plane; and a gate structure wrapping the two or more semiconductor layers.

[0077] In some embodiments, each of the two or more semiconductor layers has a <110> crystal direction extending along a direction from the first source / drain region to the second source / drain region.

[0078] In some embodiments, each of the two or more semiconductor layers includes: a top surface; a bottom surface opposite the top surface; and a vertical surface connecting the top surface to the bottom surface, wherein the vertical surface extends from the first source / drain region and the second source / drain region, wherein the top surface has a (551) surface orientation and the vertical surface has a (110) surface orientation.

[0079] In some embodiments, a distance between the top surface and the bottom surface is in a range between about 2 nm and about 10 nm.

[0080] In some embodiments, a distance between the top surface and the bottom surface is in a range between 2 nm and 10 nm.

[0081] In some embodiments, each of the two or more semiconductor layers further includes: a first end surface connecting the top surface and the bottom surface, wherein the first end surface is in contact with a sidewall of the first source / drain region and the first end surface has a (110) surface orientation.

[0082] In some embodiments, each of the two or more semiconductor layers includes a first end portion adjacent to the first end surface and a center portion in contact with the gate structure, the first end portion having a first surface roughness, the center portion having a second surface roughness different from the first surface roughness.

[0083] In some embodiments, the first surface roughness is greater than the second surface roughness.

[0084] Some embodiments of the present disclosure provide a semiconductor device, comprising: two or more semiconductor layers, wherein each of the two or more semiconductor layers includes a first end portion, a second end portion, a center portion connecting the first end portion and the second end portion, the first end portion having a first surface roughness, the center portion having a second surface roughness different from the first surface roughness; a gate structure wrapping the center portion of the two or more semiconductor layers; a first source / drain region disposed on the first end portion of the two or more semiconductor layers; and a second source / drain region disposed on the second end portion of the two or more semiconductor layers.

[0085] In some embodiments, the first surface roughness is greater than the second surface roughness.

[0086] In some embodiments, each of the two or more semiconductor layers includes a horizontal channel surface having a (551) surface orientation.

[0087] In some embodiments, the horizontal channel surface has a <110> crystal direction extending from the first source / drain region and the second source / drain region.

[0088] In some embodiments, each of the two or more semiconductor layers includes a vertical channel surface having a (110) surface orientation.

[0089] In some embodiments, the vertical channel surface has a third surface roughness that is greater than the second surface roughness.

[0090] In some embodiments, the first source / drain region has a bottom surface formed on a (551) surface orientation.

[0091] Some embodiments of the present disclosure provide a method for forming a semiconductor device, comprising: selecting a substrate having a top surface with a (551) surface orientation, epitaxially growing a semiconductor stack from the top surface of the substrate, wherein the semiconductor stack includes two or more first semiconductor layers and two or more second semiconductor layers, and the two or more first semiconductor and the two or more second semiconductor are alternately stacked; forming a fin structure from the semiconductor stack and the substrate; forming a sacrificial gate structure over the fin structure; etching back the fin structure along sidewalls of the sacrificial gate structure; epitaxially growing source / drain regions from the two or more second semiconductor layers; depositing a contact etch stop layer (CESL) over the source / drain regions; depositing an interlayer dielectric (ILD) layer over the CESL; removing the sacrificial gate structure to expose the fin structure; removing the two or more first semiconductor layers; and forming a replacement gate structure around the two or more second semiconductor layers.

[0092] In some embodiments, forming the fin structure includes forming the fin structure along a <110> crystal direction.

[0093] In some embodiments, the method further includes, prior to forming the replacement gate structure, performing a roughness treatment process to reduce a surface roughness of the second semiconductor layers.

[0094] In some embodiments, performing the roughness treatment process includes treating the two or more second semiconductor layers with a plasma.

[0095] In some embodiments, the plasma includes H radicals.

[0096] In some embodiments, epitaxially growing the source / drain regions includes growing a bottom surface from the (551) surface of the substrate.

[0097] The foregoing summary of the features of several embodiments has been presented with sufficient particularity by way of representative example to convey the spirit and scope of the disclosure to those persons skilled in the art. This detailed description is not intended to limit the scope of the disclosure, as described herein, to the particular embodiments described in connection with the representative examples. Those skilled in the art will appreciate that they can readily apply the spirit and scope of the present disclosure as a basis for designing or modifying other processes and structures to produce results and accomplish advantages similar to those achieved by the embodiments presented herein. Those skilled in the art will further appreciate that the spirit and scope of the present disclosure is not limited to any novel features or combinations of features described herein. That is, any aspects or features of the present disclosure can be used in any combination or sub-combination with any other aspect or feature of the present disclosure.

Claims

1. A semiconductor device, comprising: a first source / drain region; a second source / drain region; two or more semiconductor layers disposed between and coupled to the first source / drain region and the second source / drain region, wherein the two or more semiconductor layers are formed on a (551) plane; and a gate structure wrapping the two or more semiconductor layers.

2. The semiconductor device of claim 1, wherein, Each of the two or more semiconductor layers has a <110> crystal direction extending along a direction from the first source / drain region to the second source / drain region.

3. The semiconductor device of claim 2, wherein, Each of the two or more semiconductor layers includes: a top surface; a bottom surface opposite the top surface; and a vertical surface connecting the top surface to the bottom surface, wherein the vertical surface extends from the first source / drain region and the second source / drain region, wherein the top surface has a (551) surface orientation and the vertical surface has a (110) surface orientation.

4. The semiconductor device of claim 3, wherein, A distance between the top surface and the bottom surface is in a range between 2 nm and 10 nm.

5. The semiconductor device of claim 3, wherein, Each of the two or more semiconductor layers further includes: a first end surface connecting the top surface and the bottom surface, wherein the first end surface is in contact with a sidewall of the first source / drain region and the first end surface has a (110) surface orientation.

6. The semiconductor device of claim 5, wherein, Each of the two or more semiconductor layers includes a first end portion adjacent to the first end surface and a center portion in contact with the gate structure, the first end portion having a first surface roughness, the center portion having a second surface roughness different from the first surface roughness.

7. The semiconductor device of claim 6, wherein, The first surface roughness is greater than the second surface roughness.

8. A semiconductor device, comprising: two or more semiconductor layers, wherein each of the two or more semiconductor layers includes a first end portion, a second end portion, a center portion connecting the first end portion and the second end portion, the first end portion having a first surface roughness, the center portion having a second surface roughness different from the first surface roughness; a gate structure wrapping the center portion of the two or more semiconductor layers; a first source / drain region disposed on the first end portion of the two or more semiconductor layers; and a second source / drain region disposed on the second end portion of the two or more semiconductor layers.

9. The semiconductor device of claim 8, wherein, The first surface roughness is greater than the second surface roughness.

10. A method for forming a semiconductor device, comprising: selecting a substrate having a top surface with a (551) surface orientation; epitaxially growing a semiconductor stack from the top surface of the substrate, wherein the semiconductor stack includes two or more first semiconductor layers and two or more second semiconductor layers, and the two or more first semiconductor layers are stacked alternately with the two or more second semiconductor layers; forming a fin structure from the semiconductor stack and the substrate; forming a sacrificial gate structure over the fin structure; etching back the fin structure along sidewalls of the sacrificial gate structure; epitaxially growing source / drain regions from the two or more second semiconductor layers; depositing a contact etch stop layer (CESL) over the source / drain regions; depositing an interlayer dielectric (ILD) layer over the contact etch stop layer; removing the sacrificial gate structure to expose the fin structure; removing the two or more first semiconductor layers; and forming a replacement gate structure around the two or more second semiconductor layers.

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