Semiconductor device and manufacturing method thereof

Abstract

A method of manufacturing a semiconductor device includes forming an interface layer over a channel region and forming a metal-containing layer over the interface layer. After forming the metal-containing layer, a metal silicate layer is formed over the channel region. Portions of the metal silicate layer are removed. After removing portions of the metal silicate layer, a gate dielectric layer is formed over the channel region, and a gate electrode layer is formed over the gate dielectric layer. The embodiment of the invention also relates to a semiconductor device.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to semiconductor devices and methods of manufacturing the same. BACKGROUND

[0002] As the semiconductor industry has progressed to nanometer technology nodes in pursuit of higher device density, higher performance, and lower cost, the challenges posed by manufacturing and design issues have led to the development of field effect transistors (FETs) with three-dimensional designs such as multi-gate field effect transistors including finFETs and gate-all-around (GAA) FETs. In a finFET, a gate electrode is adjacent to three sides of a channel region with a gate dielectric interposed therebetween. Since the gate structure surrounds (encircles) the fin in three surfaces, the transistor essentially has three gates to control the current through the fin or channel region. In a GAAFET, all sides of the channel region are surrounded by a gate electrode, which allows for more complete depletion of the channel region and results in less short channel effects due to steeper subthreshold swing (SS) and less drain induced barrier lowering (DIBL). Further improvements in GAA FETs are needed as transistor sizes continue to shrink to technology nodes below 20-25 nm. SUMMARY

[0003] One aspect of embodiments of the present application provides a method of manufacturing a semiconductor device, comprising: forming an interface layer over a channel region; forming a metal-containing layer over the interface layer; forming a metal silicate layer over the channel region after forming the metal-containing layer; removing a portion of the metal silicate layer; forming a gate dielectric layer over the channel region after removing the portion of the metal silicate layer; and forming a gate electrode layer over the gate dielectric layer.

[0004] Another aspect of embodiments of the present application provides a method of manufacturing a semiconductor device, comprising: forming a plurality of spaced apart nanostructures arranged along a first direction over a substrate; forming an interface layer around each of the plurality of nanostructures; forming a metal-containing layer around the interface layer; annealing the interface layer and the metal-containing layer to form a metal silicate layer around the nanostructures; removing a portion of the metal silicate layer; forming a gate dielectric layer around the nanostructures after removing the portion of the metal silicate layer; and forming a gate electrode layer around the gate dielectric layer.

[0005] Yet another aspect of embodiments of the present application provides a semiconductor device, comprising: an interface layer disposed over a channel region; a metal-containing layer disposed over the interface layer; a gate dielectric layer disposed over the metal-containing layer; and a gate electrode layer disposed over the gate dielectric layer. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figure 1 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present invention;

[0008] Figure 2A A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present invention. Figure 2B It displays its isometric view;

[0009] Figure 3A A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present invention. Figure 3B It displays its isometric view;

[0010] Figure 4 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present invention;

[0011] Figure 5 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present invention;

[0012] Figure 6 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present invention;

[0013] Figure 7 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present invention;

[0014] Figure 8 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present invention;

[0015] Figure 9A A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present invention. Figure 9B A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present invention;

[0016] Figure 10A and Figure 10BCross-sectional views and isometric views of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present invention are shown;

[0017] Figure 11 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present invention;

[0018] Figure 12 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present invention;

[0019] Figure 13 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present invention;

[0020] Figure 14A , Figure 14B , Figure 14C ,and Figure 14D Detailed cross-sectional views of various stages of manufacturing a semiconductor device according to an embodiment of the present invention are shown;

[0021] Figure 15A An atomic layer deposition operation according to an embodiment of the present invention is shown; Figure 15B The atomic layer deposition gas supply curves according to an embodiment of the present invention are shown;

[0022] Figure 16 A schematic diagram of a rapid thermal annealing operation according to an embodiment of the present invention is shown;

[0023] Figure 17 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present invention;

[0024] Figure 18 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present invention;

[0025] Figure 19 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present invention;

[0026] Figure 20 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present invention;

[0027] Figure 21 A cross-sectional view is shown of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present invention;

[0028] Figure 22shows a cross-sectional view of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present application;

[0029] Figure 23 shows a cross-sectional view of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present application;

[0030] Figure 24 shows a cross-sectional view of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present application;

[0031] Figure 25 shows a cross-sectional view of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present application;

[0032] Figure 26 shows a cross-sectional view of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present application;

[0033] Figure 27 shows a cross-sectional view of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present application;

[0034] Figure 28 shows a cross-sectional view of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present application;

[0035] Figure 29 shows a cross-sectional view of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present application;

[0036] Figure 30 shows a cross-sectional view of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present application;

[0037] Figure 31 shows a cross-sectional view of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present application;

[0038] Figure 32 shows a cross-sectional view of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present application;

[0039] Figure 33 shows a cross-sectional view of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present application;

[0040] Figure 34 shows a cross-sectional view of one of the various stages of manufacturing a GAA FET semiconductor device according to an embodiment of the present application;

[0041] Figure 35 Detailed cross-sectional views of a gate dielectric layer / metal-containing layer / semiconductor layer interface are shown in accordance with various embodiments of the present application;

[0042] Figure 36 Cross-sectional views of a GAA FET semiconductor device are shown in accordance with embodiments of the present application;

[0043] Figure 37 Cross-sectional views of a GAA FET semiconductor device are shown in accordance with embodiments of the present application;

[0044] Figure 38 Flow diagrams of methods for fabricating semiconductor devices are shown in accordance with embodiments of the present application;

[0045] Figure 39 Flow diagrams of methods for fabricating semiconductor devices are shown in accordance with embodiments of the present application;

[0046] Figure 40 Flow diagrams of methods for fabricating semiconductor devices are shown in accordance with embodiments of the present application. DETAILED DESCRIPTION

[0047] It should be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the present application. Specific examples of components and arrangements are described below to simplify the present application. These are, of course, merely examples and are not intended to limit the application in any way. For example, the dimensions of the elements can depend on the process conditions and / or the desired characteristics of the device. Additionally, in the following description, a first component or step can be formed over or on a second component or step, which can include embodiments where the first component or step is formed directly on the second component or step, and embodiments where an additional component or step can be formed between the first component or step and the second component or step, such that the first component or step and the second component or step can not be directly in contact. For the purposes of this disclosure, the term "on" can mean directly on, indirectly on, or in contact with, unless otherwise noted. Also, the term "coupled" can mean directly connected to, or connected to through one or more intervening components or steps, unless otherwise noted.

[0048] Also, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's or portion's relationship to another element, component or portion as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Additionally, the term "coupled" can mean either an indirect connection or direct connection through one or more intervening components or steps.

[0049] Additionally, in the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the various implementations. However, various implementations can be practiced without the specific details (e.g., an appropriate configuration and order of operations can be practiced within the scope of the implementations). In other instances, well-known methods, procedures, components, and circuits have not been described in detail since not to unnecessarily obscure aspects of the implementations. Also, in the following detailed description, references are made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific implementations. Although these implementations can be referred to herein using the terminology "one implementation," "an implementation," "a specific implementation," or using a negative disclaimer, such as "not including," it should be understood that there can be multiple implementations and that these are only examples of implementations. The following detailed description is, therefore, not to be taken in a literal sense, and is merely intended to illustrate the generic principles of the various implementations. Furthermore, in the following detailed description, the phrase "one or more of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B, and C), and unless otherwise specified, does not mean one element from A, one element from B, and one element from C. Throughout the disclosure, source and drain can be used interchangeably, and source / drain refers to one or both of source and drain. Source / drain structure can refer to source or drain individually or collectively, depending on the context. In the following embodiments, materials, configurations, dimensions, processes, and / or operations described with respect to one embodiment (e.g., one or more figures) can be employed in other embodiments, and detailed descriptions thereof can be omitted.

[0050] The disclosed embodiments relate to a semiconductor device including a gate-all-around field effect transistor (GAA FET) and a gate structure of a stacked channel FET, and methods of manufacturing the same. However, the disclosed methods and devices are also applicable to planar FETs and other semiconductor devices.

[0051] In embodiments of the disclosure, the thickness of the interface layer between the gate dielectric layer and the channel region of the FET is reduced, thereby reducing the capacitance equivalent thickness without increasing current leakage, which can improve the performance of the FET device.

[0052] Figures 1-13 is a schematic showing various stages of manufacturing a semiconductor FET device according to embodiments of the present disclosure. It should be understood that additional operations can be provided before, during, and after the processes shown by Figures 1-13

[0053] As shown in Figure 1 above a substrate 10, first and second semiconductor layers 20 and 25 are formed alternately. The first and second semiconductor layers 20 and 25 are made of materials having different lattice constants, and can include one or more of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or InP.

[0054] In some embodiments, the first and second semiconductor layers 20 and 25 are made of Si, a Si compound, SiGe, Ge, or a Ge compound. In some embodiments, the first semiconductor layer 20 is made of Si. In some embodiments, the first semiconductor layer 20 is made of Si 1-x ​Ge x made of Si or Si 1-y Ge y made of Si or Si

[0055] In other embodiments, the second semiconductor layer 25 is made of Si 1-x Ge x made of Si or Si 1-y Ge y made of Si or Si

[0056] In some embodiments, the second semiconductor layer 25 is made of the same material as the semiconductor substrate 10.

[0057] In some embodiments, the semiconductor layer 25 has a thickness along the Z direction in a range from about 5 nm to about 60 nm, and a width along the Y direction in a range from about 5 nm to about 80 nm. In some embodiments, the width of the semiconductor layer is greater than the thickness. In certain embodiments, the width is up to two or five times the thickness of the semiconductor nanostructure 25.

[0058] In some embodiments, the substrate 10 includes a single-crystalline semiconductor layer at least on a surface portion thereof. The substrate 10 can include a single-crystalline semiconductor material such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. The substrate 10 can include various regions that have been appropriately doped with impurities (e.g., p-type or n-type conductivity). In some embodiments, the dopants are, for example, boron difluoride (BF2) for n-type FinFETs and phosphorus for p-type FinFETs. In certain embodiments, the substrate 10 is made of crystalline Si.

[0059] The substrate 10 can include one or more buffer layers (not shown) in a surface region thereof. The buffer layers can be used to gradually change the lattice constant from that of the substrate to that of the source / drain structure. The buffer layers can be formed of epitaxially grown single-crystal semiconductor materials such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In a particular embodiment, the substrate 10 includes a silicon germanium (SiGe) buffer layer epitaxially grown on a silicon substrate 10. The germanium concentration of the SiGe buffer layer can increase from 30 atomic percent germanium for the bottom-most buffer layer to 70 atomic percent germanium for the top-most buffer layer.

[0060] The first semiconductor layers 20 and the second semiconductor layers 25 can be formed by one or more epitaxial or epitaxial (epi) processes. Epitaxial processes include chemical vapor deposition (CVD) deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable processes.

[0061] The first semiconductor layers 20 and the second semiconductor layers 25 are alternately epitaxially formed over the substrate 10. The thickness of the first semiconductor layers 20 can be equal to or greater than the thickness of the second semiconductor layers 25, and in some embodiments is in a range of about 4 nm to about 30 nm, and in other embodiments is in a range of about 5 nm to about 15 nm. In some embodiments, the thickness of the second semiconductor layers 25 is in a range of about 4 nm to about 30 nm, and in other embodiments is in a range of about 5 nm to about 15 nm. The thickness of the first semiconductor layers 20 can be the same as or different from the thickness of the second semiconductor layers 25. Although Figure 1 Three first semiconductor layers 20 and three second semiconductor layers 25 are shown in FIG. 1, but the number is not limited to three and can be one, two, or more than three, or less than twenty. In some embodiments, the number of first semiconductor layers 20 is one greater than the number of second semiconductor layers 25 (i.e., the top and bottom layers are first semiconductor layers).

[0062] After the stacked semiconductor layers are formed, the fin structures 29 are formed by using one or more photolithography and etching operations, as shown in FIG. 2. Figure 2A and Figure 2BAs shown in the diagram, the fin structure can be patterned using any suitable method. For example, one or more lithography processes, including dual-patterning or multi-patterning processes, can be used to pattern the fin structure. Typically, dual-patterning or multi-patterning processes combine lithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches compared to those achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structure.

[0063] like Figure 2A As shown, fin structure 29 extends along the X direction and is arranged along the Y direction. The number of fin structures is not limited to... Figure 2A The two shown can be as small as one, and there can be three or more (e.g., Figure 2B (As shown in the figure). In some embodiments, one or more pseudo-fin structures are formed on both sides of the fin structure 29 to improve pattern fidelity during patterning operations. Figure 2A As shown, the fin structure 29 has an upper part consisting of stacked semiconductor layers 20, 25 and a well portion 11 (mesa structure).

[0064] In some embodiments, the width of the upper portion of the fin structure 29 is in the range of about 5 nm to about 80 nm along the Y direction, and in other embodiments, it is in the range of about 10 nm to about 40 nm.

[0065] After forming the fin structure 29, an insulating material layer comprising one or more layers of insulating material is formed over the substrate, such that the fin structure is completely embedded in the insulating layer. The insulating material used for the insulating layer may include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-k dielectric material, formed by LPCVD (low-pressure chemical vapor deposition), plasma-enhanced CVD (PECVD), or flowable CVD. An annealing operation may be performed after forming the insulating layer. Then, a planarization operation, such as chemical mechanical polishing (CMP) and / or etching-back, is performed to expose the upper surface of the uppermost second semiconductor layer 25 from the insulating material layer. In some embodiments, one or more fin pad layers are formed over the fin structure before forming the insulating material layer. In some embodiments, the fin pad layers include a first fin pad layer formed over the substrate 10 and the bottom sidewall of the fin structure 11, and a second fin pad layer formed on the first fin pad layer. In some embodiments, the fin liner is made of silicon nitride or a silicon nitride-based material (e.g., SiON, SiCN, or SiOCN). The fin liner can be deposited using one or more processes, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD), but any acceptable process can be used.

[0066] Then, as Figure 2A As shown, the insulating material layer is recessed to form an insulating isolation layer 15, thereby exposing the upper portion of the fin structure 29. Through this operation, the fin structures 29 are separated from each other by the insulating isolation layer 15, also known as shallow trench isolation (STI). The insulating isolation layer 15 can be formed using suitable dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics such as carbon-doped oxides, very low-k dielectrics such as porous carbon-doped silicon dioxide, polymers such as polyimide, combinations thereof, etc. In some embodiments, the insulating isolation layer 15 is formed by processes such as CVD, flowable CVD (FCVD), or spin-coating glass processes, but any acceptable process can be used.

[0067] In some embodiments, the insulating layer 15 is recessed until the upper portion of the fin structure (well layer) 11 is exposed. In other embodiments, the upper portion of the fin structure 11 is not exposed. The first semiconductor layer 20 is a sacrificial layer that is subsequently partially removed, and the second semiconductor layer 25 is subsequently formed as a semiconductor line or wafer as the channel layer of the GAA FET. In other embodiments, the second semiconductor layer 25 is a sacrificial layer that is subsequently partially removed, and the first semiconductor layer 20 is subsequently formed as a semiconductor line or wafer as the channel layer.

[0068] Figure 2B is an isometric view of the plurality of fin structures 29 separated by the shallow trench isolation 15 after formation of the sacrificial gate dielectric layer 41 over the fin structures 29 and over the shallow trench isolation 15.

[0069] After formation of the isolation insulating layer 15, one or more sacrificial (dummy) gate structures 40 are formed. Figure 3A and Figure 3B shows the structure after formation of the one or more sacrificial gate structures 40 over the exposed fin structures 29. Figure 3B is an isometric view of the structure. The sacrificial gate structures 40 are formed over a portion of the fin structures 29 that will become the channel region. The sacrificial gate structures 40 define the channel region of the GAA FET. The sacrificial gate structures 40 include a sacrificial gate dielectric layer 41 and a sacrificial gate electrode layer 42. The sacrificial gate dielectric layer 41 includes one or more layers of insulating material, such as silicon oxide based material. In one embodiment, silicon oxide formed by CVD is used. In some embodiments, the thickness of the sacrificial gate dielectric layer 41 is in the range of about 1 nm to about 5 nm.

[0070] The sacrificial gate structures 40 are formed by first blanket depositing the sacrificial gate dielectric layer 41 over the fin structures 29. Then, the sacrificial gate electrode layer 42 is blanket deposited over the sacrificial gate dielectric layer and over the fin structures, such that the fin structures are completely embedded in the sacrificial gate electrode layer. In some embodiments, the sacrificial gate electrode layer 42 includes silicon, such as polysilicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate electrode layer is in the range of about 100 nm to about 200 nm. In some embodiments, the sacrificial gate electrode layer is subjected to a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD, including LPCVD and PECVD, PVD, ALD, or other suitable process. Subsequently, a mask layer is formed over the sacrificial gate electrode layer. In some embodiments, the mask layer includes a pad silicon nitride layer 43 and a silicon oxide mask layer 44.

[0071] Next, a patterning operation is performed on the mask layer, and the sacrificial gate electrode layer is patterned into the sacrificial gate structures 40, as shown in Figure 3A and Figure 3B In one embodiment, the sacrificial gate structures include the sacrificial gate dielectric layer 41, the sacrificial gate electrode layer 42 (e.g., polysilicon), the pad silicon nitride layer 43, and the silicon oxide mask layer 44. By patterning the sacrificial gate structures, the stack of the first and second semiconductor layers are partially exposed on opposite sides of the sacrificial gate structures, thereby defining source / drain regions, as shown in Figure 3A and Figure 3BAs shown in the figure. In some embodiments, a sacrificial gate structure is formed above one or more fin structures, but the number of sacrificial gate structures in each fin structure is not limited to one. In some embodiments, two or more sacrificial gate structures are arranged along the X direction. In some embodiments, one or more dummy sacrificial gate structures are formed on both sides of the sacrificial gate structure to improve pattern fidelity.

[0072] After forming the sacrificial gate structure 40, a first capping layer 45 for gate sidewall spacers is formed above the sacrificial gate structure 40, such as... Figure 4 As shown in the figure, the first capping layer 45 is deposited conformally such that it is formed with substantially equal thicknesses on vertical surfaces, such as the sidewalls of the sacrificial gate structure, the horizontal surface, and the top. In some embodiments, the first capping layer 45 has a thickness in the range of about 5 nm to about 20 nm. The first capping layer 45 comprises one or more of silicon nitride, silicon oxide, SiON, SiCN, SiCO, SiOCN, or any other suitable dielectric material. The capping layer 45 can be formed by ALD, CVD, or any other suitable method. In some embodiments, one or more additional capping layers are formed over the first capping layer to form a multilayer gate sidewall spacer.

[0073] Next, as Figure 5 As shown, the first capping layer 45 is anisotropically etched to remove the first capping layer 45 disposed on the source / drain region, while retaining the first capping layer 45 as a sidewall spacer on the side of the sacrificial gate structure 40. Figure 5 A cross-sectional view along the X direction is shown. Then, by using one or more photolithography and etching operations, a stacked structure of the first semiconductor layer 20 and the second semiconductor layer 25 is etched downwards into the source / drain region to form the source / drain space 21. In some embodiments, the substrate 10 (or the bottom of the fin structure 11) is also partially etched to form a mesa structure. In some embodiments, the n-type FET and the p-type FET are fabricated separately; in this case, one type of region for the FET is processed, and the other type of region for the FET is covered by a protective layer such as a silicon nitride layer. In some embodiments, such as Figure 5 As shown, the recessed fin structure has a U-shape. In other embodiments, the recessed fin structure has a V-shape, showing the (111) facet of the silicon crystal. In other embodiments, the recess has an inverted trapezoidal shape or a rectangular shape.

[0074] In some embodiments, the recesses are formed by a dry etching process, which can be anisotropic. The anisotropic etching process can be implemented using a process gas mixture including BF2, Cl2, CH3F, CH4, HBr, O2, Ar, and other etchant gases. The process gas can be activated into a plasma by any suitable method of generating a plasma, such as a transformer coupled plasma (TCP) system, an inductively coupled plasma (ICP) system, a magnetically enhanced reactive ion technique. In some embodiments, the plasma is a remote plasma generated in a separate plasma generation chamber connected to a process chamber. The process gas used in the plasma etching process includes an etchant gas, such as H2, Ar, other gases, or a combination of gases. In some embodiments, a carrier gas such as N2, Ar, He, Xe is combined with the plasma etching process gas using hydrogen (H) radicals. The H radicals can be formed by flowing H2 gas into the plasma generation chamber and igniting a plasma within the plasma generation chamber. In some embodiments, an additional gas such as Ar can be ignited into a plasma within the plasma generation chamber. The H radicals can selectively etch the (100) plane over the (111) plane or the (110) plane. In some cases, the etch rate of the (100) plane is about three times greater than the etch rate of the (111) plane or the (110) plane. Due to this selectivity, the etching by the H radicals can tend to slow down or stop along the (111) plane or the (110) plane of the silicon during the second patterning process.

[0075] Additionally, as shown in FIG. 2A, the first semiconductor layer 20 is etched laterally along the X direction within the source / drain space 21, thereby forming a cavity 22. When the first semiconductor layer 20 is SiGe and the second semiconductor layer 25 is Si, the first semiconductor layer 20 can be selectively etched by using a wet etchant, such as, but not limited to, a mixed solution of H2O2, CH3COOH, and HF, followed by a H2O rinse. In some embodiments, the etching by the mixed solution and the rinsing by water are repeated 10 to 20 times. In some embodiments, the etching time by the mixed solution is in the range of about 1 minute to about 2 minutes. In some embodiments, the mixed solution is used at a temperature in the range of about 60 °C to about 90 °C. In some embodiments, other etchants are used. Figure 6

[0076] In some embodiments, the cavity 22 has a curved end shape (transverse U-shaped cross section) that is convex toward the first semiconductor layer 20. In other embodiments, the cavity 22 has a transverse V-shaped cross section with an apex at the first semiconductor layer 20.

[0077] Next, as shown in FIG. 2B, a second semiconductor layer 25 is formed on the first semiconductor layer 20 and the sidewalls of the cavity 22. The second semiconductor layer 25 can be formed by any suitable deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or a combination thereof. In some embodiments, the second semiconductor layer 25 is formed by a CVD process using a precursor gas, such as SiH4, GeH4, or a combination thereof. In some embodiments, the second semiconductor layer 25 is formed by a PVD process using a target material, such as Si, Ge, or a combination thereof. In some embodiments, the second semiconductor layer 25 is formed by an ALD process using a precursor gas, such as SiH4, GeH4, or a combination thereof. In some embodiments, the second semiconductor layer 25 is formed by a combination of a CVD process and a PVD process. In some embodiments, the second semiconductor layer 25 is formed by a combination of a CVD process and an ALD process. In some embodiments, the second semiconductor layer 25 is formed by a combination of a PVD process and an ALD process. Figure 7 ​As shown, a first insulating layer 30 is formed on the lateral ends of the etched first semiconductor layer 20 and the end faces of the second semiconductor layer 25 in the source / drain space 21, and over the sacrificial gate structure 40. The first insulating layer 30 is formed conformally such that a space is left in the source / drain space 21. The first insulating layer 30 comprises one of silicon nitride and silicon oxide, SiON, SiOC, SiCN, and SiOCN, or any other suitable dielectric material. In some embodiments, the first insulating layer 30 is made of a different material than the sidewall spacer (first cover layer) 45; in other embodiments, it is made of the same material as the sidewall spacer 45. The first insulating layer 30 can be formed by ALD or any other suitable method. By forming the first insulating layer 30, the chamber 22 is completely filled with the first insulating layer 30.

[0078] After the first insulating layer 30 is formed, an etching operation is performed to partially remove the first insulating layer 30, thereby forming the internal spacer 35, such as... Figure 8 As shown in the figure. In some embodiments, the end face of the inner spacer 35 is recessed more than the end face of the second semiconductor layer 25. The recess amount is in the range of about 0.2 nm to about 3 nm, and in other embodiments, in the range of about 0.5 nm to about 2 nm. In other embodiments, the recess amount is less than 0.5 nm and may be equal to zero (i.e., the end face of the inner spacer 35 and the end face of the second semiconductor layer 25 are flush with each other). In some embodiments, an additional insulating layer having a smaller thickness than the first insulating layer 30 is formed before the first insulating layer 30 is formed, so the inner spacer 35 has a two-layer structure. In some embodiments, the width (lateral length) of the inner spacer 35 is not constant.

[0079] In some embodiments, such as Figure 9A As shown, after the formation of the internal spacer 35, a first epitaxial layer 92 is formed on the lateral end face of the second semiconductor layer 25 and the exposed surface of the lower fin structure 11. In some embodiments, the first epitaxial layer 92 includes P- or As-doped Si for an n-type FET and B-doped Si for a P-type FET. In some embodiments, the dopant concentration of the first epitaxial layer 92 is higher than the dopant concentration of the second semiconductor layer 25. In some embodiments, the dopant concentration of the first epitaxial layer 92 gradually increases from the interface between the first epitaxial layer 92 and the second semiconductor layer 25 or the lower fin structure 11 to the source / drain space 21. In some embodiments, the thickness of the deposited first epitaxial layer 92 is in the range of about 1 nm to about 10 nm. In some embodiments, during the epitaxial formation of the first epitaxial layer 92, some dopant elements diffuse into the second semiconductor layer 25 or the lower fin structure 11 to a depth of about 0.5 nm to about 2 nm.

[0080] In some embodiments, after the formation of the inner spacers 35, a first epitaxial layer 92 is formed on the lateral end faces of the second semiconductor layer 25, and an undoped silicon layer 93 is formed on the exposed surfaces of the lower fin structures 11, as shown in Figure 9B In some embodiments, the first epitaxial layer 92 includes Si doped with P or As for n-type FETs, and Si doped with B for p-type FETs. The undoped silicon layer can be formed epitaxially. Although the silicon layer 93 is formed as an undoped layer, in some embodiments, it becomes a non-intentionally doped layer later. Dopants from the later formed source / drain structures can diffuse into the silicon layer 93 from the source / drain structures. Thus, the silicon layer 93 can be referred to as a non-intentionally doped layer.

[0081] Then, as shown in Figure 10A and Figure 10B , source / drain structures 50 are formed in the source / drain spaces 21. Figure 10A is a cross-sectional view along the X direction, Figure 10B is an isometric view of the structure. In some embodiments, the source / drain structures 50 include one or more layers of SiC, SiP, SiAs, and / or SiCP for n-type FETs. In certain embodiments, SiC or SiCP is used. In some embodiments, the source / drain structures 50 include SiGe, SiGeSn, Ge, GeSn, and / or SiSn for p-type FETs. When SiGe is used, in some embodiments, the Ge content is about 60 atomic % to about 80 atomic %. In some embodiments, the source / drain structures 50 are formed by an epitaxial process. In some embodiments, the source / drain structures 50 exert tensile stress on the second semiconductor layer 25 for n-type FETs, and exert compressive stress for p-type FETs.

[0082] Then, an interlayer dielectric (ILD) layer 70 is formed over the source / drain structures 50 and the sacrificial gate structures 40. In some embodiments, a contact etch stop layer 68 is formed before the formation of the ILD layer 70. Next, the ILD layer 70 is planarized by chemical mechanical polishing (CMP) to expose the sacrificial gate electrode layer 42, as shown in Figure 11 The material for the ILD layer 70 can include compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials, such as polymers, including polyimides, can be used for the ILD layer 70. The material for the contact etch stop layer 68 can include silicon nitride, silicon oxide, SiCN, SiON, and SiOCN. In some embodiments, the materials for the ILD layer 70 and the etch stop layer 68 are different from each other, thus having different etch selectivity.

[0083] Then, as shown in Figure 12 the sacrificial gate electrode layer 42 and the sacrificial gate dielectric layer 41 are removed to form a gate space 72. The ILD layer 70 protects the source / drain structures 50 during removal of the sacrificial gate structure. Plasma dry etching and / or wet etching can be used to remove the sacrificial gate structure. When the sacrificial gate electrode layer 42 is polysilicon and the ILD layer 70 is silicon oxide, a wet etchant such as TMAH solution can be used to selectively remove the sacrificial gate electrode layer 42. Thereafter, plasma dry etching and / or wet etching can be used to remove the sacrificial gate dielectric layer 41.

[0084] After the sacrificial gate structure is removed, the first semiconductor layer 20 is removed to form nanosheets, nanowires, or nanostructures (channel regions) of the second semiconductor layer 25 stacked along the Z direction, as shown in Figure 12 As set forth above, the first semiconductor layer 20 can be removed or etched using an etchant that can selectively etch the first semiconductor layer 20 relative to the second semiconductor layer 25. Since the internal spacers 35 are pre-formed, the etching of the first semiconductor layer 20 stops at the internal spacers 35. In other words, the internal spacers 35 can function as an etch stop layer for etching the first semiconductor layer 20.

[0085] After the semiconductor nanowires or nanosheets (channel regions) of the second semiconductor layer 25 are formed, a metal gate structure is formed, as shown in Figure 13 Figure 13 is a cross-sectional view along the X direction. In some embodiments, the structure and / or material of the gate electrode for the n-type GAA FET is different from the structure and / or material of the gate electrode for the p-type GAA FET.

[0086] In certain embodiments, the gate dielectric layer 82 includes one or more layers of dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric material, and / or combinations thereof. In some embodiments of the present disclosure, the high-k dielectric material has a dielectric constant greater than about 7. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, yttrium oxide, yttrium silicon oxide, hafnium oxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, an interface layer 94c including a metal silicate is formed between the channel layer 25 and the gate dielectric layer 82. The formation of the metal silicate-containing interface layer 94c will be described in more detail below.

[0087] ​The gate dielectric layer 82 can be formed by CVD, ALD, or any suitable method. In one embodiment, a highly conformal deposition process such as ALD is used to form the gate dielectric layer to ensure that a gate dielectric layer of uniform thickness is formed around each channel layer. In one embodiment, the gate dielectric layer 82 has a thickness in a range from about 1 nm to about 6 nm.

[0088] In some embodiments, the metal gate structure includes one or more work function adjusting layers 84 disposed above the gate dielectric layer 82. The work function adjusting layer 84 is formed from a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. In some embodiments, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as the work function adjusting layer for a p-channel FET. According to some embodiments, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the work function adjusting layer for an n-channel FET. The work function adjusting layer can be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable process. Additionally, the work function adjusting layer can be formed separately for n-channel FETs and p-channel FETs, which can use different metal layers.

[0089] A gate electrode layer 86 is formed on the work function adjusting layer 84, if present, or on the gate dielectric layer 82 to surround each channel layer. The gate electrode layer 86 includes one or more layers of conductive material, such as polysilicon, aluminum, copper, nickel, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, TiSiN, WCN, TiWN, metal alloys, other suitable materials, and / or combinations thereof.

[0090] The gate electrode layer 86 can be formed by CVD, ALD, electroplating, or other suitable method. The gate electrode layer 86 is also deposited over the upper surface of the I LD layer 70. The gate dielectric layer, work function adjusting layer, and gate electrode layer formed over the I LD layer 70 are then planarized by using, for example, CMP, until the top surface of the I LD layer 70 is exposed. In some embodiments, after the planarization operation, the gate electrode layer is recessed, and a capping insulating layer (not shown) is formed over the recessed gate electrode. In some embodiments, the capping insulating layer includes one or more layers of silicon nitride-based material, such as silicon nitride. The capping insulating layer is formed by depositing an insulating material and then performing a planarization operation.

[0091] Figures 14A-14D is a schematic diagram showing formation of a metal silicate-containing interface layer 94c over the channel region 25 according to embodiments of the application.

[0092] In some embodiments, an interface layer 94a is formed over the exposed portion of the channel region 25 (or semiconductor layer, nanosheet, or nanostructure), as shown in Figure 14A Figure 14A is a detailed view of a portion of the channel region 25 / interface layer 94a interface. While the interface layer 94a is shown disposed over one surface of the channel region 25, it is understood that the interface layer 94a surrounds the upper surface and opposing side surfaces of the channel region in a FinFET device, and surrounds the nanosheet in a GAA FET device. In some embodiments, the interface layer 94a comprises silicon oxide. In some embodiments, the interface layer 94a is formed by thermal oxidation, vapor, or chemical oxidation. In some embodiments, the interface layer 94a is formed by an RCA-1 cleaning operation (a solution comprising water, ammonium hydroxide, and hydrogen peroxide). In other embodiments, the interface layer 94a is formed by a deposition operation such as a CVD operation.

[0093] Subsequently, a metal-containing layer 95a is formed over the interface layer 94a, as shown in Figure 14B In some embodiments, the metal-containing layer 95a is made of a metal oxide, but is not limited to a metal oxide. In some embodiments, the metal-containing layer is made of one or more elemental metals, metal alloys, or metal nitrides. In some embodiments, the metal-containing layer 95a comprises one or more metals selected from the group consisting of Al, Ga, Gd, Hf, La, Lu, Nd, Pr, Ta, Ti, Tm, Y, and Zr. In some embodiments, the metal-containing layer 95a is formed by a deposition process, such as atomic layer deposition, chemical vapor deposition, sputtering, or plating.

[0094] The metal-containing layer 95a and the interface layer 94a are heated so that a reaction occurs between the metal in the metal-containing layer 95a and the silicon in the interface layer 94a to form a metal silicate layer. In some embodiments, during the heating operation, the metal diffuses from the metal-containing layer 95a into the interface layer 94a and the silicon diffuses from the interface layer 94a into the metal-containing layer 95a, thereby forming a metal silicate layer 96 comprising a silicon-containing metal-containing layer 95b and a metal-containing interface layer 94b, as shown in Figure 14C In some embodiments, the heating is performed by a rapid thermal anneal (RTA) operation.

[0095] Subsequently, the silicon-containing metal-containing layer 95b is removed by an etching operation, as shown in Figure 14D ​The etching operation is performed after the formation of the metal-containing layer 95a and the interface layer 94a. In some embodiments, the etching operation is a wet etching operation. In some embodiments, the etching operation is performed using an RCA cleaning operation, including sequential standard clean 1 (SC1) (H2O, H2O2, and NH4OH solutions) and standard clean 2 (SC2) (H2O, H2O2, and HC1 solutions) operations. The chemical composition of the RCA cleaning operation has a high selectivity of etching metal oxides over silicon dioxide. In some embodiments, the etching operation also removes a portion of the metal silicate-containing interface layer 94b. Thus, in some embodiments, the final metal silicate-containing interface layer 94c, or metal silicate layer 94c, is thinner than the initially formed interface layer 94a. In some embodiments, the metal silicate layer 94c has a higher dielectric constant k than the initially formed interface layer 94a. In some embodiments, the metal concentration in the metal silicate layer 94c ranges from about 25 ppm to about 2 at.%. In some embodiments, the metal concentration in the metal silicate layer 94c ranges from about 50 ppm to about 1 at.%.

[0096] Figure 15A An atomic layer deposition operation according to embodiments of the application is shown. In this example, a metal oxide layer is formed over the channel region 25 through a series of operations. An initial H2O pulse to form a monolayer over the channel region is followed by an H2O purge. One or more cycles of pulses and purges of a gaseous metal compound and pulses and purges of H2O are performed to form the desired number of metal oxide layers. Figure 15B An atomic layer deposition gas supply profile according to embodiments of the application is shown. In particular, gas supply profiles for a gaseous metal compound, water, and a nitrogen carrier gas are shown.

[0097] Figure 16 A schematic diagram of a rapid thermal anneal (RTA) operation according to embodiments of the application is shown. The RTA is used to diffuse and react the metal in the metal-containing layer 95a and the silicon in the interface layer 94a to form a metal silicate layer 96. In some embodiments, the interface layer 94a and the metal-containing layer 95a are rapidly heated to a temperature of about 300 °C to about 700 °C using a high intensity infrared lamp or laser. The RTA is performed under vacuum, or in an inert environment such as a nitrogen or argon ambient. In some embodiments, a pyrometer is used to measure the temperature of the substrate and control the duration and temperature of the RTA.

[0098] Figures 17-34 Cross-sectional views of various stages in the fabrication of a GAA FET semiconductor device according to embodiments of the application are shown. It will be understood that for Figures 17-34The shown processes provide additional operations before, during, and after the processes, and can replace or eliminate some of the operations described below. The order of the operations / processes can be interchanged.

[0099] Figure 17 Formation of an interface layer 94a over the channel region 25 is shown. The interface layer 94a can be formed by any suitable technique, including the techniques disclosed herein. Figures 17-34 A GAA FET structure is shown in the middle, but other structures, including FinFETs and planar FETs, are within the scope of the present disclosure. In the case where the device is a GAA FET, the interface layer 94a surrounds the nanosheet or nanostructure 25. As Figures 17-34 As shown in the middle, the GAA FET includes two nanosheet multilayer stacks, but in other embodiments, the GAA FET has one nanosheet multilayer stack, or more than two nanosheet multilayer stacks. The first multilayer stack is in the first region 160a, and the second multilayer stack is in the second region 160b. In some embodiments, the interface layer 94a has a thickness of about 0.3 nm to about 3 nm. In other embodiments, the interface layer 94a has a thickness of about 0.5 nm to about 1.5 nm.

[0100] Subsequently, a metal-containing layer 95a is formed over the interface layer 94a, as shown in the middle. Figure 18 The metal-containing layer 95a can be a pure element layer, an alloy, a metal oxide layer, or a metal nitride layer formed by suitable techniques disclosed herein. The metal can include one or more metals disclosed herein. In some embodiments, the metal-containing layer 95a is a metal oxide layer formed by atomic layer deposition at a temperature range of about 150 °C to about 450 °C. In the case where the semiconductor device structure is a GAAFET, the metal-containing layer 95a surrounds the interface layer 94a. In some embodiments, the metal-containing layer 95a is also formed over the isolation insulating layer 15 between the nanosheet multilayer stacks.

[0101] Subsequently, the metal-containing layer 95a and the interface layer 94a are heated to cause the metal in the metal-containing layer 95a to react with the silicon in the interface layer 94b to form a metal silicate layer 96, as disclosed herein with reference to Figure 14C and as shown in the middle. Figure 19 During the heating, the metal in the metal-containing layer 95a diffuses into the interface layer 94a to form a metal-containing interface layer 94b, and the silicon from the interface layer diffuses into the metal-containing layer to form a silicon-containing metal-containing layer. Thus, the metal silicate layer 96 includes the silicon-containing metal-containing layer 95b and the metal-containing interface layer 94b. In some embodiments, the heating is performed by a rapid thermal anneal (RTA) operation, as disclosed herein.

[0102] Then, as shown in the middle,Figure 20 As shown, a portion of the metal silicate layer 96 is removed to create an interface layer 94c, which comprises the metal silicate disposed above the nanosheet 25. The portion of the metal silicate layer can be removed by wet etching or dry etching. In some embodiments, a wet etching operation is performed using an RCA cleaning operation comprising sequential SC1 and SC2 operations, as referenced herein. Figure 14D As disclosed. In some embodiments, the final interface layer 94c containing metal silicate or (metal silicate layer 94c) is thinner than the initially formed interface layer 94a and has a higher dielectric constant k. In some embodiments, the thinner, higher-k metal silicate layer 94c is also retained above the insulating layer 15. In some embodiments, the metal concentration in the metal silicate layer 94c formed above the insulating layer 15 is the same as the metal concentration in the metal silicate layer 94c formed above the channel region 25.

[0103] In some embodiments, the metal silicate-containing interface layer 94c has a thickness of about 0.3 nm to about 3 nm. In other embodiments, the metal silicate-containing interface layer 94c has a thickness of about 0.5 nm to about 1.5 nm. In other embodiments, the metal silicate-containing interface layer 94c has a thickness of about 0.7 nm to about 1.2 nm. Thicknesses of the metal silicate-containing interface layer 94c outside the disclosed range may result in degraded device performance if the thickness is greater than the disclosed range, and may result in increased current leakage if the thickness is less than the disclosed range.

[0104] In some embodiments, a gate dielectric layer 82 is subsequently formed over the metal silicate-containing interface layer 94c, such as... Figure 21 As shown herein, the gate dielectric layer 82 is made and formed using the gate dielectric materials and techniques disclosed herein. In some embodiments, the gate dielectric layer is made of a high-k material and has a thickness ranging from about 0.5 nm to about 5 nm. In other embodiments, the thickness of the gate dielectric layer ranges from about 1 nm to about 2.5 nm.

[0105] In some embodiments, the hard mask layer 220 and the second mask layer 230 are formed over the first region 160a of the semiconductor device structure, such as Figure 22In some embodiments, the hard mask layer 220 is a nitride or oxide layer conformally formed over the gate dielectric layer 82, and the second mask layer 230 is a carbon or organic material based layer formed over the hard mask layer 220. In some embodiments, the hard mask layer is formed by CVD or ALD. In some embodiments, the second mask layer 230 is a bottom anti-reflective coating (BARC) layer, a photoresist layer, or a spin-on carbon layer. In some embodiments, the hard mask layer 220 and the second mask layer 230 are formed over the surface of both the first region 160a and the second region 160b, and then removed from over the second region 160b using lithography and / or etching techniques.

[0106] In some embodiments, the hard mask 220 is then removed in the second region 160b by etching using a suitable etchant selective to the hard mask material, as shown in Figure 23 . The second mask layer 230 is then removed in the first region using a suitable technique, such as plasma ashing or photoresist stripping, as shown in Figure 24 .

[0107] In some embodiments, it is desirable to tune the threshold voltage (V t ) of the gate electrode. By forming a dipole layer over the channel region of one or more regions of the semiconductor device, but not over other regions, different threshold voltages can be obtained. For example, as shown in Figure 25 , a dipole layer 250 is formed over the dielectric layer 82 in the second region 160b, and over the hard mask layer 220 in the first region 160a. In some embodiments, the dipole layer 250 includes one or more selected from the group consisting of Al2O3, CaO, Ga2O3, La2O3, Lu2O3, MgO, ScO2, Y2O3, and ZnO. After forming the dipole layer 250, the semiconductor device structure is heated to diffuse the dipole layer material into the gate dielectric layer 82 and the channel region 25 of the second region 160b, thereby forming a doped gate dielectric layer 82a and a doped channel region 25a doped with the dipole layer material in the second region. The hard mask layer 220 prevents the dipole layer material from diffusing into the dielectric layer 82 and the channel region 25 of the first region 160a. In some embodiments, the structure is heated by a rapid thermal anneal (RTA) operation disclosed herein. As shown in Figure 26 , in some embodiments, after diffusing the dipole layer material into the gate dielectric layer and the channel region of the second region, the dipole layer 250 and the hard mask layer 220 are removed from the first region 160a by a suitable etching operation. Any remaining dipole layer 250 in the second region can also be removed by the etching operation.

[0108] In some embodiments, a second hard mask layer 260 and a third mask layer 270 are formed over a semiconductor device structure. The second hard mask layer 260 and the third mask layer 270 may be made of the same material and can be referenced herein. Figure 22 The disclosed hard mask layer 220 is formed using the same operation as the second mask layer 230. Then, as... Figure 27 As shown in the document, and as referenced in this article Figure 22 As disclosed, the third mask layer 270 is removed in the second region.

[0109] In some embodiments, the second hard mask layer 260 is removed in the second region 160b, such as Figure 28 As shown herein, the second hard mask layer 260 can be removed using a suitable etching technique. In some embodiments, after removing the second hard mask layer in the second region 160b, the third mask layer 270 is removed in the first region 160a, and a portion of the second hard mask layer 260 is removed in the first region 160a, as shown in the figure. Figure 29 As shown in the figure. In some embodiments, the third mask layer 270 can be removed by a suitable resist stripping operation or by plasma ashing, and a portion of the second hard mask layer 260 can be removed by a suitable etching operation. Figure 29 As shown in some embodiments where the semiconductor device is a GAA FET, a portion of the second hard mask layer 260 between the channel layers 25 is retained after the etching operation.

[0110] In some embodiments, a first power function modulation layer 84a is formed above the gate dielectric layer 82, such as... Figure 30 As shown in the figure, the first work function regulating layer 84a is formed by a monolayer of a conductive material, such as TiN, TaN, TaAlC, TiC, TaC, W, Co, Al, Ni, Ti, TiAl, TiSiN, HfTi, TiSi, TaSi, TiAlC, TiCN, WCN, TiWN, Ta, TaN, or WN. The first work function regulating layer can be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. In some embodiments, the first work function regulating layer has various thicknesses over various nanosheets. For example, in some embodiments, in a multilayer nanosheet stack, the first work function regulating layer has a thickness in the range of about 1.5 nm to about 4.0 nm over the outer nanosheet and a thickness in the range of about 3.0 nm to about 6.0 nm over the inner nanosheet.

[0111] In some embodiments, a fourth mask layer 310 is formed over the first power function adjustment layer 84a. In some embodiments, such as... Figure 31As shown, a fourth mask layer 310 is removed from the first region 160a. The fourth mask layer 310 can be made of any material disclosed herein for the second mask layer 230 and the third mask layer 270. The portion of the fourth mask layer removed from the first region 160a can be removed using any technique disclosed herein for removing the second mask layer 230 and the third mask layer 270. In some embodiments, such as... Figure 32 As shown, the first power function adjustment layer 84a and any remaining third hard mask layer 260 are removed from the first region 160a of the semiconductor device structure. A suitable etching operation is used to remove the first power function adjustment layer 84a and any remaining third hard mask layer 260.

[0112] The fourth mask layer 310 is removed from the second region 160b using any suitable technique for removing the second mask layer 230 or the third mask layer 270. In some embodiments, after removing the fourth mask layer, a second power function modulation layer 84b is formed over the semiconductor device structure, such as... Figure 33 As shown in [the image / document]. Figure 33 In the embodiments shown, the multilayer stack of nanosheets in the first region 160a includes a first work function adjustment layer 84a, while the multilayer stack of nanosheets in the second region 160b includes a first work function adjustment layer 84a and a second work function adjustment layer 84b. The first work function adjustment layer 84a and the second work function adjustment layer 84b are made of different materials. In some embodiments, the second work function adjustment layer 84b is made of TiAl, TiAlN, TiAlC, TiC, TaAlC, or TaC. The second work function adjustment layer can be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. In some embodiments, in the multilayer nanosheet stack, the second work function layer has a thickness of about 1.5 nm to about 4.0 nm above the outer nanosheets, and the thickness above the nanosheets is in the range of about 3.0 nm to about 6.0 nm.

[0113] like Figure 34 As shown, a gate electrode layer 86 is formed above the power function conditioning layers 84a and 84b. As disclosed herein, the gate electrode layer 86 comprises one or more layers of conductive material, such as polysilicon, aluminum, copper, nickel, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, TiSiN, WCN, TiWN, metal alloys, other suitable materials, and / or combinations thereof. Furthermore, the gate electrode layer 86 can be formed by CVD, ALD, electroplating, or other suitable methods.

[0114] Figure 35Detailed cross-sectional views of gate dielectric layer / metal-containing layer / semiconductor layer interfaces according to various embodiments of the application are shown. The relationship between the thickness of the interface layer (IL) and the thickness of the metal silicate layer (M-silicate) is shown. In some embodiments, the thickness of the interface layer ranges from about 0.7 nm to about 1.5 nm, while the thickness of the metal silicate portion of the interface layer is from 0.2 nm to about 0.7 nm. In some embodiments, the metal concentration [M] in the interface layer IL increases as the thickness of the metal silicate portion of the interface layer increases. As shown in Figure 35 some embodiments, the metal concentration [M] increases from about 50 ppm to about 1 at. % as the thickness of the metal-containing portion [M-silicate] increases from about 0.2 nm to about 0.7 nm.

[0115] Figure 36 Cross-sectional views of GAA FET semiconductor devices according to embodiments of the application are shown. In some embodiments, a single work function adjusting layer 84 is formed between the gate dielectric layer 82 and the gate electrode layer 86 in either an n-type FET or a p-type FET. In some embodiments, the work function adjusting layer 84 is made of any of the materials disclosed herein for the first work function adjusting layer 84a and the second work function adjusting layer 84b. In some embodiments, as disclosed herein with reference to Figure 25 and Figure 26 the single work function adjusting layer 84 is formed after diffusing a suitable dipole layer material into the dielectric layer 82 to tune the Vt. In some embodiments, the single work function adjusting layer 84 is formed in both the n-type FET and the p-type FET of a complementary metal-oxide-semiconductor (CMOS) device after diffusing different dipole layer materials into the dielectric layer in the n-type FET and the p-type FET to provide different Vts to each FET.

[0116] Figure 37 Cross-sectional views of GAA FET semiconductor devices according to embodiments of the application are shown. In some embodiments, an n-type FET (NFET) is formed in one region of the semiconductor device structure and a p-type FET (PFET) is formed in another region of the semiconductor device structure. The NFET can have a different work function adjusting layer than the PFET. For example, as shown in Figure 37 the NFET includes a single work function adjusting layer, i.e., the second work function adjusting layer 84b, while the PFET includes the first work function adjusting layer 84a and the second work function adjusting layer 84b disposed above the first work function adjusting layer 84a. The work function adjusting layers 84a, 84b can be made of any of the materials disclosed herein for work function adjusting layers.

[0117] In some embodiments, the semiconductor device structure shown in Figure 34 is formed without the step of forming a dipole layer. In some embodiments, the semiconductor device structure shown inFigure 34 semiconductor device structure shown in FIG. 1 1 1 0 without Figures 27-31 semiconductor device structure shown in FIG. 1 1 1 0 without Figures 27-31 intervening steps shown in FIG. 1 1 1 0.

[0118] Figure 38 A flowchart of a method 3800 for fabricating a semiconductor device according to an embodiment of the present application is shown. The method for fabricating a semiconductor device includes operation S3810 of forming an interface layer 94a over the channel region 25. In operation S3820, a metal-containing layer 95a is formed over the interface layer 94a. Then, in operation S3830, a metal silicate layer 96 is formed over the channel region 25. The metal silicate layer 96 is formed by a heating operation, such as a rapid thermal anneal. In operation S3840, portions of the metal silicate layer 96 are removed. A suitable etching operation is performed to remove portions of the metal silicate layer 96. In operation S3850, a gate dielectric layer 82 is formed over the channel region 25. The gate dielectric layer 82 is formed over portions of the metal silicate layer 94c that remain over the channel region 25 after the portions of the metal silicate layer 96 are removed. In operation S3860, a gate electrode layer 86 is formed over the gate dielectric layer 82. In some embodiments, a dipole layer 250 is formed over the gate dielectric layer 82 in operation S3870 before the gate electrode layer 86 is formed.

[0119] Figure 39 A flowchart of a method 3900 for fabricating a semiconductor device according to an embodiment of the present application is shown. The method for fabricating a semiconductor device includes operation S3910 of forming a plurality of spaced apart nanostructures 25 arranged along a first direction over a substrate 10. In operation S3920, an interface layer 94a is formed around each nanostructure 25. In operation S3930, a metal-containing layer 95a is formed around each interface layer 94a. In operation S3940, the interface layer 94a and the metal-containing layer 95a are annealed to form a metal silicate layer 96 around each nanostructure 25. In operation S3950, portions of the metal silicate layer 96 are removed. In operation S3960, a gate dielectric layer 82 is formed around each nanostructure 25 after the portions of the metal silicate layer 96 are removed, and in operation S3970, a gate electrode layer 86 is formed around each gate dielectric layer 82. In some embodiments, the method includes forming a dipole layer 250 over the gate dielectric layer 82 in operation S3980 before the gate electrode layer 86 is formed.

[0120] Figure 40A flowchart of a method 4000 for fabricating a semiconductor device according to an embodiment of the application is shown. The method of fabricating a semiconductor device includes an operation S4005 of forming a first multilayer stack and a second multilayer stack over a substrate 10. The first multilayer stack and the second multilayer stack are spaced apart from each other along a first direction. An insulating layer 15 is disposed between the spaced apart first multilayer stack and the second multilayer stack, and the first multilayer stack and the second multilayer stack include a plurality of spaced apart nanosheets 25 arranged along a second direction perpendicular to the first direction. In operation S4010, an oxide layer 94a is formed around each nanosheet. In operation S4015, a metal-containing layer 95a is formed around each oxide layer 94a. In operation S4020, portions of the oxide layer 94a and the metal-containing layer 95a are converted to metal silicate layers 94b, 95b. In operation S4025, portions of the metal-containing layers 94b, 95b are removed. In operation S4030, after the portions of the metal-containing layers are removed, a gate dielectric layer 82 is formed around each nanosheet 25, and in operation S4035, a gate electrode layer 86 is formed around each gate dielectric layer 82. In some embodiments, the method includes an operation S4040 of forming a metal-containing layer 95a over the insulating layer 15. In some embodiments, the method includes an operation S4045 of forming a hardmask layer 220 over the gate dielectric layer 82 in the first multilayer stack before forming the gate electrode layer 86. In some embodiments, the method includes an operation S4050 of forming a dipole layer 250 over the hardmask layer 220 in the first multilayer stack and over the gate dielectric layer 82 in the second multilayer stack before forming the gate electrode layer 86.

[0121] Additional operations can be performed on the structures of Figure 13 、 Figure 34 、 Figure 36 、and Figure 37 including forming electrical contacts to the gate electrodes and source / drain regions, including silicide layers. Additional insulating layers and metal wiring layers, including interconnects and vias, can be formed over the structures of Figure 13 、 Figure 34 、 Figure 36 、and Figure 37 . The structures of Figure 13 、 Figure 34 、 Figure 36 、and Figure 37 may be part of a larger integrated circuit, including additional devices and components.

[0122] In embodiments of the present disclosure, the thickness of the interface layer between the gate dielectric layer and the channel region of the FET is reduced, thereby reducing the capacitance equivalent thickness without increasing current leakage, and the dielectric constant of the interface layer is increased, thereby allowing improved performance of the FET device. Embodiments of the present disclosure also allow for local control of the voltage threshold Vt of various transistors in a semiconductor device.

[0123] It should be appreciated that not necessarily all advantages are discussed, nor necessarily the same advantages are achieved with all embodiments or examples, and other embodiments or examples can provide different advantages.

[0124] One embodiment of the present disclosure is a method of fabricating a semiconductor device, including forming an interface layer over a channel region, forming a metal-containing layer over the interface layer. After forming the metal-containing layer, a metal silicate layer is formed over the channel region. A portion of the metal silicate layer is removed. After removing the portion of the metal silicate layer, a gate dielectric layer is formed over the channel region, and a gate electrode layer is formed over the gate dielectric layer. In embodiments, the metal-containing layer includes a metal oxide or a metal nitride. In embodiments, forming the metal silicate layer includes annealing the interface layer and the metal-containing layer. In embodiments, the metal-containing layer is formed by atomic layer deposition. In embodiments, the metal-containing layer includes one or more metals selected from the group consisting of Al, Ga, Gd, Hf, La, Lu, Nd, Pr, Ta, Ti, Tm, Y, and Zr. In embodiments, the gate dielectric layer includes one or more selected from the group consisting of hafnium oxide, zirconium oxide, aluminum oxide, hafnium zirconium oxide, yttrium oxide, and yttrium silicon oxide. In embodiments, the method includes forming a dipole layer over the gate dielectric layer prior to forming the gate electrode layer. In embodiments, the dipole layer includes one or more selected from the group consisting of aluminum oxide, calcium oxide, gallium oxide, lutetium oxide, magnesium oxide, scandium oxide, yttrium oxide, and zinc oxide. In embodiments, the channel region includes Si or SiGe.

[0125] Another embodiment of the present disclosure is a method of fabricating a semiconductor device, including forming a plurality of spaced apart nanostructures arranged along a first direction over a substrate, and forming an interface layer around each of the plurality of nanostructures. A metal-containing layer is formed around the interface layer. The interface layer and the metal-containing layer are annealed to form a metal silicate layer around the nanostructures. Portions of the metal silicate layer are removed. After the portions of the metal silicate layer are removed, a gate dielectric layer is formed around the nanostructures, and a gate electrode layer is formed around the gate dielectric layer. In an embodiment, the metal-containing layer includes a metal oxide or a metal nitride. In an embodiment, the metal-containing layer includes one or more metals selected from the group consisting of Al, Ga, Gd, Hf, La, Lu, Nd, Pr, Ta, Ti, Tm, Y, and Zr. The gate dielectric layer includes one or more selected from the group consisting of hafnium oxide, zirconium oxide, aluminum oxide, hafnium zirconium oxide, yttrium oxide, and yttrium silicon oxide. In an embodiment, the method includes forming a dipole layer over the gate dielectric layer prior to forming the gate electrode layer. In an embodiment, the nanostructures include Si or SiGe.

[0126] Another embodiment of the present disclosure is a method of fabricating a semiconductor device, including forming a first multi-layer stack and a second multi-layer stack over a substrate. The first multi-layer stack and the second multi-layer stack are spaced apart from each other along a first direction. An insulating layer is disposed between the spaced apart first multi-layer stack and the second multi-layer stack, and the first multi-layer stack and the second multi-layer stack include a plurality of spaced apart nanosheets arranged along a second direction perpendicular to the first direction. An oxide layer is formed around each nanosheet. A metal-containing layer is formed around each oxide layer. Portions of the oxide layer and the metal-containing layer are converted to a metal silicate layer. Portions of the metal-containing layer are removed. After the portions of the metal-containing layer are removed, a gate dielectric layer is formed around each nanosheet, and a gate electrode layer is formed around each gate dielectric layer. In an embodiment, the method includes forming the metal-containing layer over the insulating layer. In an embodiment, the method includes forming a hard mask layer over the gate dielectric layer in the first multi-layer stack prior to forming the gate electrode layer. In an embodiment, the method includes forming a dipole layer over the hard mask layer in the first multi-layer stack and over the gate dielectric layer in the second multi-layer stack prior to forming the gate electrode layer. In an embodiment, the metal-containing layer includes one or more metals selected from the group consisting of Al, Ga, Gd, Hf, La, Lu, Nd, Pr, Ta, Ti, Tm, Y, and Zr.

[0127] Another embodiment of the present disclosure is a semiconductor device comprising: an interface layer disposed over a channel region; and a metal-containing layer disposed over the interface layer. A gate dielectric layer is disposed over the metal-containing layer, and a gate electrode layer is disposed over the gate dielectric layer. In embodiments, the metal-containing layer comprises a metal silicate. In embodiments, the metal-containing layer comprises one or more metals selected from the group consisting of Al, Ga, Gd, Hf, La, Lu, Nd, Pr, Ta, Ti, Tm, Y, and Zr. In embodiments, the concentration of the metal in the metal-containing layer ranges from 25 ppm to 2 at.%. In embodiments, the concentration of the metal in the metal-containing layer ranges from 50 ppm to 1 at.%. In embodiments, the thickness of the metal-containing layer ranges from 0.1 nm to 1.5 nm. In embodiments, the thickness of the metal-containing layer ranges from 0.2 nm to 0.7 nm. In embodiments, the semiconductor device comprises one or more work function adjusting layers disposed between the gate dielectric layer and the gate electrode layer. In embodiments, a first work function adjusting layer comprises W, Co, Ni, Ti, TiN, TiSiN, WCN, TiWN, Ta, TaN, or WN. In embodiments, a second work function adjusting layer is disposed over the first work function adjusting layer, and the second work function adjusting layer comprises TiAl, TiAlN, TiAlC, TiC, TaAlC, or TaC.

[0128] Another embodiment of the present disclosure is a semiconductor device comprising a plurality of spaced-apart nanostructures arranged along a first direction over a substrate. An interface layer surrounds each nanostructure. A metal-containing layer surrounds each interface layer. A gate dielectric layer surrounds each metal-containing layer, and a gate electrode layer surrounds each gate dielectric layer. In embodiments, the metal-containing layer comprises a metal silicate. In embodiments, the metal-containing layer comprises one or more metals selected from the group consisting of Al, Ga, Gd, Hf, La, Lu, Nd, Pr, Ta, Ti, Tm, Y, and Zr. In embodiments, the concentration of the metal in the metal-containing layer ranges from 25 ppm to 2 at.%. In embodiments, the thickness of the metal-containing layer ranges from 0.1 nm to 1.5 nm.

[0129] Another embodiment of the present disclosure is a semiconductor device including a first multilayer stack and a second multilayer stack disposed above a substrate. The first multilayer stack and the second multilayer stack are spaced apart from each other along a first direction, and an insulating layer is disposed between the spaced apart first multilayer stack and the second multilayer stack. The first multilayer stack and the second multilayer stack include a plurality of spaced apart nanosheets arranged along a second direction perpendicular to the first direction. An oxide layer surrounds each nanosheet. A metal-containing layer surrounds each oxide layer. A gate dielectric layer surrounds each metal-containing layer, and a gate electrode layer surrounds each gate dielectric layer. In an embodiment, the nanosheet includes Si or SiGe. In an embodiment, the metal-containing layer is disposed above the insulating layer. In an embodiment, the metal-containing layer includes one or more metals selected from the group consisting of Al, Ga, Gd, Hf, La, Lu, Nd, Pr, Ta, Ti, Tm, Y, and Zr. In an embodiment, a concentration of the metal in the metal-containing layer ranges from 25 ppm to 2 at.%. In an embodiment, the semiconductor device includes a first work function adjusting layer disposed between the gate dielectric layer and the gate electrode layer of the first multilayer stack and the second multilayer stack, and a second work function adjusting layer disposed above the first work function adjusting layer of the first multilayer stack, wherein the first work function adjusting layer, the second work function adjusting layer, and the gate electrode layer are made of different materials.

[0130] The foregoing summary of features of several embodiments has been presented for the purposes of illustration so that one skilled in the art can better understand the various aspects of the disclosure. One skilled in the art should appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. One skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that various changes, substitutions, and alterations can be made thereto without departing from the spirit and scope of the disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: An interface layer is formed above the channel area; A metal-containing layer is formed above the interface layer; After the metal-containing layer is formed, a metal silicate layer is formed above the channel region; Remove a portion of the metal silicate layer; After removing the portion of the metal silicate layer, a gate dielectric layer is formed over the channel region; as well as A gate electrode layer is formed above the gate dielectric layer.

2. The method according to claim 1, wherein, The metal-containing layer includes metal oxides or metal nitrides.

3. The method according to claim 1, wherein, The formation of the metal silicate layer includes annealing the interface layer and the metal-containing layer.

4. The method according to claim 1, wherein, The metal-containing layer is formed by atomic layer deposition.

5. The method according to claim 1, wherein, The metal-containing layer comprises one or more metals selected from the group consisting of Al, Ga, Gd, Hf, La, Lu, Nd, Pr, Ta, Ti, Tm, Y, and Zr.

6. The method according to claim 1, wherein, The gate dielectric layer comprises one or more selected from the group consisting of hafnium oxide, zirconium oxide, aluminum oxide, hafnium zirconium oxide, yttrium oxide, and yttrium silicon oxide.

7. The method according to claim 1, further comprising: A dipole layer is formed over the gate dielectric layer before the gate electrode layer is formed.

8. The method according to claim 7, wherein, The dipole layer comprises one or more selected from the group consisting of aluminum oxide, calcium oxide, gallium oxide, lutetium oxide, magnesium oxide, scandium oxide, yttrium oxide, and zinc oxide.

9. A method for manufacturing a semiconductor device, comprising: Multiple spaced nanostructures arranged along a first direction are formed above the substrate; An interface layer is formed around each of the plurality of nanostructures; A metal-containing layer is formed around the interface layer; The interface layer and the metal-containing layer are annealed to form a metal silicate layer around the nanostructure; Remove a portion of the metal silicate layer; After removing a portion of the metal silicate layer, a gate dielectric layer is formed around the nanostructure; as well as A gate electrode layer is formed around the gate dielectric layer.

10. A semiconductor device, comprising: The interface layer is positioned above the channel area; A metal layer is disposed above the interface layer; A gate dielectric layer is disposed above the metal-containing layer; as well as A gate electrode layer is disposed above the gate dielectric layer.

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