Semiconductor device including dedicated gate electrode structure

Abstract

A semiconductor device includes: a first source / drain structure and a second source / drain structure spaced apart from each other; a first channel structure connected to the first source / drain structure; a second channel structure connected to the second source / drain structure; the separation insulating layer is arranged between the first source / drain structure and the second source / drain structure and between the first channel structure and the second channel structure; and a gate electrode overlapping the separation insulating layer, the first channel structure, and the second channel structure. The gate electrode includes a first channel overlapping portion overlapping the first channel structure, a second channel overlapping portion overlapping the second channel structure, and a bridge portion disposed between the first channel overlapping portion and the second channel overlapping portion.

Description

Cross Reference to Related Applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0064011, filed on May 16, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The disclosure relates to a semiconductor device, and particularly, to a semiconductor device including a dedicated gate electrode structure. BACKGROUND

[0003] A semiconductor device generally includes an integrated circuit composed of a metal oxide semiconductor field effect transistor (MOS-FET). In order to meet the increasing demand for a semiconductor device having a small pattern size and reduced design rules, the MOS-FET is being scaled down in size. The scaling down of the MOS-FET can cause the operating characteristics of the semiconductor device to deteriorate. Therefore, various studies are being conducted to overcome the technical limitations associated with the scaling down of the semiconductor device and to provide a high-performance semiconductor device. SUMMARY

[0004] A semiconductor device includes a first source / drain structure and a second source / drain structure spaced apart from each other, a first channel structure connected to the first source / drain structure, a second channel structure connected to the second source / drain structure, a separation insulating layer disposed between the first source / drain structure and the second source / drain structure and between the first channel structure and the second channel structure, and a gate electrode overlapping the separation insulating layer, the first channel structure, and the second channel structure. The gate electrode includes a first channel overlap portion overlapping the first channel structure, a second channel overlap portion overlapping the second channel structure, and a bridge portion disposed between the first channel overlap portion and the second channel overlap portion. A height of a top surface of the bridge portion is higher than a height of a top surface of the first channel overlap portion and a height of a top surface of the second channel overlap portion.

[0005] A semiconductor device includes a first source / drain structure and a second source / drain structure spaced apart from each other, a first channel structure connected to the first source / drain structure, a second channel structure connected to the second source / drain structure, a separation insulating layer disposed between the first source / drain structure and the second source / drain structure and between the first channel structure and the second channel structure, and a gate electrode overlapping the separation insulating layer, the first channel structure, and the second channel structure. The gate electrode includes a first channel overlap portion overlapping the first channel structure, a second channel overlap portion overlapping the second channel structure, and a bridge portion connecting the first channel overlap portion to the second channel overlap portion. The bridge portion includes a first portion connected to the first channel overlap portion, a second portion connected to the second channel overlap portion, and a third portion disposed between the first portion and the second portion. The third portion of the bridge portion is disposed at a height higher than the separation insulating layer, and the third portion of the bridge portion overlaps the separation insulating layer.

[0006] A semiconductor device includes a first source / drain structure and a second source / drain structure spaced apart from each other, a first channel structure connected to the first source / drain structure, a second channel structure connected to the second source / drain structure, a first active contact disposed on the first source / drain structure, a second active contact disposed on the second source / drain structure, a separation insulating layer disposed between the first source / drain structure and the second source / drain structure, between the first channel structure and the second channel structure, and between the first active contact and the second active contact, a gate electrode overlapping the separation insulating layer, the first channel structure, and the second channel structure, a gate insulating layer disposed between the gate electrode and the separation insulating layer, a cap insulating layer disposed on the first active contact, a gate connection pattern disposed on the gate electrode, a bridge insulating layer in contact with the gate electrode, the gate connection pattern, and the cap insulating layer, and a contact connection pattern disposed on the first active contact. The gate electrode includes a bridge portion in contact with the bridge insulating layer and the gate connection pattern. A width of the bridge portion increases as a height decreases.

[0007] A method of manufacturing a semiconductor device includes forming a semiconductor layer and a sacrificial semiconductor layer, forming a separation insulating layer to penetrate the semiconductor layer and the sacrificial semiconductor layer, etching the semiconductor layer and the sacrificial semiconductor layer, forming a semiconductor pattern by etching the semiconductor layer, a first source / drain structure and a second source / drain structure spaced apart from each other with the separation insulating layer interposed therebetween, removing the sacrificial semiconductor layer, forming a gate electrode to overlap the semiconductor pattern, forming a bridge sacrificial pattern on the gate electrode, etching the bridge sacrificial pattern to form a gate sacrificial pattern, removing the gate sacrificial pattern to form a first space, and forming a gate connection pattern in the first space. BRIEF DESCRIPTION OF DRAWINGS

[0008] A more complete understanding of the present disclosure and the many attendant aspects thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, in which:

[0009] FIG. 1A is a plan view showing a semiconductor device according to an embodiment of the present inventive concept.

[0010] FIG. 1B is a cross-sectional view taken along line A-A' of FIG. 1A .

[0011] FIG. 1C is a cross-sectional view taken along line B-B' of FIG. 1A .

[0012] FIG. 1D is a cross-sectional view taken along line C-C' of FIG. 1A .

[0013] FIG. 1E is an enlarged cross-sectional view showing a portion 'El' of FIG. 1B .

[0014] FIG. 1F is an enlarged cross-sectional view showing a portion 'E2' of FIG. 1C .

[0015] FIG. 2A , FIG. 2B , FIG. 2C , FIG. 3A , FIG. 3B , FIG. 4A , FIG. 4B , FIG. 4C , FIG. 5A , FIG. 5B , FIG. 5C , FIG. 6A , FIG. 6B , FIG. 6C , FIG. 7A , FIG. 7B , FIG. 7C , FIG. 7D , FIG. 8A , FIG. 8B , FIG. 8C , FIG. 9A , FIG. 9B , FIG. 9C , FIG. 9D , FIG. 10A , FIG. 10B , FIG. 10C , FIG. 11A , FIG. 11B and FIG. 11C are diagrams showing a method of manufacturing a semiconductor device according to an embodiment of the present inventive concept.

[0016] FIG. 12 is an enlarged cross-sectional view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0017] FIG. 13 is an enlarged cross-sectional view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0018] FIG. 14 is an enlarged cross-sectional view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0019] FIG. 15 is an enlarged cross-sectional view illustrating a semiconductor device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0020] FIG. 1A is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept. FIG. 1B is a cross-sectional view taken along line A-A' of FIG. 1A . FIG. 1C is a cross-sectional view taken along line B-B' of FIG. 1A . FIG. 1D is a cross-sectional view taken along line C-C' of FIG. 1A . FIG. 1E is an enlarged cross-sectional view illustrating a portion 'E1' of FIG. 1B . FIG. 1F is an enlarged cross-sectional view illustrating a portion 'E2' of FIG. 1C .

[0021] Referring to FIG. 1A , FIG. 1B , FIG. 1C and FIG. 1D , the semiconductor device can include a substrate 10. Logic transistors constituting a logic circuit can be disposed on the substrate 10. The substrate 10 can be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. In an embodiment, the semiconductor substrate can be formed of silicon, germanium, silicon-germanium, GaP, or GaAs, or otherwise include silicon, germanium, silicon-germanium, GaP, or GaAs.

[0022] The substrate 10 can be a plate-shaped structure extending in a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 are different from each other. In an embodiment, the first direction D1 and the second direction D2 can be horizontal directions orthogonal to each other.

[0023] The substrate 10 can include active patterns AP1 and AP2. The active patterns AP1 and AP2 can extend in the second direction D2. The active patterns AP1 and AP2 can be spaced apart from each other in the first direction D1. The active patterns AP1 and AP2 can be upper portions of the substrate 10 that protrude in the third direction D3. The third direction D3 can be non-parallel to the first direction D1 and the second direction D2. In embodiments, the third direction D3 can be a vertical direction that is orthogonal to the first direction D1 and the second direction D2.

[0024] The active patterns AP1 and AP2 can include a first active pattern AP1 and a second active pattern AP2. The first active pattern AP1 and the second active pattern AP2 can be two active patterns AP1 and AP2 that are adjacent to each other in the first direction D1. The first active pattern AP1 and the second active pattern AP2 can be spaced apart from each other in the first direction D1.

[0025] The device isolation layers 11 can be disposed on the substrate 10. The first active pattern AP1 and the second active pattern AP2 can be disposed between the device isolation layers 11, which are spaced apart from each other in the first direction D1. The device isolation layers 11 can include an insulating material. In embodiments, the device isolation layers 11 can be formed of, or otherwise include, an oxide material.

[0026] The channel structures CH1 and CH2 can overlap the active patterns AP1 and AP2 in the third direction D3. The channel structures CH1 and CH2 can include first channel structures CH1 that overlap the first active patterns AP1 in the third direction D3 and second channel structures CH2 that overlap the second active patterns AP2 in the third direction D3.

[0027] The channel structures CH1 and CH2 can overlap each of the active patterns AP1 or AP2 in the third direction D3 and can be spaced apart from each other in the second direction D2. For example, the first channel structures CH1 that overlap the first active patterns AP1 in the third direction D3 can be spaced apart from each other in the second direction D2.

[0028] Each of the first channel structures CH1 can include a first semiconductor pattern SP1 arranged in the third direction D3. As used herein, the phrase“arranged in a direction” means that an element or group has a largest dimension in a given direction. The first semiconductor patterns SP1 can be spaced apart from each other in the third direction D3. The first semiconductor patterns SP1 can overlap each other in the third direction D3. Each of the second channel structures CH2 can include a second semiconductor pattern SP2 arranged in the third direction D3. The second semiconductor patterns SP2 can be spaced apart from each other in the third direction D3. The second semiconductor patterns SP2 can overlap each other in the third direction D3.

[0029] The number of semiconductor patterns SP1 and SP2 in each channel structure CH1 or CH2 is not necessarily limited to the number in the illustrated example. In embodiments, the number of semiconductor patterns SP1 and SP2 in each channel structure CH1 or CH2 can be less than or equal to 3, or can be greater than or equal to 5.

[0030] In embodiments, the first semiconductor patterns SP1 and the second semiconductor patterns SP2 can be formed of, or otherwise include, silicon (Si). For example, the first semiconductor patterns SP1 and the second semiconductor patterns SP2 can be formed of, or otherwise include, crystalline silicon.

[0031] The source / drain structures SS can be disposed on the active patterns AP1 and AP2. The source / drain structures SS disposed on each active pattern AP1 or AP2 can be spaced apart from each other in the second direction D2. The source / drain structures SS can include first source / drain structures SS1 on the first active pattern AP1 and second source / drain structures SS2 on the second active pattern AP2. The first source / drain structures SS1 can be connected to the first semiconductor patterns SP1 of the first channel structures CH1. The second source / drain structures SS2 can be connected to the second semiconductor patterns SP2 of the second channel structures CH2. Each of the source / drain structures SS can include a lower source / drain pattern LSD and an upper source / drain pattern USD.

[0032] The lower source / drain pattern LSD can be disposed on or in the active pattern AP1 or AP2. The lower source / drain pattern LSD can be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. In embodiments, the lower source / drain pattern LSD can be formed of, or otherwise include, silicon (Si) or silicon-germanium (SiGe).

[0033] The upper source / drain pattern USD can be disposed on the active pattern AP1 or AP2. The upper source / drain pattern USD can be disposed on the lower source / drain pattern LSD. The upper source / drain pattern USD can be disposed between the channel structures CH1 and CH2 adjacent to each other along the second direction D2. The upper source / drain pattern USD can be connected to the semiconductor patterns SP1 and SP2 of the channel structure CH1 or CH2.

[0034] The upper source / drain pattern USD can be an epitaxial pattern formed by a selective epitaxial growth process. In an embodiment, the upper source / drain pattern USD can be formed of, or otherwise include, silicon (Si) or silicon-germanium (SiGe).

[0035] A separation insulating layer 20 can be disposed. The separation insulating layer 20 can extend in the second direction D2. The separation insulating layers 20 can be spaced apart from each other in the first direction D1. One of the separation insulating layers 20 can be disposed between the first active pattern AP1 and the second active pattern AP2, between the first channel structure CH1 and the second channel structure CH2, and between the first source / drain structure SS1 and the second source / drain structure SS2. The first active pattern AP1 and the second active pattern AP2 can be spaced apart from each other in the first direction D1 with the separation insulating layer 20 interposed therebetween. The first channel structure CH1 and the second channel structure CH2 can be spaced apart from each other in the first direction D1 with the separation insulating layer 20 interposed therebetween. The first source / drain structure SS1 and the second source / drain structure SS2 can be spaced apart from each other in the first direction D1 with the separation insulating layer 20 interposed therebetween. The separation insulating layer 20 can include an insulating material. In an embodiment, the separation insulating layer 20 can include a nitride material.

[0036] A gate electrode GE can be disposed. The gate electrode GE can extend in the first direction D1. One of the gate electrodes GE can overlap the first channel structure CH1, the second channel structure CH2, and the separation insulating layer 20 between the first channel structure CH1 and the second channel structure CH2 in the third direction D3. The gate electrode GE can be disposed between the upper source / drain patterns USD adjacent to each other along the second direction D2.

[0037] The gate electrode GE and the semiconductor patterns SP1 and SP2 can constitute a three-dimensional field effect transistor (e.g., MBCFET or GAAFET). The gate electrode GE can include a conductive material. In an embodiment, the gate electrode GE can include a barrier layer and a conductive layer formed of, or otherwise including, different materials from each other.

[0038] A gate insulating layer GI can be provided. The gate insulating layer GI can separate the gate electrode GE from the semiconductor patterns SP1 and SP2 of the channel structure CH1 or CH2. The gate insulating layer GI can be provided between the gate electrode GE and the semiconductor pattern SP1 or SP2 of the channel structure CH1 or CH2. The gate insulating layer GI can separate the gate electrode GE from the separation insulating layer 20. The gate insulating layer GI can be provided between the gate electrode GE and the separation insulating layer 20. The gate insulating layer GI can be in contact with the device isolation layer 11 and the separation insulating layer 20. The gate insulating layer GI can include an insulating material. In an embodiment, the gate insulating layer GI can include silicon oxide.

[0039] A gate spacer GS can be provided. The gate spacer GS can be provided on both sides of the gate electrode GE. The gate spacer GS can include an insulating material.

[0040] A cover insulating layer 15 can be provided. The cover insulating layer 15 can be provided on the upper source / drain pattern USD, the separation insulating layer 20, and the gate spacer GS. The cover insulating layer 15 can include an insulating material. An insulating layer 13 can be provided on the cover insulating layer 15. The insulating layer 13 can include an insulating material.

[0041] A gate cut insulating layer 14 can be provided. The gate cut insulating layer 14 can be provided between the gate electrodes GE spaced apart from each other in the first direction D1. Side surfaces of the gate cut insulating layer 14 can be in contact with the gate electrode GE, the device isolation layer 11, the cover insulating layer 15, and the insulating layer 13.

[0042] An active contact AC can be provided on the upper source / drain pattern USD of the source / drain structure SS1 and SS2. The active contact AC can include a first active contact AC1 on the first source / drain structure SS1 and a second active contact AC2 on the second source / drain structure SS2. The active contact AC can penetrate the cover insulating layer 15 and the insulating layer 13. The separation insulating layer 20 can be provided between the first active contact AC1 and the second active contact AC2. The first active contact AC1 and the second active contact AC2 can be spaced apart from each other in the first direction D1 with the separation insulating layer 20 interposed therebetween. The active contact AC can include a conductive material.

[0043] A capping insulating layer 21 can be provided on the active contact AC and the gate electrode GE. The capping insulating layer 21 can be in contact with the gate cut insulating layer 14 and the separation insulating layer 20. The capping insulating layer 21 can include an insulating material.

[0044] An upper insulating layer 22 can be provided on the capping insulating layer 21. The upper insulating layer 22 can include an insulating material.

[0045] A bridge insulating layer 23 can be disposed on the gate electrode GE. The bridge insulating layer 23 can be in contact with the gate electrode GE, the cap insulating layer 21, and the upper insulating layer 22. The bridge insulating layer 23 can be disposed between the gate electrode GE and the upper insulating layer 22. The bridge insulating layer 23 can be surrounded by the cap insulating layer 21. The bridge insulating layer 23 can be disposed in the cap insulating layer 21.

[0046] The cap insulating layer 21 and the bridge insulating layer 23 can include a material having etching selectivity with respect to the upper insulating layer 22. In an embodiment, the cap insulating layer 21 and the bridge insulating layer 23 can include a nitride material, and the upper insulating layer 22 can include an oxide material.

[0047] In an embodiment, the cap insulating layer 21 and the bridge insulating layer 23 can be formed of the same insulating material, or otherwise include the same insulating material. In an embodiment, the cap insulating layer 21 and the bridge insulating layer 23 can be formed of different insulating materials from each other, or otherwise include different insulating materials from each other.

[0048] One of the gate electrodes GE can include a first channel overlap portion GE1, a second channel overlap portion GE2, and a bridge portion GE3. The first channel overlap portion GE1 can overlap the first channel structure CH1 in the third direction D3, and the second channel overlap portion GE2 can overlap the second channel structure CH2 in the third direction D3. The first channel overlap portion GE1 can include a portion interposed between the first semiconductor patterns SP1 of the first channel structure CH1. The second channel overlap portion GE2 can include a portion interposed between the second semiconductor patterns SP2 of the second channel structure CH2.

[0049] The bridge portion GE3 can be disposed between the first channel overlap portion GE1 and the second channel overlap portion GE2. The bridge portion GE3 can connect the first channel overlap portion GE1 to the second channel overlap portion GE2. The bridge portion GE3 can be disposed at a height higher than the first channel overlap portion GE1 and the second channel overlap portion GE2. The bridge portion GE3 can be surrounded by the cap insulating layer 21. Each of the gate electrodes GE can include at least one bridge portion GE3.

[0050] The first channel overlap portion GE1 and the second channel overlap portion GE2 can be spaced apart from each other in the first direction D1. The separation insulating layer 20 can be disposed between the first channel overlap portion GE1 and the second channel overlap portion GE2. A side surface of the gate cut insulating layer 14 can be in contact with a side surface of the first channel overlap portion GE1.

[0051] Each of the active contacts AC can include an upper portion UAC and a lower portion LAC. The upper portion UAC of the active contact AC can be disposed at a higher level than the lower portion LAC of the active contact AC. The upper portion UAC of the active contact AC can be surrounded by the capping insulating layer 21. The lower portion LAC of the active contact AC can be disposed between the separation insulating layers 20. The lower portion LAC of the active contact AC can be in contact with the upper source / drain pattern USD.

[0052] The gate connection pattern 30 can penetrate the upper insulating layer 22. The gate connection pattern 30 can be disposed on the bridging portion GE3 of the gate electrode GE. The gate connection pattern 30 can be in contact with the capping insulating layer 21, the bridging insulating layer 23, the upper insulating layer 22, and the bridging portion GE3 of the gate electrode GE. The gate connection pattern 30 can include a conductive material.

[0053] The gate connection pattern 30 can include a lower portion 31 and an upper portion 32. The lower portion 31 of the gate connection pattern 30 can be disposed at a lower level than the upper portion 32 of the gate connection pattern 30. The lower portion 31 of the gate connection pattern 30 can be in contact with the bridging portion GE3 of the gate electrode GE, the capping insulating layer 21, and the bridging insulating layer 23. The upper portion 32 of the gate connection pattern 30 can be in contact with the upper insulating layer 22. A width of the lower portion 31 of the gate connection pattern 30 in the second direction D2 can be less than a width of the upper portion 32 of the gate connection pattern 30 in the second direction D2. The upper portion 32 of the gate connection pattern 30 can have a linear pattern extending in the second direction D2. The lower portion 31 of the gate connection pattern 30 can have a contact-shaped pattern surrounded by the capping insulating layer 21.

[0054] The contact connection pattern 40 can penetrate the upper insulating layer 22. The contact connection pattern 40 can be disposed on the upper portion UAC of the active contact AC. The contact connection pattern 40 can be in contact with the capping insulating layer 21, the upper insulating layer 22, and the upper portion UAC of the active contact AC. The contact connection pattern 40 can include a conductive material.

[0055] The contact connection pattern 40 can include a lower portion 41 and an upper portion 42. The lower portion 41 of the contact connection pattern 40 can be disposed at a lower level than the upper portion 42 of the contact connection pattern 40. The lower portion 41 of the contact connection pattern 40 can be in contact with the capping insulating layer 21 and the upper portion UAC of the active contact AC. The upper portion 42 of the contact connection pattern 40 can be in contact with the upper insulating layer 22. A width of the lower portion 41 of the contact connection pattern 40 in the second direction D2 can be less than a width of the upper portion 42 of the contact connection pattern 40 in the second direction D2. The upper portion 42 of the contact connection pattern 40 can have a linear pattern extending in the second direction D2. The lower portion 41 of the contact connection pattern 40 can have a contact-shaped pattern surrounded by the capping insulating layer 21.

[0056] The conductive lines 24 can be provided in the upper insulating layer 22. The conductive lines 24 can extend in the second direction D2. The upper portions 32 of the gate connection patterns 30 and the upper portions 42 of the contact connection patterns 40 can have a similar shape to the conductive lines 24. The upper portions 32 of the gate connection patterns 30 and the upper portions 42 of the contact connection patterns 40 can be provided at the same height as the conductive lines 24. The conductive lines 24 can be spaced apart from each other in the first direction D1. The conductive lines 24 can include a conductive material.

[0057] Referring to FIG. 1E and FIG. 1F The bridge portion GE3 can include a first side surface GE3_S1 connecting the top surface GE3_U of the bridge portion GE3 to the top surface GE1_U of the first channel overlap portion GE1 and a second side surface GE3_S2 connecting the top surface GE3_U of the bridge portion GE3 to the top surface GE2_U of the second channel overlap portion GE2. A distance between the first side surface GE3_S1 and the second side surface GE3_S2 of the bridge portion GE3 in the first direction D1 can increase as the height decreases.

[0058] The first side surface GE3_S1 and the second side surface GE3_S2 of the bridge portion GE3 can be inclined at an angle with respect to the top surface GE3_U of the bridge portion GE3, the top surface GE1_U of the first channel overlap portion GE1, and the top surface GE2_U of the second channel overlap portion GE2. In FIG. 1E In the illustrated cross-sectional view, an angle between the first side surface GE3_S1 of the bridge portion GE3 and the top surface GE1_U of the first channel overlap portion GE1 and an angle between the second side surface GE3_S2 of the bridge portion GE3 and the top surface GE2_U of the second channel overlap portion GE2 can be greater than 90°. In FIG. 1E In the illustrated cross-sectional view, an angle between the first side surface GE3_S1 of the bridge portion GE3 and the top surface GE3_U and an angle between the second side surface GE3_S2 of the bridge portion GE3 and the top surface GE3_U can be less than 270°.

[0059] A width W1 of the bridge portion GE3 in the first direction D1 can increase as the height decreases. The width W1 of the bridge portion GE3 in the first direction D1 can increase as the distance from the channel structure CH1 or CH2 decreases. The width W1 of the bridge portion GE3 in the first direction D1 can be less than a sum of widths of the first channel structure CH1, the second channel structure CH2, and the separation insulating layer 20 measured in the first direction D1.

[0060] The bridge portion GE3 can overlap the separation insulating layer 20 in the third direction D3. The separation insulating layer 20 can include a first portion P1 overlapping the bridge portion GE3 of the gate electrode GE in the third direction D3 and a second portion P2 disposed between the first source / drain structure SS1 and the second source / drain structure SS2. The second portion P2 of the separation insulating layer 20 can not overlap the bridge portion GE3 of the gate electrode GE in the third direction D3.

[0061] The top surface LAC_U of the lower portion LAC of the first active contact AC1, the top surface LAC_U of the lower portion LAC of the second active contact AC2, the top surface GE1_U of the first channel overlap portion GE1, the top surface GE2_U of the second channel overlap portion GE2, the top surface 14_U of the gate cut insulating layer 14 (see, for example, FIG. 6A), and the top surface P2_U of the second portion P2 of the separation insulating layer 20 can be located at the same height. The top surface LAC_U of the lower portion LAC of the first active contact AC1, the top surface GE1_U of the first channel overlap portion GE1, and the top surface 14_U of the gate cut insulating layer 14 can be coplanar with each other. The top surface LAC_U of the lower portion LAC of the first active contact AC1, the top surface LAC_U of the lower portion LAC of the second active contact AC2, and the top surface P2_U of the second portion P2 of the separation insulating layer 20 can be coplanar with each other. FIG. 1B and FIG. 1C The top surface LAC_U of the lower portion LAC of the first active contact AC1, the top surface LAC_U of the lower portion LAC of the second active contact AC2, the top surface GE1_U of the first channel overlap portion GE1, the top surface GE2_U of the second channel overlap portion GE2, the top surface 14_U of the gate cut insulating layer 14 (see, for example, FIG. 6A), and the top surface P2_U of the second portion P2 of the separation insulating layer 20 can be located at the same height. The top surface LAC_U of the lower portion LAC of the first active contact AC1, the top surface GE1_U of the first channel overlap portion GE1, and the top surface 14_U of the gate cut insulating layer 14 can be coplanar with each other. The top surface LAC_U of the lower portion LAC of the first active contact AC1, the top surface LAC_U of the lower portion LAC of the second active contact AC2, and the top surface P2_U of the second portion P2 of the separation insulating layer 20 can be coplanar with each other.

[0062] The height of the top surface P1_U of the first portion P1 of the separation insulating layer 20 can be higher than the height of the top surface LAC_U of the lower portion LAC of the first active contact AC1, the height of the top surface LAC_U of the lower portion LAC of the second active contact AC2, the height of the top surface GE1_U of the first channel overlap portion GE1, the height of the top surface GE2_U of the second channel overlap portion GE2, the height of the top surface 14_U of the gate cut insulating layer 14, and the height of the top surface P2_U of the second portion P2 of the separation insulating layer 20.

[0063] The height of the top surface GE3_U of the bridge portion GE3 can be higher than the height of the top surface P1_U of the first portion P1 of the separation insulating layer 20, the height of the top surface P2_U of the second portion P2 of the separation insulating layer 20, the height of the top surface LAC_U of the lower portion LAC of the first active contact AC1, the height of the top surface LAC_U of the lower portion LAC of the second active contact AC2, the height of the top surface GE1_U of the first channel overlap portion GE1, the height of the top surface GE2_U of the second channel overlap portion GE2, and the height of the top surface 14_U of the gate cut insulating layer 14.

[0064] The bridge insulating layer 23 can include a first side surface 23_S1 in contact with the capping insulating layer 21 and a second side surface 23_S2 in contact with the lower portion 31 of the gate connection pattern 30. The first side surface 23_S1 and the second side surface 23_S2 of the bridge insulating layer 23 can be opposite to each other. The first side surface 23_S1 of the bridge insulating layer 23 can be coplanar with the first side surface GE3_S1 of the bridge portion GE3. The first side surface 23_S1 of the bridge insulating layer 23 can be inclined at an angle with respect to the top surface and the bottom surface of the bridge insulating layer 23.

[0065] The capping insulating layer 21 can include a first side surface 21_S1 in contact with the first side surface 23_S1 of the bridge insulating layer 23 and the first side surface GE3_S1 of the bridge portion GE3, and a second side surface 21_S2 in contact with the lower portion 31 of the gate connection pattern 30 and the second side surface GE3_S2 of the bridge portion GE3. The first side surface 21_S1 and the second side surface 21_S2 of the capping insulating layer 21 can be inclined at an angle with respect to the top surface and the bottom surface of the capping insulating layer 21.

[0066] The width W2 of the lower portion 31 of the gate connection pattern 30 in the first direction D1 can increase as the height decreases. The width W3 of the upper portion 32 of the gate connection pattern 30 in the first direction D1 can decrease as the height decreases. The width W2 of the lower portion 31 of the gate connection pattern 30 in the first direction D1 and the width W3 of the upper portion 32 of the gate connection pattern 30 in the first direction D1 can be less than the width W1 of the bridge portion GE3 in the first direction D1.

[0067] A bottom surface of the lower portion 31 of the gate connection pattern 30 can be in contact with a top surface GE3_U of the bridging portion GE3. The lower portion 31 of the gate connection pattern 30 can include a first side surface 31_S1 in contact with a second side surface 23_S2 of the bridging insulating layer 23 and a second side surface 31_S2 in contact with a second side surface 21_S2 of the capping insulating layer 21. The first side surface 31_S1 of the lower portion 31 of the gate connection pattern 30 can be connected to the top surface GE_U of the bridging portion GE3. The second side surface 31_S2 of the lower portion 31 of the gate connection pattern 30 can be connected to the top surface GE_U and the second side surface GE3_S2 of the bridging portion GE3. There can be a triple point at which the top surface GE3_U of the bridging portion GE3, the second side surface GE3_S2 of the bridging portion GE3, and the second side surface 31_S2 of the lower portion 31 of the gate connection pattern 30 are connected to each other. The second side surface 31_S2 of the lower portion 31 of the gate connection pattern 30 can be coplanar with the second side surface GE3_S2 of the bridging portion GE3. The side surface 32_S of the upper portion 32 of the gate connection pattern 30 can be connected to the side surfaces 31_S1 and 31_S2 of the lower portion 31 of the gate connection pattern 30.

[0068] The bridging portion GE3 can include a first portion G1 connected to the first channel overlap portion GE1, a second portion G2 connected to the second channel overlap portion GE2, and a third portion G3 between the first portion G1 and the second portion G2. The third portion G3 of the bridging portion GE3 can overlap the first portion P1 of the separation insulating layer 20 in the third direction D3.

[0069] The first portion G1 of the bridging portion GE3 can be disposed between the third portion G3 of the bridging portion GE3 and the first channel overlap portion GE1. The second portion G2 of the bridging portion GE3 can be disposed between the third portion G3 of the bridging portion GE3 and the second channel overlap portion GE2. The first side surface GE3_S1 of the bridging portion GE3 can be a side surface of the first portion G1 of the bridging portion GE3. The second side surface GE3_S2 of the bridging portion GE3 can be a side surface of the second portion G2 of the bridging portion GE3. The lower portion 31 of the gate connection pattern 30 can be in contact with a top surface of the second portion G2 of the bridging portion GE3. In an embodiment, the lower portion 31 of the gate connection pattern 30 can be in contact with a top surface of the first portion G1 or the third portion G3 of the bridging portion GE3.

[0070] A width of the gate connection pattern 30 in the first direction D1 can be smaller than a width of the second portion G2 of the bridge portion GE3 in the first direction D1. A bottom surface of the bridge insulating layer 23 can be in contact with top surfaces of the first to third portions G1, G2, and G3 of the bridge portion GE3. Each of the first and second portions G1 and G2 of the bridge portion GE3 can increase in width in the first direction D1 as the height decreases.

[0071] The third portion G3 of the bridge portion GE3 can be disposed at a height higher than a top surface P1_U of the first portion P1 of the separation insulating layer 20. The first channel overlap portion GE1, the second channel overlap portion GE2, a portion of the first portion G1 of the bridge portion GE3, and a portion of the second portion G2 of the bridge portion GE3 can be disposed at a height lower than the top surface P1_U of the first portion P1 of the separation insulating layer 20.

[0072] The first portion G1 of the bridge portion GE3 can include a side surface G1_S in contact with the gate insulating layer GI. The second portion G2 of the bridge portion GE3 can include a side surface G2_S in contact with the gate insulating layer GI. A bottom surface G3_L of the third portion G3 of the bridge portion GE3 can be in contact with the gate insulating layer GI.

[0073] A side surface UAC_S of the upper portion UAC of the first active pattern AC1 can be coplanar with a side surface 41_S of the lower portion 41 of the contact connection pattern 40. A bottom surface of the lower portion 41 of the contact connection pattern 40 can be in contact with a top surface UAC_U of the upper portion UAC of the first active pattern AC1. A width W4 of the upper portion UAC of the first active pattern AC1 in the first direction D1 can increase as the height decreases. A width W5 of the lower portion 41 of the contact connection pattern 40 in the first direction D1 can increase as the height decreases. A width W6 of the upper portion 42 of the contact connection pattern 40 in the first direction D1 can decrease as the height decreases.

[0074] The cap insulating layer 21 can include a third side surface 21_S3 in contact with the side surface UAC_S of the upper portion UAC of the first active pattern AC1 and the side surface 41_S of the lower portion 41 of the contact connection pattern 40.

[0075] In an embodiment, a range of distances in the third direction D3 between an uppermost portion of the channel structure CH1 or CH2 and a top surface GE_U of the bridging portion GE3 can be 1 nm to 30 nm. A third portion G3 of the bridging portion GE3 can have a thickness in the third direction D3 that is less than thicknesses in the third direction D3 of the first portion G1 and the second portion G2 of the bridging portion GE3. In an embodiment, a range of thicknesses in the third direction D3 of the third portion G3 of the bridging portion GE3 can be 1 nm to 20 nm. A width W1 of the bridging portion GE3 in the first direction D1 can be 1 nm to 20 nm greater than a width W2 of the lower portion 31 of the gate connection pattern 30 in the first direction D1. In an embodiment, a range of thicknesses in the third direction D3 of the lower portion 31 of the gate connection pattern 30 can be 1 nm to 20 nm.

[0076] In an embodiment, since the semiconductor device includes the bridging portion GE3 of the gate electrode GE and the gate connection pattern 30, it can not be necessary to separately form a contact and a conductive line connected to each of the first channel overlap portion GE1 and the second channel overlap portion GE2. Thus, it is possible to reduce the size and manufacturing cost of the semiconductor device. Further, it is also possible to reduce the technical difficulty in designing the conductive line 24.

[0077] In an embodiment, since the bridging portion GE3 of the gate electrode GE has a relatively small width, it is possible to reduce a capacitance problem caused by the gate electrode GE and to improve the electrical characteristics of the semiconductor device.

[0078] FIG. 2A , FIG. 2B , FIG. 2C , FIG. 3A , FIG. 3B , FIG. 4A , FIG. 4B , FIG. 4C , FIG. 5A , FIG. 5B , FIG. 5C , FIG. 6A , FIG. 6B , FIG. 6C , FIG. 7A , FIG. 7B , FIG. 7C , FIG. 7D , FIG. 8A , FIG. 8B , FIG. 8C , FIG. 9A , FIG. 9B , FIG. 9C , FIG. 9D , FIG. 10A , FIG. 10B , FIG. 10C , FIG. 11A , FIG. 11B and FIG. 1A to FIG. 1D are shown in FIG. 12FIG. 1 is a diagram of a method of manufacturing a semiconductor device.

[0079] Referring to FIG. 12 , FIG. 1A to FIG. 1F and FIG. 12 , a device isolation layer 11, active patterns AP1 and AP2, a sacrificial semiconductor layer 51, a semiconductor layer 52, and a separation insulating layer 20 can be formed. Forming the device isolation layer 11, the active patterns AP1 and AP2, the sacrificial semiconductor layer 51, the semiconductor layer 52, and the separation insulating layer 20 can include: alternately forming preliminary sacrificial semiconductor layers and preliminary semiconductor layers on the substrate 100; patterning the substrate 100, the preliminary sacrificial semiconductor layers, and the preliminary semiconductor layers to form preliminary active patterns, the sacrificial semiconductor layer 51, and the semiconductor layer 52; forming the device isolation layer 11; and forming the separation insulating layer 20. The preliminary active patterns can be divided into the active patterns AP1 and AP2 by the separation insulating layer 20.

[0080] The sacrificial semiconductor layer 51 can include a material that is etch-selective with respect to the semiconductor layer 52. For example, the sacrificial semiconductor layer 51 can be formed of, or otherwise include, silicon-germanium (SiGe), and the semiconductor layer 52 can be formed of, or otherwise include, silicon (Si).

[0081] A gate sacrificial pattern 53, a gate mask pattern 54, and a gate spacer GS can be formed. Forming the gate sacrificial pattern 53, the gate mask pattern 54, and the gate spacer GS can include: forming a preliminary gate sacrificial layer disposed on the semiconductor layer 52 and the sacrificial semiconductor layer 51; forming the gate mask pattern 54 on the preliminary gate sacrificial layer; etching the preliminary gate sacrificial layer using the gate mask pattern 54 as an etch mask to form the gate sacrificial pattern 53; and forming the gate spacer GS.

[0082] The gate sacrificial pattern 53 and the gate mask pattern 54 can extend in a first direction D1. In an embodiment, the gate sacrificial pattern 53 can be formed of, or otherwise include, polysilicon. The gate mask pattern 54 can include an insulating material.

[0083] The separation insulating layer 20 can include an exposed top surface ES. The exposed top surface ES of the separation insulating layer 20 can not be covered by the gate sacrificial pattern 53 and can be exposed to the exterior.

[0084] Referring to FIG. 11A and FIG. 13 , the sacrificial semiconductor layer 51, the semiconductor layer 52, and the active patterns AP1 and AP2 can be etched using the gate mask pattern 54 and the gate spacer GS as etch masks. As a result of the etching process, the semiconductor layer 52 can be divided into semiconductor patterns SP1 and SP2.

[0085] A sacrificial insulating layer 61 can be formed on the separation insulating layer 20. The sacrificial insulating layer 61 can be formed on the exposed top surface ES of the separation insulating layer 20. The sacrificial insulating layer 61 can include an insulating material.

[0086] A lower source / drain pattern LSD and an upper source / drain pattern USD can be formed. The lower source / drain pattern LSD can be formed in the empty space formed by etching the active pattern API or AP2. The upper source / drain pattern USD can be formed in the empty space formed by etching the sacrificial semiconductor layer 51 and the semiconductor layer 52.

[0087] Referring to FIG. 13 , FIG. 1A to FIG. 1F and FIG. 13 , the cover insulating layer 15 and the insulating layer 13 can be formed.

[0088] The gate mask pattern 54, the gate sacrificial pattern 53, and the sacrificial semiconductor layer 51 can be removed.

[0089] Referring to FIG. 11A , FIG. 14 and FIG. 14 , the gate insulating layer GI and the gate electrode GE can be formed. The gate insulating layer GI and the gate electrode GE can be formed in the empty space formed by removing the gate sacrificial pattern 53 and the sacrificial semiconductor layer 51. The gate capping layer 62 can be formed on the gate electrode GE. The gate capping layer 62 can include an insulating material.

[0090] The gate cut insulating layer 14 can be formed. The gate cut insulating layer 14 can penetrate the gate capping layer 62 and the gate electrode GE. The gate electrode GE can be divided into a plurality of gate electrodes GE by the gate cut insulating layer 14.

[0091] Referring to FIG. 1A to FIG. 1F , FIG. 14 and FIG. 11A , the insulating layer 13 and the cover insulating layer 15 can be etched to expose the upper source / drain pattern USD. A preliminary contact layer can cover the exposed upper source / drain pattern USD. An upper portion of the preliminary contact layer and the gate capping layer 62 can be removed. In an embodiment, the upper portion of the preliminary contact layer and the gate capping layer 62 can be removed by a chemical mechanical polishing (CMP) process. In an embodiment, an upper portion of the sacrificial insulating layer 61 can be removed during the removal of the upper portion of the preliminary contact layer and the gate capping layer 62.

[0092] As a result of the removal of the upper portion of the preliminary contact layer, an active contact AC can be formed. As a result of the removal of the upper portion of the preliminary contact layer, the preliminary contact layer can be divided into the active contact AC. As a result of the removal of the gate capping layer 62, the gate electrode GE can be exposed.

[0093] Referring toFIG. 15 FIG. 15 FIG. 1A to FIG. 1F FIG. 15 A mask layer 64 can be formed on the gate electrode GE and the active contact AC. The mask layer 64 can include an insulating material. In embodiments, the mask layer 64 can include a nitride material.

[0094] The bridge sacrifice pattern 63 and the contact sacrifice pattern 65 can penetrate the mask layer 64. The bridge sacrifice pattern 63 can overlap with the gate electrode GE in the third direction D3. The contact sacrifice pattern 65 can overlap with the active contact AC in the third direction D3. The bridge sacrifice pattern 63 and the contact sacrifice pattern 65 can include an insulating material. In embodiments, the bridge sacrifice pattern 63 and the contact sacrifice pattern 65 can include an oxide material.

[0095] A thickness of the bridge sacrifice pattern 63 and the contact sacrifice pattern 65 in the third direction D3 can be greater than a thickness of the mask layer 64 in the third direction D3. A height of a top surface of the bridge sacrifice pattern 63 and the contact sacrifice pattern 65 can be higher than a height of a top surface of the mask layer 64. In embodiments, the bridge sacrifice pattern 63 and the contact sacrifice pattern 65 can be formed simultaneously.

[0096] A width of the bridge sacrifice pattern 63 in the first direction D1 can be less than a width of the gate electrode GE in the first direction D1. A width of the bridge sacrifice pattern 63 in the second direction D2 can be greater than a width of the gate electrode GE in the second direction D2.

[0097] Referring to ​ ​ ​ The bridge sacrifice pattern 63 and the contact sacrifice pattern 65 can be used as an etching mask to etch the mask layer 64, the gate electrode GE, the gate cut insulating layer 14, the separation insulating layer 20, and the active contact AC. In embodiments, the mask layer 64, the gate electrode GE, the gate cut insulating layer 14, the separation insulating layer 20, and the active contact AC can be etched by a non-selective etching process.

[0098] As a result of etching the gate electrode GE, a first channel overlap portion GE1, a second channel overlap portion GE2, and a bridge portion GE3 of the gate electrode GE can be formed. The bridge portion GE3 can be a portion of the gate electrode GE that is not etched during the etching process due to the bridge sacrifice pattern 63. A side surface 63_S of the bridge sacrifice pattern 63 can be coplanar with side surfaces GE3_S1 and GE3_S2 of the bridge portion GE3. The side surface 63_S of the bridge sacrifice pattern 63 can be inclined at an angle with respect to a top surface and a bottom surface of the bridge sacrifice pattern 63. A width of the bridge sacrifice pattern 63 in the first direction D1 can increase as the height decreases.

[0099] ​​​​​As a result of etching the active contact AC, a lower portion LAC and an upper portion UAC of the active contact AC can be formed. The upper portion UAC of the active contact AC can be a portion of the active contact AC that is not etched during the etching process as a result of the contact sacrificial pattern 65. The side surface 65 S of the contact sacrificial pattern 65 can be coplanar with a side surface UAC S of the upper portion UAC of the active contact AC. The side surface 65 S of the contact sacrificial pattern 65 can be inclined at an angle with respect to the top surface and the bottom surface of the contact sacrificial pattern 65. The width of the contact sacrificial pattern 65 in the first direction D1 can increase as the height decreases.

[0100] The first portion PI of the separation insulating layer 20 can overlap the bridge sacrificial pattern 63 in the third direction D3. The first portion PI of the separation insulating layer 20 can be protected from the etching process as a result of the bridge sacrificial pattern 63 and the bridge portion GE3. The mask layer 64 can be removed by the etching process and, in this case, the second portion P2 of the separation insulating layer 20 can be exposed and etched. As a result of etching the second portion P2 of the separation insulating layer 20, a top surface P2 U of the second portion P2 of the separation insulating layer 20 can be defined.

[0101] As a result of etching the mask layer 64, the gate cut insulating layer 14 can be exposed and etched. As a result of etching the gate cut insulating layer 14, a top surface 14 U of the gate cut insulating layer 14 can be defined.

[0102] As a result of the etching process, the top surface 14 U of the gate cut insulating layer 14, the top surface P2 U of the second portion P2 of the separation insulating layer 20, the top surfaces GE1 U and GE2 U of the first and second channel overlap portions GE1 and GE2, and the top surface LAC U of the lower portion LAC of the active contact AC can be coplanar with each other.

[0103] Referring to ​ , ​ , ​ and ​ A capping insulating layer 21 can be formed. The capping insulating layer 21 can enclose the bridge portion GE3, the upper portion UAC of the active contact AC, the bridge sacrificial pattern 63, and the contact sacrificial pattern 65. The capping insulating layer 21 can contact the top surface 14 U of the gate cut insulating layer 14, the top surface P2 U of the second portion P2 of the separation insulating layer 20, the top surfaces GE1 U and GE2 U of the first and second channel overlap portions GE1 and GE2, the top surface LAC U of the lower portion LAC of the active contact AC, the side surfaces GE3 S1 and GE3 S2 of the bridge portion GE3, the side surface 63 S of the bridge sacrificial pattern 63, the side surface UAC S of the upper portion UAC of the active contact AC, and the side surface 65 S of the contact sacrificial pattern 65.

[0104] The top surface of the cap insulating layer 21, the top surface of the bridge sacrificial pattern 63, and the top surface of the contact sacrificial pattern 65 can be coplanar with each other. In an embodiment, forming the cap insulating layer 21 can include forming a preliminary cap insulating layer, and removing an upper portion of the preliminary cap insulating layer to form the cap insulating layer 21.

[0105] Referring to ​ , ​ and ​ , the bridge sacrificial pattern 63 can be selectively etched. As a result of etching the bridge sacrificial pattern 63, a gate sacrificial pattern 71 can be formed. A remaining portion of the bridge sacrificial pattern 63 that is not etched by the etching process can be defined as the gate sacrificial pattern 71.

[0106] As a result of etching the bridge sacrificial pattern 63, a top surface GE3_U of the bridge portion GE3 can be exposed. A bridge insulating layer 23 can be formed on the top surface GE3_U of the bridge portion GE3. The bridge insulating layer 23 can cover the top surface GE3_U of the bridge portion GE3.

[0107] A width of the gate sacrificial pattern 71 in the first direction D1 can be less than a width of the bridge insulating layer 23 in the first direction D1. The width of the gate sacrificial pattern 71 in the first direction D1 can be less than a width of the bridge portion GE3 in the first direction D1. A width of the gate sacrificial pattern 71 in the second direction D2 can be equal to a width of the bridge insulating layer 23 in the second direction D2. The width of the gate sacrificial pattern 71 in the second direction D2 can be greater than a width of the bridge portion GE3 in the second direction D2. A portion of the top surface GE3_U of the bridge portion GE3 can be in contact with a bottom surface of the gate sacrificial pattern 71, and another portion can be in contact with a bottom surface of the bridge insulating layer 23.

[0108] Referring to ​ and ​ , the gate sacrificial pattern 71 and the contact sacrificial pattern 65 can be selectively removed. The gate sacrificial pattern 71 can be removed to form a first space 72. The first space 72 can be an empty space formed by removing the gate sacrificial pattern 71. The first space 72 can expose the bridge portion GE3. The contact sacrificial pattern 65 can be removed to form a second space 73. The second space 73 can be an empty space formed by removing the contact sacrificial pattern 65. The second space 73 can expose an upper portion UAC of the active contact portion AC.

[0109] Referring to ​ , an upper insulating layer 22 can be formed. The upper insulating layer 22 can include a first portion filling the first space 72 and a second portion filling the second space 73.

[0110] The upper insulating layer 22 can be etched to form a hollow space. The gate connection pattern 30, the contact connection pattern 40, and the conductive line 24 can be formed in the hollow space. The etching of the upper insulating layer 22 can be performed to remove a first portion of the upper insulating layer 22 and to reopen the first space 72. The lower portion 31 of the gate connection pattern 30 can be formed in the first space 72. The etching of the upper insulating layer 22 can also be performed to remove a second portion of the upper insulating layer 22 and to reopen the second space 73. The lower portion 41 of the contact connection pattern 40 can be formed in the second space 73. The gate connection pattern 30, the contact connection pattern 40, and the conductive line 24 can be formed simultaneously.

[0111] In the method of manufacturing a semiconductor device according to the embodiment of the present inventive concept, the bridging portion GE3 can be formed using the bridging sacrificial pattern 63 as an etching mask, the gate sacrificial pattern 71 can be formed by etching the bridging sacrificial pattern 63, and the gate connection pattern 30 can be formed in a hollow space formed by removing the gate sacrificial pattern 71. Thus, a misalignment problem occurring between the bridging portion GE3 and the gate connection pattern 30 can be reduced.

[0112] In the method of manufacturing a semiconductor device, according to the embodiment of the present inventive concept, the upper portion UAC of the active contact portion AC can be formed using the contact sacrificial pattern 65 as an etching mask, and the contact connection pattern 40 can be formed in a hollow space formed by removing the contact sacrificial pattern 65. Thus, a misalignment problem occurring between the upper portion UAC of the active contact portion AC and the contact connection pattern 40 can be reduced.

[0113] In the method of manufacturing a semiconductor device, according to the embodiment of the present inventive concept, the gate connection pattern 30, the contact connection pattern 40, and the conductive line 24 can be formed simultaneously. Thus, a process of manufacturing a semiconductor device can be simplified.

[0114] ​ is an enlarged cross-sectional view illustrating a semiconductor device according to an embodiment of the present inventive concept. ​ The semiconductor device of ​ The semiconductor device of

[0115] Reference is made to ​The gate connection pattern 130 can include a lower portion 131 and an upper portion 132. The lower portion 131 of the gate connection pattern 130 can include a first side surface 131_S1 in contact with the side surface 123_S of the bridging insulating layer 123 and a second side surface 131_S2 in contact with the capping insulating layer 21. The second side surface 131_S2 of the lower portion 131 of the gate connection pattern 130 can not be parallel to the side surface GE3_S of the bridging portion GE3. The side surfaces 131_S1 and 131_S2 of the lower portion 131 of the gate connection pattern 130 can be coplanar with the side surface 132_S of the upper portion 132 of the gate connection pattern 130.

[0116] The width of the bridging insulating layer 123 in the first direction D1 can increase as the height decreases. The width of the lower portion 131 of the gate connection pattern 130 in the first direction D1 can decrease as the height decreases. The width of the upper portion 132 of the gate connection pattern 130 in the first direction D1 can decrease as the height decreases.

[0117] In embodiments, the first space 72 can be enlarged after the first space 72 is formed (e.g., see ​ ). The width of the enlarged first space in the first direction D1 can decrease as the height decreases. The upper insulating layer 22 can fill the enlarged first space. The upper insulating layer 22 can be etched to open the enlarged first space 72, and then the gate connection pattern 130 can be formed.

[0118] ​ is a magnified cross-sectional view illustrating a semiconductor device according to an embodiment of the inventive concept. ​ The semiconductor device of ​ may be similar to the semiconductor device of , except for the features to be described below and to the extent that elements are not described in detail for these figures, it is to be understood that the elements are at least similar to corresponding elements already described elsewhere in the disclosure.

[0119] Referring to ​ , the gate connection pattern 230 can include a lower portion 231 and an upper portion 232. The lower portion 231 of the gate connection pattern 230 can include a first side surface 231_S1 in contact with the side surface 223_S of the bridging insulating layer 223 and a second side surface 231_S2 in contact with the capping insulating layer 21. The second side surface 231_S2 of the lower portion 231 of the gate connection pattern 230 can not be parallel to the side surface GE3_S of the bridging portion GE3. The side surfaces 231_S1 and 231_S2 of the lower portion 231 of the gate connection pattern 230 can not be parallel to the side surface 232_S of the upper portion 232 of the gate connection pattern 230.

[0120] The width of the lower portion 231 of the gate connection pattern 230 in the first direction D1 can decrease as the height decreases. The width of the upper portion 232 of the gate connection pattern 230 in the first direction D1 can increase as the height decreases. The width of the conductive line 224 in the first direction D1 can increase as the height decreases.

[0121] In embodiments, the first space 72 can be enlarged after the first space 72 is formed (e.g., see ​ ). The preliminary conductive layer can fill the enlarged first space. The preliminary conductive layer can cover the bridge insulating layer 223 and the capping insulating layer 21. The preliminary conductive layer can be etched to form the conductive line 224 and the upper portion 232 of the gate connection pattern 230. Next, the upper insulating layer 22 can be formed.

[0122] ​ is an enlarged sectional view illustrating a semiconductor device according to an embodiment of the present inventive concept. ​ The semiconductor device of ​ may be similar to the semiconductor device of , except for the features to be described below and to the extent that elements are not described in detail for these figures, it is to be understood that the elements are at least similar to corresponding elements already described elsewhere in the present disclosure.

[0123] Referring to ​ , the gate connection pattern 330 can include a lower portion 331 and an upper portion 332. The lower portion 331 of the gate connection pattern 330 can include a first side surface 331_S1 in contact with a side surface 323_S of the bridge insulating layer 323 and a second side surface 331_S2 in contact with the capping insulating layer 21. The second side surface 331_S2 of the lower portion 331 of the gate connection pattern 330 can be coplanar with the side surface GE3_S of the bridge portion GE3. The second side surface 331_S2 of the lower portion 331 of the gate connection pattern 330 can be parallel to the side surface GE3_S of the bridge portion GE3. The side surfaces 331_S1 and 331_S2 of the lower portion 331 of the gate connection pattern 330 can be coplanar with a side surface 332_S of the upper portion 332 of the gate connection pattern 330.

[0124] The width of the lower portion 331 of the gate connection pattern 330 in the first direction D1 can increase as the height decreases. The width of the upper portion 332 of the gate connection pattern 330 in the first direction D1 can increase as the height decreases.

[0125] In embodiments, the first space 72 can be enlarged after the first space 72 is formed (e.g., see ​), the preliminary conductive layer can fill the first space 72. The preliminary conductive layer can cover the bridging insulating layer 323 and the capping insulating layer 21. The preliminary conductive layer can be etched to form the conductive line 324 and the upper portion 332 of the gate connection pattern 330. Next, the upper insulating layer 22 can be formed.

[0126] ​ is an enlarged cross-sectional view illustrating a semiconductor device according to an embodiment of the inventive concept. ​ The semiconductor device of ​ The semiconductor device of

[0127] Referring to ​ The gate connection pattern 430 can include a lower portion 431 and an upper portion 432. The lower portion 431 of the gate connection pattern 430 can include a first side surface 431_S1 in contact with a side surface 423_S of the bridging insulating layer 423 and a second side surface 431_S2 in contact with the capping insulating layer 21. The second side surface 431_S2 of the lower portion 431 of the gate connection pattern 430 can be coplanar with the side surface GE3_S of the bridging portion GE3. The second side surface 431_S2 of the lower portion 431 of the gate connection pattern 430 can be parallel to the side surface GE3_S of the bridging portion GE3.

[0128] The upper portion 432 of the gate connection pattern 430 can include a bottom surface 432_L connecting the side surface 432_S of the upper portion 432 of the gate connection pattern 430 and the side surfaces 431_S1 and 431_S2 of the lower portion 431 of the gate connection pattern 430. The bottom surface 432_L of the upper portion 432 of the gate connection pattern 430 can be in contact with the top surface of the capping insulating layer 21 and the top surface of the bridging insulating layer 423.

[0129] A width of the upper portion 432 of the gate connection pattern 430 in the first direction D1 can be greater than a width of the lower portion 431 of the gate connection pattern 430 in the first direction D1. A width of the conductive line 424 in the first direction D1 can be greater than the width of the lower portion 431 of the gate connection pattern 430 in the first direction D1.

[0130] In a semiconductor device, according to embodiments of the inventive concept, a gate electrode can include a bridging portion, and it can not be necessary to connect a contact and a conductive line to each of the channel overlap portions. Accordingly, a size and manufacturing cost of the semiconductor device can be reduced.

[0131] While example embodiments of the inventive concept have been particularly shown and described, ordinary skilled in the art will understand that changes can be made in form and details without departing from the spirit and scope of the disclosure.

Claims

1. A semiconductor device, comprising: A first source / drain structure and a second source / drain structure spaced apart from the first source / drain structure; The first channel structure is connected to the first source / drain structure; The second channel structure is connected to the second source / drain structure; A separate insulating layer is disposed between the first source / drain structure and the second source / drain structure, and also between the first channel structure and the second channel structure; as well as The gate electrode overlaps with the separated insulating layer, the first channel structure, and the second channel structure. The gate electrode includes: The overlapping portion of the first channel overlaps with the structure of the first channel; The overlapping portion of the second channel overlaps with the structure of the second channel; and The bridging portion is disposed between the overlapping portion of the first channel and the overlapping portion of the second channel. The height of the top surface of the bridging portion is higher than the height of the top surface of the first overlapping portion of the channel and the height of the top surface of the second overlapping portion of the channel.

2. The semiconductor device according to claim 1, wherein, The overlapping portions of the first and second channels are spaced apart from each other. The separating insulating layer is disposed between the overlapping portion of the first channel and the overlapping portion of the second channel, and The bridging portion overlaps with the separated insulating layer.

3. The semiconductor device according to claim 1, wherein, The bridging portion includes: The first side surface connects the top surface of the bridging portion to the top surface of the first channel overlapping portion; and The second side surface connects the top surface of the bridging portion to the top surface of the overlapping portion of the second channel. The distance between the first side surface and the second side surface of the bridging portion increases as the height decreases.

4. The semiconductor device according to claim 1, wherein, The height of the top surface of the portion where the separating insulating layer overlaps with the bridging portion is higher than the height of the top surface of the first overlapping portion and the top surface of the second overlapping portion.

5. The semiconductor device according to claim 4, wherein, The height of the top surface of the portion of the separating insulating layer is lower than the height of the top surface of the bridging portion.

6. The semiconductor device according to claim 1, wherein, The first overlapping portion and the second overlapping portion of the channel are spaced apart from each other in a first direction. The semiconductor device further includes a gate connection pattern that contacts the top surface of the bridging portion, and Wherein, the width of the gate connection pattern in the first direction is smaller than the width of the bridging portion in the first direction.

7. The semiconductor device of claim 1, further comprising a bridging insulating layer in contact with the top surface of the bridging portion. in, The side surface of the bridging insulation layer is coplanar with the side surface of the bridging portion.

8. The semiconductor device of claim 7, further comprising a capping insulating layer, the capping insulating layer being in contact with the top surface of the overlapping portion of the first channel, the side surface of the bridging portion, and the side surface of the bridging insulating layer. in, The sealing insulation layer has an inclined side surface.

9. A semiconductor device, comprising: A first source / drain structure and a second source / drain structure spaced apart from the first source / drain structure; The first channel structure is connected to the first source / drain structure; The second channel structure is connected to the second source / drain structure; A separation insulating layer is disposed between the first source / drain structure and the second source / drain structure, and between the first channel structure and the second channel structure; as well as The gate electrode overlaps with the separated insulating layer, the first channel structure, and the second channel structure. The gate electrode includes: The overlapping portion of the first channel overlaps with the structure of the first channel; The overlapping portion of the second channel overlaps with the structure of the second channel; and The bridging section connects the overlapping portion of the first channel to the overlapping portion of the second channel. The bridging portion includes: The first part is connected to the overlapping portion of the first channel; The second part connects to the overlapping portion of the second channel; and The third part is located between the first part and the second part. The third portion of the bridging section is positioned at a height higher than the separating insulating layer, and The third portion of the bridging portion overlaps with the separated insulating layer.

10. The semiconductor device according to claim 9, wherein, The width of the first portion of the bridging section increases as the height decreases, and The width of the second portion of the bridging section increases as the height decreases.

11. The semiconductor device of claim 9, further comprising a gate-cut insulating layer, the gate-cut insulating layer being in contact with a side surface of the overlapping portion of the first channel. in, The bridging portion is located at a height higher than the top surface of the gate-cut insulating layer.

12. The semiconductor device according to claim 11, wherein, The top surface of the first channel overlap portion is coplanar with the top surface of the gate-cut insulating layer.

13. The semiconductor device according to claim 11, wherein, The separating insulating layer includes a portion that overlaps with the third portion of the bridging portion, and The height of the top surface of the portion of the separated insulating layer is higher than the height of the top surface of the gate-cut insulating layer.

14. The semiconductor device according to claim 9, wherein, The first overlapping portion and the second overlapping portion of the channel are spaced apart from each other in a first direction, and Wherein, the width of the bridging portion in the first direction is less than the sum of the widths of the first channel structure, the second channel structure, and the separating insulating layer in the first direction.

15. The semiconductor device according to claim 9, wherein, The first overlapping portion and the second overlapping portion of the channel are spaced apart from each other in a first direction. The semiconductor device further includes a gate connection pattern that contacts the top surface of the second portion of the bridging portion, and Wherein, the width of the gate connection pattern in the first direction is smaller than the width of the second portion of the bridging portion in the first direction.

16. The semiconductor device according to claim 15, wherein, The gate connection pattern includes a lower part and an upper part, and Wherein, the side surface of the lower part of the gate connection pattern is coplanar with the side surface of the second part of the bridging portion.

17. The semiconductor device according to claim 16, wherein, The width of the lower portion of the gate connection pattern increases as the height decreases, and The width of the upper part of the gate connection pattern decreases as the height decreases.

18. The semiconductor device of claim 15, further comprising a bridging insulating layer, the bridging insulating layer being in contact with the top surfaces of the first portion and the third portion of the bridging portion. in, The side surface of the bridging insulation layer is coplanar with the side surface of the first portion of the bridging portion.

19. A semiconductor device, comprising: A first source / drain structure and a second source / drain structure spaced apart from the first source / drain structure; The first channel structure is connected to the first source / drain structure; The second channel structure is connected to the second source / drain structure; The first active contact portion is disposed on the first source / drain structure; The second active contact portion is disposed on the second source / drain structure; A separation insulating layer is disposed between the first source / drain structure and the second source / drain structure, between the first channel structure and the second channel structure, and between the first active contact portion and the second active contact portion; The gate electrode overlaps with the separated insulating layer, the first channel structure, and the second channel structure; A gate insulating layer is disposed between the gate electrode and the separation insulating layer; An insulating layer is provided on the first active contact portion, the second active contact portion, and the gate electrode; as well as A gate connection pattern is disposed on the gate electrode; A bridging insulating layer is in contact with the gate electrode, the gate connection pattern, and the capping insulating layer; as well as A contact connection pattern is disposed on the first active contact portion. The gate electrode includes a bridging portion that contacts the bridging insulating layer and the gate connection pattern. The width of the bridging portion increases as the height decreases.

20. The semiconductor device according to claim 19, wherein, The first active contact portion includes a lower portion that contacts the first source / drain structure and an upper portion that contacts the contact connection pattern. The width of the upper part of the first active contact increases as the height decreases.

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