Semiconductor device

Abstract

The invention relates to a semiconductor device. In one embodiment, forming the semiconductor device includes forming a gate trench in a semiconductor substrate. A portion of the material between the trenches is constricted, and another material is formed on sidewalls of the constricted portion that are substantially unetched by an etchant that etches the material of the portion of the material between the trenches. The source contact opening and the gate contact opening are formed together.

Description

[0001] This divisional application is based on a Chinese Patent Application No. 202010189342.8, filed on March 18, 2020, entitled “Method of Forming Semiconductor Device”. TECHNICAL FIELD

[0002] The present disclosure relates generally to electronic devices, and more particularly to semiconductors, semiconductor structures, and methods of forming semiconductor devices. BACKGROUND

[0003] In the past, the semiconductor industry has utilized various methods and structures to form trench metal oxide semiconductor field effect transistors (MOSFETs). As process technology allows for smaller device spacing, it becomes more difficult to provide reliable contacts to the MOSFET. In some manufacturing techniques, the contacts become misaligned, which sometimes increases the Rdson of the MOSFET. Higher Rdson results in poorer performance or alternatively higher manufacturing costs. In some applications, misalignment of some MOSFET features results in non-clamped inductive switching (UIS) performance degradation.

[0004] In some other manufacturing techniques, different masking and etching operations are utilized to form the source contact and the gate contact. These different operations for the two contacts result in higher manufacturing costs for the MOSFET.

[0005] Accordingly, it would be desirable to have a manufacturing technique that provides more reliable contacts, provides more reliable Rdson, reduces manufacturing operations, or / and reduces manufacturing costs. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 An example showing an enlarged plan view of a portion of an embodiment of a semiconductor device according to the present disclosure;

[0007] Figure 2 An example showing an enlarged cross-sectional view of a portion of a device according to the present disclosure; Figure 1

[0008] Figure 3 An example showing an early stage in an embodiment of a method of forming a device according to the present disclosure; Figures 1-2

[0009] Figure 4 An example showing a later stage in an embodiment of a method of forming a device according to the present disclosure; Figures 1-2

[0010] Figure 5 An example showing another later stage in an embodiment of a method of forming a device according to the present disclosure; Figures 1-2 ​​​​

[0011] Figure 6 a device according to the application in an example of an embodiment of a method of forming Figures 1-2 a device according to the application in an example of an embodiment of a method of forming

[0012] Figure 7 a device according to the application in an example of an embodiment of a method of forming Figures 1-2 a device according to the application in an example of an embodiment of a method of forming

[0013] Figure 8 a device according to the application in an example of an embodiment of a method of forming Figures 1-2 a device according to the application in an example of an embodiment of a method of forming

[0014] Figure 9 a device according to the application in an example of an embodiment of a method of forming Figures 1-2 a device according to the application in an example of an embodiment of a method of forming

[0015] For clarity of illustration and simplicity of description, the elements illustrated in the figures are not necessarily drawn to scale, some elements can be exaggerated, and unless otherwise specified, the same reference numerals are used throughout different figures when referring to a same or like elements. Additionally, for simplicity of description, the description can omit well-known steps and elements and details of known components and techniques. As used herein, a current carrying element or current carrying electrode means an element of a device that carries current through the device, such as a source or drain of a MOS transistor or an emitter or collector of a bipolar transistor or a cathode or anode of a diode, while a control element or control electrode means an element of a device that controls current through the device, such as a gate of a MOS transistor or a base of a bipolar transistor. Additionally, one current carrying element can carry current through the device in one direction, such as carrying current into the device, while a second current carrying element can carry current through the device in the opposite direction, such as carrying current out of the device. Although devices can be described herein as certain N-channel or P-channel devices or as certain N-type or P-type doped regions, one of ordinary skill in the art will understand that complementary devices are also possible in accordance with the present application. One of ordinary skill in the art understands that the conductivity type refers to the mechanism by which conduction occurs, such as by holes or electrons, and thus, the conductivity type refers to the type of doping, such as P-type or N-type, and not to the doping concentration. One of ordinary skill in the art will understand that the terms "during," "while," and "when" used in relation to circuit operations herein do not mean exactly immediately following the initiation of the action, but rather that there can be some minor, but reasonable, delay between the initiation of the initial action and the reaction it causes. Additionally, the term "while" means that the action occurs at least for some portion of the duration of the initiating action. The use of the words "approximately" or "substantially" means that the value of an element has a parameter that is intended to be close to the stated value or position. However, as is well known in the art, there is always a minor variation that prevents the value or position from being exactly as stated. It is recognized in the art that a deviation of up to at least ten percent (10%) (and for some elements including semiconductor doping concentrations, up to twenty percent (20%)) is a reasonable deviation from the ideal target as stated. When used in relation to signal states, the term "active" means the active state of the signal, while the term "inactive" means the inactive state of the signal. The actual voltage value or logic state of the signal, such as "1" or "0," depends on whether positive or negative logic is used. Thus, if positive logic is used, a high voltage or high logic can be active, while if negative logic is used, a low voltage or low logic can be active; while if positive logic is used, a low voltage or low state can be inactive, while if negative logic is used, a high voltage or high logic can be inactive. In this document, the positive logic convention is used, but one of ordinary skill in the art understands that the negative logic convention can also be used.The terms "first," "second," "third," etc. as used in the claims and / or the specification, e.g., in reference to a part of an element, are used to distinguish between similar elements and do not necessarily describe a temporal or spatial order between the elements. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments described herein are capable of operating in other sequences than described or illustrated herein. Reference to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, although it can be. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. For clarity, the drawings are shown with exaggerated or non-precise dimensions to illustrate the features of the device structures. It will be understood by those within the art that, in actual practice, the dopant regions can not have the precise shapes or angles shown in the drawings, but are represented with exaggerated or non-precise dimensions to illustrate the features of the device structures.

[0016] In addition, the present specification shows a cellular design in which the body region is a plurality of cellular regions, instead of a monolithic design in which the body region is a single region formed in an elongated pattern, in some embodiments generally a serpentine pattern. However, the present specification is intended to apply to both cellular implementations and single substrate implementations.

[0017] Embodiments, which will be exemplified and described as appropriate hereinafter, can lack any element of the herein described embodiments, and / or embodiments can be implemented using only elements of the herein described embodiments. DETAILED DESCRIPTION

[0018] Figure 1 An example of an enlarged plan view of a portion of an embodiment of a semiconductor device 20 formed using improved manufacturing techniques is shown. In one embodiment, the device 20 can comprise a trench MOSFET. The device 20 includes an active portion 21 configured for conducting current between active elements within the portion 21. For example, the portion 21 can be configured for forming a channel region that selectively allows current to flow from a source region to a drain region of the trench MOSFET. The device 20 also includes a non-active portion 22 that facilitates forming electrical connections to portions of the device 20 within the portion 21, but does not conduct current flow through the device 20, although some current can flow into the portion 22 to charge parasitic capacitances, etc.

[0019] In trench-type MOSFET embodiments, the device 20 includes a plurality of gate trenches 26. Each trench 26 has an active portion 33 within the portion 21 and also has a length 48 such that a non-active portion 40 of each trench 26 is within the portion 22. The gate electrode 25 extends into the portion 22 and covers the non-active portion 40 of the trench 26, but does not extend into the active portion 21. A termination trench 28 can be formed around the portions 21 and 22 to isolate the device 20 from other devices. In some embodiments, the trench 28 can have a different configuration and can be in a different location relative to the trench 26. In one embodiment, the trench 28 can be formed as a plurality of connection fields, with the trench 26 and the portions 21 and 22 being within the field.

[0020] Figure 2 An enlarged cross-sectional view of a portion of the device 20 along the section line 2-2 shown in FIG. 1 is shown. Figure 1 An enlarged cross-sectional view of a portion of the device 20 along the section line 2-2 shown in FIG. 1 is shown. Figure 2 The left-hand portion of FIG. 2 shows an example of an embodiment of the active portion 33 of the trench 26, and also shows the trench 28 formed in the active portion 21, and Figure 2 The right-hand portion of FIG. 2 shows an example of an embodiment of the non-active portion 40 of the trench 26, and also shows the trench 28 formed in the non-active portion 22.

[0021] Figure 3 An early stage in an example of an embodiment of a method of forming the device 20 is shown. The device 20 includes a substrate 30 having a surface 31. The substrate 30 is typically a silicon semiconductor substrate. The substrate 30 can include a plurality of layers not shown. For example, the substrate 30 can include a bulk silicon semiconductor substrate on which a plurality of layers can be formed, such as by epitaxy or other well-known processes. One embodiment of the substrate 30 can include a bulk silicon semiconductor substrate on which two or more epitaxial layers are formed. In addition, the substrate 30 can include a doped region doped to a particular conductivity type in which the device 20 is formed. Such configurations are well known to those skilled in the art.

[0022] An opening 46 is formed at an area where the trench 26 is to be located, the opening extending from the surface 31 a depth or distance 49 into the substrate 30. The opening 46 extends along the length 48 of the trench 26 to be formed, and also extends along a width 50 of the trench 26 to be formed. Figure 1). Openings 46 can be shaped to have a width 53 and can extend from surface 31 a depth 49 into substrate 30. In addition, openings 47 are formed that extend from surface 31 into substrate 30 in which trenches 28 will be positioned. Openings 46 are separated from each other by a distance or width 54 such that a portion of substrate 30 forms a protrusion 70 between openings 46. One embodiment can include protrusions 70 can also be formed between openings 47 and adjacent openings 46. Openings 47 can optionally be formed to extend further into substrate 30 than depth 49. Openings 47 can be formed simultaneously with openings 46 or not. In one embodiment, the bottoms of openings 46 and 47 can have a circular shape. Openings 46 and 47 can be formed by a trench etch operation well known to those skilled in the art. One embodiment can include using anisotropic etching techniques to form openings 46 and 47, or alternatively trenches 26 and 28.

[0023] One embodiment can include forming an optional insulator layer 50 on surface 31 and removing portions of layer 50 in which openings 46 and 47 are to be formed. Layer 50 can be silicon dioxide formed by oxidizing surface 31. Layer 50 and the openings therein can then be used as a mask for forming openings 46 and 47.

[0024] Figure 4 An example of a subsequent stage in one embodiment of a method of forming device 20 is shown. The widths of openings 46 and 47 are expanded near surface 31. The widths of openings 46 and 47 are expanded to a width 55 that extends a depth or distance 51 into substrate 30 from surface 31. Depth 51 is much less than depth 49. Expanding the widths of openings 46 and 47 reduces the width of protrusion 70 at surface 31 to a width 56 that extends depth 51 into substrate 30. Width 56 is less than width 54. In one embodiment, width 56 is at least about seventy nanometers (70 nm) less than width 54. Other embodiments can include width 56 can be anywhere between about seventy nanometers (70 nm) to about eighty nanometers (80 nm) less than width 54.

[0025] In one embodiment, isotropic etching can be used to expand the widths of openings 46 and 47. During the operation of expanding the widths of openings 46 and 47, portions of optional layer 50 can also be removed. Then, the remaining portions of layer 50 can be removed.

[0026] Figure 5Another subsequent stage in an embodiment of the method of forming device 20 is shown. Insulator 73 is formed along the sidewalls and the bottom of openings 46 and 47. In one embodiment, insulator 73 is formed to have a thickness or width 58 along the portion of openings 46 and 47 having width 53. In other embodiments, insulator 73 can also be formed along the sidewalls having width 55 and along surface 31 with width 58. One embodiment can include forming insulator 73 from silicon dioxide. For example, the exposed portions of substrate 30 can be oxidized to form insulator 73.

[0027] Subsequently, shield conductor 75 can be formed in the lower portion of opening 46. Terminal conductor 74 can also be formed within the remaining portion of opening 47. Conductors 74 and 75 can be formed from well-known conductor materials, such as doped polysilicon or other conductor materials.

[0028] Embodiments of forming conductors 74 and 75 can include filling openings 46 and 47 with a conductor material. In some embodiments, the conductor material can extend out of surface 31 of substrate 30 and onto or over the surface. For such embodiments, a planarization process, such as a chemical mechanical polishing (CMP) process, can be used to remove portions of the conductor material from the surface of substrate 30 and / or the surface of insulator 73 formed on surface 31. Portions of conductor 75 within opening 46 can then be removed. During the removal of the portions of conductor 75, mask 44 (shown in phantom) can be used to protect opening 47 to leave the conductor material as conductor 74 within opening 47. Mask 44 can then be removed.

[0029] Figure 6 Another subsequent step in an example of an embodiment of the method of forming device 20 is shown. Spacer insulator 76 can be formed on conductor 75 within opening 46. Those skilled in the art will appreciate that insulator 76 separates or spaces conductor 75 from gate conductor 83 Figure 2 as will be further explained below.

[0030] One embodiment of forming insulator 76 can include forming an insulator material within opening 46 and on conductor 75 such that the material fills at least a portion of the remaining portion of opening 46. The insulator material can also be formed on conductor 74. One embodiment can include forming the insulator material to fill the remaining portion of opening 46 and extend to cover surface 31, such as forming an insulator material that covers insulator 73 on surface 31 Figure 5). The material for the insulator 76 can be any of a variety of well-known insulator materials, such as silicon dioxide or other well-known insulator materials. Some embodiments can include removing a portion of the insulator material from the surface 31, for example, by planarizing the insulator material. CMP or other types of planarization procedures can be used. The removal step also removes portions of the insulator 73 on the surface 31 of the substrate 30.

[0031] A portion of the insulator material within the opening 46 can then be removed to a distance or depth 77, leaving a portion of the insulator material on the conductor 75 as the insulator 76. One embodiment can include forming a mask 60 (shown in dashed lines) covering the opening 47 during the step of removing the portion of the insulator to protect the opening 47 and the trench 28. During the step of removing the insulator material to the depth 77, portions of the insulator 73 on the sidewalls of the opening 46 are also removed, as shown by the dashed lines 68, down to the depth 77, leaving a portion of the insulator 73 on the sidewalls of the opening 46 deeper than the distance 77 to form an insulator 78 that extends from the bottom of the opening 46 toward the surface 31 at least as far as the insulator 76, and optionally adjacent to all of the insulator 76. The depth 77 is greater than the depth 51 but less than the depth 49. Methods of forming the insulators 76 and 78 are well known to those skilled in the art.

[0032] Figure 7 Another subsequent step in the example of an embodiment of a method of forming the device 20 is shown. After the insulators 76 and 78 are formed, another insulator 80 is formed on the sidewalls of the opening 46 that extends down from the surface 31 to the depth 77 or alternatively to the insulator 78. One embodiment can include forming the insulator 80 to at least the depth 77 into the opening 46. The insulator 80 has a thickness that is less than the thickness 58 of the insulator 78. A portion of the insulator 80 can sometimes be referred to as a gate insulator. In one embodiment, the insulator 80 can also be formed to extend onto the surface 31 and onto the protrusions 70 that are positioned between and adjacent to the openings 46. The insulator 80 can be one or more of a variety of well-known insulator materials that can be used as a gate insulator for a transistor. In one embodiment, the insulator 80 can be silicon dioxide formed by oxidizing silicon exposed within the opening 46 and on the surface 31. One embodiment can include a portion of the conductor 74 being oxidized to the insulator 65 even though the mask 60 covers the opening 47. The mask 60 can then be removed.

[0033] Subsequently, a gate conductor 83 can be formed in the opening 46. As will be seen further below, the conductor 83 is recessed from the surface 31 to a depth 52 such that the depth 52 from the surface 31 is greater than the depth 51. Thus, the conductor 83 extends further into the opening 46 from the depth 52.

[0034] One embodiment of a method of forming the conductor 83 can include filling the remaining portions of the openings 46 with a conductor material. The conductor material can be formed to fill the openings 46 and extend to cover the surface 31. Portions of the conductor material can be removed to leave the conductor material in the openings 46. For example, the conductor material can be planarized by CMP or other well-known methods. In some embodiments, a portion of the material of the conductor 83 can also be formed over the conductor 74 within the openings 47. The formation of the conductor 83 will be further described below.

[0035] The doped regions 85 can be formed within the substrate 30 and extend at least between the openings 46. The regions 85 can be shaped to extend substantially parallel to the surface 31. In some embodiments, the regions 85 can also extend laterally to the openings 47 and, optionally, can extend through the openings 47. In some embodiments, the regions 85 do not extend into the portion 22. The regions 85 are shaped to be positioned below the surface 31 at least a depth 84, such that the depth 84 is not less than the depth 52. In one embodiment, the depth 84 can be greater than the depth 52.

[0036] Subsequently, portions of the protrusion 70 within the active portion 21 and positioned between the openings 46 are doped to form doped regions, the doped regions 87 can have a conductivity type opposite that of the regions 85. One embodiment can include the regions 87 having N-type conductivity and the regions 85 having P-type conductivity. In one embodiment, the regions 85 can be formed in a portion of the substrate 30 having N-type conductivity. The doped regions 87 extend from the surface 31 a depth 59, such that the depth 59 is greater than the depth 51. The regions 87 extend down the sidewalls of the openings 46 having a width 55 to a sidewall having a width 53 within the protrusion 70, such that a portion of the doped regions 87 is adjacent to the insulator 80 on the sidewall of the portion of the openings 46 having the width 53. In some embodiments, the depth 59 is greater than the depth 52, such that a portion of the regions 87 abut a portion of the insulator 80 abutting the conductor 83. In one embodiment, the depth 84 is greater than the depth 59, such that the regions 87 do not extend as far as the depth 84 of the regions 85. During the formation of the regions 87, portions of the protrusion 70 adjacent to the openings 47 are masked with another mask 61 (dashed lines) similar to the mask 60, such that the doped regions 87 do not extend to be adjacent to the insulator 73 within the openings 47.

[0037] Returning to the conductor 83, portions of the conductor material within the openings 46 can be removed down to a depth 52 to leave the conductor 83 within each of the openings 46. The material used for the conductor 83 can be any of the well known conductor materials that can be used to form the gate conductor of a MOSFET. For example, the material of the conductor 83 can be doped polysilicon, or silicide, or salacided or other well known conductor materials. Those skilled in the art will appreciate that in other embodiments the order of the shaped regions 83, 87 and 85 can be different.

[0038] The mask 61 can be removed.

[0039] Figure 8 Another subsequent step in the example of an embodiment of the method of forming the device 20 is shown. An insulator 92 is formed covering the conductor 83 and the protrusions 70. In one embodiment, the insulator 92 is formed covering all of the trenches 26. One embodiment can include the insulator 92 formed covering any of the active portions 21 and the non-active portions 22 and the surface 31 between the two. The insulator 92 can have an embodiment covering all of the surface 31. One embodiment can include the insulator 92 extending sufficiently into the openings 46 to contact the conductor 83.

[0040] A stop layer 94 is formed on the insulator 92. One embodiment of the stop layer 94 covers at least all of the trenches 26 and the protrusions 70. In one embodiment, the stop layer 94 is formed covering all of the insulator 92. The opening is formed covering the layer 94 and at least the trenches 26 and the protrusions 70.

[0041] A mask 99 is applied and patterned. The mask 99 has a mask opening 97 covering a portion of the length of the protrusions 70 within the active portions 21 but not within the non-active portions 22. The mask 99 also has an opening 98 covering a portion of the conductor 83 within the non-active portions 22 but not covering a portion of the conductor 83 in the active portions 21. The opening 97 has a length of the opening 97 extending substantially parallel to the length 48 of the width of the opening 97 Figure 1 ) but the length of the opening 97 is less than the width of the portion 21. Embodiments of the opening 97 have a width of the narrower portion of the protrusions 70 Figure 4The width of the opening 98 is substantially the same as the width of the portion of the non-active portion 22. However, in other embodiments, the width can be different. The opening 98 is formed substantially simultaneously with the opening through the portion of the non-active portion 22 and covering a portion of the conductor 83. The length of the opening 98 is substantially parallel to the length 48 but less than the width of the portion 22. The openings 97 and 98 are formed in the openings by removing a lower portion of the openings, where the removal operation substantially stops upon reaching the layer 94. For example, the openings can be etched by an etchant that does not substantially etch the material of the layer 94. One embodiment can include that the layer 94 can be silicon nitride and the openings can be silicon dioxide. One embodiment can include etching the openings with an etchant that preferentially etches silicon dioxide over silicon nitride. In one embodiment, the openings can be etched with a fluorine-based etchant that does not substantially affect the material of the layer 94. Because the removal substantially stops after reaching the layer 94, the removal operation is substantially independent of the thickness of the openings.

[0042] Subsequently, the exposed portions of the layer 94 within the openings 97 and 98 (as shown by the dashed portions of the layer 94) are removed to expose the underlying portions of the insulator 92. In one embodiment, the operation of removing the exposed portions of the layer 94 substantially stops upon reaching the insulator 92. For example, the layer 94 can be etched by an etchant that does not substantially etch the material of the insulator 92. One embodiment can include that the layer 94 can be phosphosilicate glass (PSG) or silicon dioxide or other material that is not etched by an etch that etches the layer 94. In one embodiment, the operation of removing the layer 94 preferentially etches silicon and silicon dioxide over silicon nitride, so the removal does not substantially affect the material of the layers 96 or 92. One embodiment can include that the layer 94 can be etched with an etchant that does not substantially affect the material of the insulator 92.

[0043] Figure 9 Another subsequent step in the example of the embodiment of the method of forming the device 20 is shown. The opening 97 extends through the insulator 92 and through the insulator 80 to at least expose the protrusion 70 (as shown by the dashed line representing the top of the protrusion 70), or alternatively, to at least expose the region 87. Substantially simultaneously, the opening 98 also extends through the insulator 92 to at least expose the conductor 83. In one embodiment, the insulators 92 and 80 are etched through the openings 97 and 98 using an etchant that etches silicon dioxide faster than silicon or silicon nitride to remove the material of the insulators 92 and 80 and does not substantially affect the material of the protrusion 70 and the conductor 83.

[0044] Each opening 97 then extends through the corresponding protrusion 70 and region 87 to at least expose the doped region 85. One embodiment of the removal operation is selective to silicon over silicon dioxide or silicon nitride. Thus, if the opening 97 is slightly offset from the middle of the protrusion 70, the removal does not substantially affect the material of the insulator 92, and thus the removal does extend the opening 97 laterally to expose the conductor 83. Thus, because the region 87 has silicon dioxide on its sidewalls, the subsequently formed electrode 24 cannot contact the conductor 83. In addition, the portion of the opening 97 through the region 87 is substantially self-aligned with the trench 33. For example, the portion of the opening 97 can be substantially equidistant from each trench 33 on opposite sides of the opening 97. Thus, the portion of the source of the contact region 87 is self-aligned with the trench 33. Although the lower portion of the opening 97 is narrower than the upper portion of the opening 97, in some embodiments the two portions can have the same width.

[0045] Substantially simultaneously, each opening 98 can extend into the material of the corresponding conductor 83. In the case where the conductor 83 is a self-aligned silicide or a silicide material, the opening 98 will extend only slightly into the conductor 83. In the case where the conductor 83 is doped polysilicon that is not a silicide or self-aligned silicide material, the opening 98 can extend into the material of the conductor 83, as shown by the dashed line. In some embodiments, the opening 97 through the region 87 can be referred to as a source contact opening, and the opening 98 that exposes the conductor 83 can be referred to as a gate contact opening.

[0046] Forming both the openings 97 and 98 using the same removal operation saves manufacturing operations that would previously be used to form source contact openings (e.g., the openings 97) using one set of operations and to form gate contact openings (e.g., the openings 98) using a separate set of operations. Thus, the current method saves costs.

[0047] Referring back to Figures 1-2 A mask can be applied and patterned with mask openings covering at least the openings 97 and separate mask openings covering at least the openings 98. The mask openings can extend to additionally expose a portion of the openings adjacent the openings 97 and 98. A conductor material is then applied to fill the openings 97 and form the source 24 within the openings 97 and to electrically contact the doped region 87 and the doped region 85. The conductor material in the portion 21 can extend to cover the surface 31 between the openings 97 of all of the trenches 26. The conductor material also forms the gate electrode 25 in the openings 98. The conductor material in the portion 22 also extends to cover the surface 31 between the openings 98 of all of the trenches 26.

[0048] The conductor material can be any well-known conductor material. One embodiment can include the conductor material being a multi-layer metal including titanium and a titanium nitride (TiN) barrier layer.

[0049] In accordance with all of the foregoing, those skilled in the art will appreciate that examples of embodiments of methods of forming semiconductor devices can include:

[0050] providing a substrate (e.g., substrate 30) having a first surface (e.g., top surface), the substrate being a semiconductor substrate having a first conductivity type (e.g., N-type);

[0051] forming a plurality of gate trench openings (e.g., openings 46-47) having a first width (e.g., width 53) extending a first distance (e.g., distance 49) into the substrate, wherein each gate trench opening (e.g., opening of trench 33) is in an active region (e.g., region 21) of the semiconductor device and has a length (e.g., length 48) that extends, e.g., portion 40, from the active region into a non-active region (e.g., region 22) of the semiconductor device.

[0052] forming a termination trench opening (e.g., opening 47 of trench 28) having a first width extending into the substrate, wherein the termination trench opening surrounds the plurality of gate trench openings, and wherein the plurality of gate trench openings leaves a protrusion of the substrate having a second width (e.g., width 54) between each gate trench opening and also along an outer edge of the termination trench opening;

[0053] extending the first width to a third width (e.g., width 55), wherein the third width extends a second distance (e.g., distance 51) into the substrate that is less than the first distance, thereby reducing the second width of the protrusion to a fourth width (e.g., width 56), wherein the fourth width extends substantially the second distance into the substrate;

[0054] forming a first insulator (e.g., insulator 78) having a first thickness along at least a first portion of sidewalls of the plurality of gate trench openings having the first width, wherein the first insulator extends a third distance from a bottom of the plurality of gate trench openings toward the first surface;

[0055] forming a second insulator, e.g., insulator 80, having a second thickness along another portion of the sidewalls, wherein the second insulator extends from the third distance toward the first surface;

[0056] forming a gate conductor, e.g., conductor 83, in the plurality of gate trench openings and abutting the second insulator;

[0057] forming a third insulator, e.g., insulator 92, covering the gate conductor and the protrusion;

[0058] forming an etch stop layer, e.g., layer 94, on the third insulator;

[0059] forming a fourth insulator (e.g., insulator 96) overlying the etch stop layer, wherein the material of the etch stop layer is not affected by an operation to remove the material of the fourth insulator;

[0060] etching portions of the fourth insulator overlying the protrusions to form first openings through the fourth insulator, and etching portions of the fourth insulator overlying the gate conductors in the non-active region to form second openings through the fourth insulator, wherein the etching substantially stops on the etch stop layer;

[0061] extending the first openings and the second openings through the etch stop layer;

[0062] etching exposed portions of a third insulator through the first openings and into the protrusions and through the second openings to expose the gate conductors;

[0063] forming a source in the active region overlying the protrusions and the plurality of gate trench openings, and extending through the first openings to form an electrical connection with the protrusions; and

[0064] forming a gate electrode in the non-active region overlying the plurality of gate trench openings, and extending through the second openings to form an electrical connection with the gate conductors.

[0065] One embodiment of the method can also include forming the etch stop layer from a material that is not etched by an etchant that can etch the material of the fourth insulator.

[0066] Another embodiment can include forming the etch stop layer from silicon nitride.

[0067] One embodiment can also include doping portions of the protrusions to form first doped regions having a first conductivity type within the protrusions and adjacent the second insulator on the sidewalls.

[0068] An embodiment of the method can also include forming first doped regions having a second conductivity type in the substrate adjacent the second insulator and under the protrusions, wherein the first doped regions extend laterally between each of the plurality of gate trench openings.

[0069] In one embodiment, the method can include doping portions of the protrusions to form second doped regions having the first conductivity type overlying the first doped regions.

[0070] One embodiment can also include etching through the protrusions to expose at least the first doped regions.

[0071] Another embodiment can include forming the gate conductors from doped polysilicon.

[0072] An embodiment of the method can also include self-aligning silicidation of at least a portion of the gate conductors after etching the exposed portions of the third insulator.

[0073] The method can also have an implementation that can include forming a shield conductor within the plurality of gate trench openings and adjacent to the first insulator after the step of forming the first insulator.

[0074] An implementation can include forming a spacer insulator covering the shield conductor and positioned between the shield conductor and the gate conductor.

[0075] One skilled in the art will also appreciate that another example of an implementation of a method of forming a semiconductor device can include:

[0076] providing a substrate having a first surface, the substrate being a semiconductor substrate having a first conductivity type;

[0077] forming a plurality of gate trench openings having a first width (e.g., width 53) that extend a first distance (e.g., distance 49) into the substrate, wherein each gate trench opening is located in an active region (e.g., region 21) of the semiconductor device and has a length (e.g., length 48) that extends from the active region into a non-active region (e.g., region 22) of the semiconductor device, wherein the plurality of gate trench openings leave a protrusion of the substrate having a second width (e.g., width 54) that is interposed between each gate trench opening;

[0078] expanding the first width to a third width (e.g., width 55), wherein the third width extends a second distance (e.g., distance 51) into the substrate, the second distance being less than the first distance, thereby reducing the second width of the protrusion to a fourth width (e.g., width 56), wherein the fourth width extends substantially the second distance into the substrate;

[0079] forming a gate insulator (e.g., insulator 80) having a first thickness along at least a first portion of sidewalls of the plurality of gate trench openings;

[0080] forming a gate conductor (e.g., conductor 83) in the plurality of gate trench openings and adjacent to a first portion of the gate insulator, the first portion being positioned along the first width of the plurality of gate trench openings;

[0081] forming a first insulator, e.g., insulator 92, covering the gate conductor and the protrusion;

[0082] forming a stop layer, e.g., layer 94, on the first insulator;

[0083] forming a second insulator (e.g., insulator 96) covering the stop layer, wherein the material of the stop layer is not affected by an operation to remove the material of the second insulator;

[0084] removing portions of the second insulator overlying the protrusion to form a first opening through the second insulator and substantially simultaneously removing portions of the second insulator overlying the gate conductors in the non-active region of the plurality of gate trench openings to form a second opening through the second insulator, wherein the removing is substantially stopped on the stop layer;

[0085] extending the first and second openings through the stop layer;

[0086] extending the first and second openings through the exposed portions of the first insulator, including extending the first opening into the protrusion and extending the second opening to expose the gate conductors; and

[0087] forming a first electrode in the active region overlying the protrusion and the plurality of gate trench openings, wherein the first conductor extends through the first opening to form an electrical connection with the lower portion of the protrusion, and forming a gate electrode in the non-active region overlying the plurality of gate trench openings and extending through the second opening to form an electrical connection with the gate conductors.

[0088] The method can also have an embodiment that can include forming a mask overlying a portion of the plurality of gate trench openings positioned between the active region and the non-active region, wherein the first opening is exposed to a first mask opening of the mask and the second opening is exposed to a second mask opening of the mask, followed by applying a conductor material to form the first electrode and the gate electrode.

[0089] One embodiment can also include forming a first doped region having a second conductivity type within the substrate and adjacent to the gate insulator, wherein the first doped region extends between each of the gate trench openings.

[0090] In one embodiment, the method can include extending the first opening into the protrusion, including extending the first opening to contact at least the first doped region.

[0091] Another embodiment can include doping a portion of the protrusion with a first conductivity type to form a source region of the semiconductor device.

[0092] Those skilled in the art will also appreciate that examples of embodiments of the method of forming a semiconductor device can include:

[0093] providing a semiconductor substrate having a first surface;

[0094] forming a plurality of gate trench openings having a first width (e.g., width 53) that extend a first distance into the semiconductor substrate with a protrusion (e.g., protrusion 70) of the semiconductor substrate having a second width between the plurality of gate trench openings, wherein each gate trench opening has a length (e.g., link 48) along the first surface that extends from an active region of the semiconductor device into an inactive region of the semiconductor device;

[0095] expanding the first width of each gate trench opening to a third width (e.g., width 55) to achieve at least a second distance from the first surface, wherein the second distance is less than the first distance, leaving each gate trench opening with the first width along a remaining portion of the first distance, wherein expanding the first width reduces the second width of the protrusion to a fourth width (e.g., width 56) to achieve at least the second distance;

[0096] forming a gate conductor in each of the plurality of gate trench openings;

[0097] forming a first insulator, e.g., insulator 92 and / or 80, on sidewalls of the protrusion having the fourth width;

[0098] forming a stop layer, e.g., layer 94, over the first insulator;

[0099] forming a second insulator, e.g., insulator 96, over the stop layer;

[0100] forming a first opening through the second insulator that covers a portion of the protrusion in the active region and substantially simultaneously forming a second opening through the second insulator that covers a portion of the gate conductor in the inactive region, wherein the first and second openings are substantially stopped on the stop layer;

[0101] extending the first and second openings through the first insulator includes extending the first opening into the protrusion; and

[0102] forming a first electrode in the active region that covers the protrusion and the plurality of gate trench openings, wherein the first electrode extends through the first opening to form an electrical connection with the protrusion, and forming a gate electrode in the inactive region that covers the plurality of gate trench openings and extends through the second opening to form an electrical connection with the gate conductor.

[0103] Embodiments of the method can also include forming the gate conductor includes forming the gate conductor and each gate trench opening, wherein the gate conductor extends from within the active region into the inactive region.

[0104] The method can have an embodiment that can also include forming the stop layer includes forming the stop layer from a material that is not etched by an etchant that can etch the second insulator.

[0105] Another embodiment can include doping a portion of the protrusion to form a first doped region in the protrusion, wherein the doping is performed prior to the step of forming the first insulator.

[0106] In view of the entirety of the foregoing, it will be apparent that a novel device and method is disclosed. Among other features, including forming a semiconductor device having protrusions positioned between gate trenches, wherein a portion of the protrusion near the surface has a narrower width than an underlying portion of the protrusion. The narrower portion of the protrusion has a sidewall having a material on the sidewall that is substantially not etched by an etchant that etches the material of the protrusion. Resulting in self-alignment between the source contact and the active trench portion 33. Such a method of forming a semiconductor device improves the reliability of the source connection and provides a more reliable Rdson and improved UIS performance for the device.

[0107] Additionally, forming the source contact opening and the gate contact opening substantially simultaneously reduces the manufacturing cost of the semiconductor device.

[0108] While the subject matter of the specification is described with specific reference to particular preferred embodiments and exemplary implementations, the foregoing description of the drawings and the specification are merely representative and non-limiting examples of implementations of the subject matter and are not intended to limit the scope of the subject matter to the specific embodiments and implementations described, as many alternatives and variations will be readily apparent to one of skill in the art. As will be appreciated by those skilled in the art, different steps can be used to form the semiconductor device so long as the step forms a material along the sidewall of the protrusion that is substantially not etched by removing the protrusion and so long as the source contact opening and the gate contact opening are formed by substantially simultaneous operations.

[0109] The subject matter has been described with specific reference to a particular MOSFET structure, but the method is directly applicable to other transistor structures, including BiCMOS, metal semiconductor FET (MESFET), HFET, other transistor structures, and diodes.

[0110] As reflected in the claims that follow below, aspects of the present invention can have fewer than all of the features of the single embodiments disclosed in the foregoing description. Therefore, the claims that follow below are hereby expressly incorporated into the description of the drawings and each claim by itself represents an independent embodiment of the present invention. Moreover, although some embodiments described herein contain some, but not all, of the features of some other embodiments, persons of skill in the art will understand that a combination of aspects from different embodiments is within the scope of the present invention and is intended to be formed.

Claims

1. A transistor, comprising: A substrate having a first surface, the substrate comprising a semiconductor substrate of a first conductivity type; A plurality of gate trenches of a first width, extending into the substrate by a first distance and laterally separated from each other, wherein each gate trench is located in the active region of the transistor and has a length extending from the active region into the non-active region of the transistor; At least a first-width terminal trench extending into the substrate, wherein the terminal trench surrounds the plurality of gate trenches; A first insulator having a first thickness along at least a first portion of the sidewalls of the plurality of gate trenches, wherein the first insulator extends a second distance from the bottom of the plurality of gate trenches toward the first surface, and wherein the second distance is less than the first distance; The substrate has a protrusion located between adjacent gate trenches and along the outer edge of the terminal trench. A first region of the protrusion with a second width extends from the first surface to a third distance in the substrate, wherein the third distance is less than the second distance. A second region of the protrusion with a third width extends from the first region to the substrate and toward the bottom of the plurality of gate trenches. A second insulator having a second thickness along a second portion of the sidewalls of the plurality of gate trenches, the second insulator extending toward the first surface, including extending at least along the sidewalls of the first region of the protrusion; A gate conductor in the plurality of gate trenches, wherein the gate conductor is recessed from the first surface by at least the first distance, and the gate conductor is adjacent to the second insulator; A third insulator covers the gate conductor and is adjacent to the second insulator along the second portion of the sidewalls of the plurality of gate trenches; The etch stop layer on the third insulator; A fourth insulator covering the etch stop layer, wherein the material of the etch stop layer is unaffected by the operation of removing the material of the fourth insulator; A first opening extends through the fourth insulator, the etch stop layer, and the third insulator, the first opening covering the protrusion and having a fourth width greater than the second width; A second opening extends from the first opening into the first region of the protrusion, the second opening having a fifth width smaller than the second width; A source electrode covering the protrusion and the plurality of gate trenches in the active region, the source electrode extending through the first opening and the second opening to form an electrical connection to the protrusion; A third opening in the gate conductor in the non-active region covering the plurality of gate trenches, the third opening extending through the fourth insulator, the etch stop layer and the third insulator; as well as A gate electrode that covers the plurality of gate trenches in the non-active region and extends through the third opening to form an electrical connection to the gate conductor.

2. The transistor of claim 1, further comprising a first doped region of a first conductivity type, which extends within the protrusion and adjacent to the second insulator extending along the second portion of the sidewalls of the plurality of gate trenches, the first doped region extending from the first surface at a distance not less than the first distance.

3. The transistor of claim 2, further comprising a second doped region of a second conductivity type in the substrate, the second doped region being below the protrusion and extending laterally between each of the plurality of gate trenches, wherein the second doped region is adjacent to the second portion of the sidewall of the plurality of gate trenches, and wherein the source electrode forms an electrical connection to the second doped region.

4. A semiconductor device, comprising: A substrate having a first surface, the substrate comprising a semiconductor substrate of a first conductivity type; A plurality of gate trenches of a first width extending into the substrate by a first distance, wherein each gate trench is located in an active region of the semiconductor device and has a length extending from the active region into an active region of the semiconductor device; The substrate has a protrusion between each gate trench, the protrusion having a first segment with a second width at the first surface, and the protrusion having a second segment with a third width below the first segment, wherein the third width is greater than the second width; A first insulator having a first thickness, a first section of the first insulator extending along the sidewalls of the plurality of gate trenches and also along the sidewalls of a second section of the protrusion, the first insulator having a second section extending along the sidewalls of the first section of the protrusion; The gate conductor in the first section of the plurality of gate trenches and adjacent to the first insulator; A second insulator covering the first segment of the gate conductor and the first insulator; Stop layer on the second insulator; A third insulator covering the stop layer; A first electrode covering the protrusion and the plurality of gate trenches in the active region, the first electrode having a first portion extending through the third insulator, the stop layer and the second insulator, wherein the first portion of the first electrode has a fourth width not greater than the third width, and the first electrode having a first section extending from the first portion through the first section of the protrusion and entering a second portion of the second section of the protrusion to form an electrical connection to the substrate. as well as A gate electrode that covers the plurality of gate trenches in the non-active region and forms an electrical connection to the gate conductor.

5. The semiconductor device of claim 4, wherein the material of the stop layer is unaffected by the operation of removing the material of the third insulator.

6. The semiconductor device of claim 4, further comprising a first doped region of a second conductivity type formed within the substrate and adjacent to the first segment of the first insulator, wherein the first doped region extends between each gate trench.

7. The semiconductor device of claim 6, further comprising a second doped region within the first segment of the protrusion, wherein the second doped region has the first conductivity type, and the first electrode forms an electrical connection to the second doped region and the first doped region.

8. A semiconductor device, comprising: A substrate having a first surface, the substrate comprising a semiconductor substrate of a first conductivity type; A plurality of gate trenches extending to a first distance in the substrate, each gate trench having a length extending from the active region of the semiconductor device to the non-active region of the semiconductor device along the first surface; Gate conductors within each gate trench; The substrate has a protrusion between the plurality of gate trenches, the protrusion having a first segment having a first width at the first surface, the protrusion having a second width below the first segment of the protrusion, wherein the second width is greater than the first width, and the second segment of the protrusion is spaced apart from the first segment of the protrusion by a second distance, wherein the second distance is less than the first distance; A first insulator on the sidewall of the plurality of gate trenches, the first insulator being adjacent to the gate conductor and also extending along the sidewall of the first section of the protrusion; A second insulator covering the gate conductor and the first insulator on the sidewalls of the plurality of gate trenches; A first electrode covers the protrusion and the second insulator in the active region. The first electrode has a third width extending through the second insulator, wherein the third width is smaller than the second width. The first electrode has a fourth width extending into the first section of the protrusion, wherein the fourth width is smaller than the first width and smaller than the third width. The first electrode forms an electrical connection to the protrusion. as well as A gate electrode that covers the plurality of gate trenches in the non-active region and forms an electrical connection to the gate conductor.

9. The semiconductor device of claim 8, wherein the third width of the first electrode is greater than the first width of the first segment of the protrusion.

10. The semiconductor device of claim 8, further comprising doping a portion of the protrusion to form a first doped region of the first conductivity type in the first segment of the protrusion, the first doped region being adjacent to the first insulator.

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