Semiconductor device and manufacturing method thereof
By introducing strain layers and stress-providing layers into semiconductor devices and utilizing lattice mismatch to generate tensile stress, the problem of high channel resistance in shielded gate power MOSFETs is solved, achieving a tradeoff between lower on-resistance and higher breakdown voltage, thus improving device performance.
Patent Information
- Application Number
- CN202511122295.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-12
- Publication Date
- 2025-11-18
- Estimated Expiration
- 2045-08-12
AI Technical Summary
The existing shielded gate power MOSFETs have high channel resistance, resulting in a poor trade-off between on-resistance and breakdown voltage. It is necessary to improve the channel carrier mobility to reduce the total device resistance.
Introducing strain layers and stress-providing layers into semiconductor devices generates tensile stress through lattice mismatch, thereby improving carrier mobility in the channel region and reducing channel resistance.
This effectively reduces channel resistance, improves the trade-off between on-resistance and breakdown voltage, and enhances device performance and reliability.
Smart Images
Figure CN120980921A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, and in particular to a semiconductor device and a manufacturing method thereof. BACKGROUND
[0002] Power Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has the advantages of fast switching speed, high input impedance and easy driving, and is a widely used power device. Shielded gate power MOSFET is an advanced power MOSFET device that has appeared in recent years, and its core advantage is in the application of high frequency and high efficiency. By integrating a shield gate under the control gate to form a shield gate power MOSFET, the structure significantly reduces the gate-drain capacitance, effectively suppresses the voltage oscillation caused by the Miller effect, thereby reducing the switching loss. At the same time, the optimized charge balance design enables the device to achieve lower on-resistance under the same chip area, breaking through the traditional silicon limit and improving the power density. Therefore, shielded gate MOSFET is widely used in server power supply, photovoltaic inverter and new energy vehicle on-board charger fields, helping to improve system efficiency and achieve miniaturization design.
[0003] The shielded gate power MOSFET usually has a low breakdown voltage and a low epitaxial layer resistivity, so the channel resistance accounts for a high proportion in the total on-resistance. In order to further optimize the trade-off relationship between the breakdown voltage and the on-resistance of the device, the channel resistance needs to be reduced. Channel mobility is a key parameter that determines channel resistance, and improving the channel carrier mobility can effectively reduce the channel resistance, thereby reducing the total resistance of the device and achieving lower power consumption. Therefore, improving the channel carrier mobility of the shielded gate power MOSFET has become a problem to be solved. SUMMARY
[0004] The present application provides a semiconductor device and a manufacturing method thereof to improve the channel carrier mobility and reduce the channel resistance.
[0005] According to an aspect of the present application, a semiconductor device is provided, which comprises:
[0006] The semiconductor body comprises a first surface and a second surface arranged oppositely; further comprises a well region and a first region, the first region is arranged to be of a first conductivity type and is located at the first surface, the well region is arranged to be of a second conductivity type and is located at a side of the first region away from the first surface; the semiconductor body further comprises a first recess and a second recess; the first recess comprises a first sub-recess and a second sub-recess in communication; the first sub-recess extends from the first surface into the semiconductor body; the second sub-recess is located at a side of the first sub-recess away from the first surface; the second recess is located at least between the well region and the first recess;
[0007] a first insulating layer located at a bottom surface and a sidewall of the second sub-trench;
[0008] a shield gate located at a side of the first insulating layer away from the second sub-trench;
[0009] a first isolation layer located in the second sub-trench, a vertical projection of the first isolation layer on the second surface covering a vertical projection of the shield gate on the second surface and a vertical projection of the first insulating layer on the second surface;
[0010] a stress providing layer located at a sidewall of the second trench;
[0011] a strain layer located at a side of the stress providing layer away from the well region, a vertical projection of the stress providing layer on the second surface not overlapping with a vertical projection of the strain layer on the second surface, the stress providing layer configured to provide stress for the strain layer to improve carrier mobility in the strain layer;
[0012] a second insulating layer located at a sidewall of the first sub-trench;
[0013] a control gate located in the first sub-trench and at a side of the second insulating layer away from the strain layer;
[0014] a source electrode located at the first surface;
[0015] a drain electrode located at the second surface.
[0016] Optionally, the semiconductor body further comprises a third trench, the third trench located at a side of the second trench away from the first surface.
[0017] The semiconductor device further comprises a channel protection layer, the channel protection layer located in the third trench.
[0018] Optionally, an ion concentration of the channel protection layer is positively correlated with a threshold voltage of the semiconductor device.
[0019] Optionally, the stress providing layer and the strain layer in contact with the well region are configured to be of a second conductivity type and have an ion concentration less than an ion concentration of the channel protection layer.
[0020] Optionally, the second trench is further located between the first region and the first trench.
[0021] The stress providing layer and the strain layer in contact with the first region are configured to be of a first conductivity type and have an ion concentration same as an ion concentration of the first region.
[0022] Optionally, in a direction perpendicular to the first surface and pointing to the second surface, a thickness of the strain layer is greater than or equal to 5 nm and less than or equal to 20 nm, and a thickness of the stress providing layer is greater than or equal to 100 nm and less than or equal to 500 nm.
[0023] Optionally, the semiconductor body further comprises a second region, the second region is of a second conductivity type and is located at the first surface; the second region is in contact with the first region.
[0024] Optionally, the material of the stress providing layer comprises silicon germanium; and / or, the material of the strain layer comprises silicon.
[0025] According to another aspect of the present application, there is provided a method for manufacturing a semiconductor device, the method comprising:
[0026] providing a semiconductor body, the semiconductor body comprising a first surface and a second surface located opposite to each other; further comprising a first region and a well region, the first region is of a first conductivity type and is located at the first surface, the well region is of a second conductivity type and is located at a side of the first region away from the first surface; the semiconductor body further comprises a first recess and a second recess; the first recess comprises a first sub-recess and a second sub-recess which are in communication; the first sub-recess extends into the semiconductor body from the first surface; the second sub-recess is located at a side of the first sub-recess away from the first surface; the second recess is located at least between the well region and the first recess;
[0027] forming a first insulating layer on a bottom surface and a sidewall of the second sub-recess;
[0028] forming a shield gate at a side of the first insulating layer away from the second sub-recess;
[0029] forming a first isolation layer in the second sub-recess, a vertical projection of the first isolation layer on the second surface covers a vertical projection of the shield gate on the second surface and a vertical projection of the first insulating layer on the second surface;
[0030] forming a stress providing layer on a sidewall of the second recess;
[0031] forming a strain layer at a side of the stress providing layer away from the well region; a vertical projection of the stress providing layer on the second surface does not overlap with a vertical projection of the strain layer on the second surface; the stress providing layer is used to provide stress for the strain layer to improve carrier mobility in the strain layer;
[0032] forming a second insulating layer on a sidewall of the first sub-recess;
[0033] forming a control gate in the first sub-recess and at a side of the second insulating layer away from the strain layer;
[0034] forming a source electrode on the first surface;
[0035] forming a drain electrode on the second surface.
[0036] Optionally, the semiconductor body is provided by:
[0037] The semiconductor body comprises a first surface and a second surface arranged oppositely; a first region and a well region are further included, the first region is arranged as a first conductive type and is located at the first surface, and the well region is arranged as a second conductive type and is located at a side of the first region away from the first surface;
[0038] A first recess is formed at the first surface; the first recess comprises a first sub-recess and a second sub-recess which are communicated; the first sub-recess extends from the first surface into the semiconductor body; and the second sub-recess is located at a side of the first sub-recess away from the first surface;
[0039] A second recess is formed at least between the well region and the first recess.
[0040] The technical scheme of the embodiment of the present application comprises that a strain layer and a stress providing layer are sequentially arranged at a side of the second insulating layer away from the control gate, there is a lattice mismatch between the strain layer and the stress providing layer, the thickness of the strain layer and the stress providing layer is controlled, and appropriate stress is generated in the strain layer. Since the lattice constant of the stress providing layer is greater than the lattice constant of the strain layer, when the strain layer is grown on the stress providing layer, the spacing of the strain layer at the interface will be enlarged, resulting in the generation of tensile stress, and the strain layer is just located at the channel region of the semiconductor device, so that the generated tensile stress can improve the carrier mobility of the channel region, effectively reduce the channel resistance, and thus reduce the on-resistance of the semiconductor device.
[0041] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS
[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.
[0043] Figure 1 is a schematic diagram of a cross-sectional structure of a semiconductor device according to an embodiment of the present application;
[0044] Figure 2 is a schematic diagram of a cross-sectional structure of another semiconductor device according to an embodiment of the present application;
[0045] Figure 3 is a flowchart of a preparation method of a semiconductor device according to an embodiment of the present application;
[0046] Figures 4-8 According to the embodiments of the present application,Figure 3 Corresponding cross-sectional structure schematic diagram of each step in the method;
[0047] Figure 9 According to the embodiment of the present application Figure 3 Corresponding flowchart of S110 in the method;
[0048] Figures 10-13 According to the embodiment of the present application Figure 9 Corresponding cross-sectional structure schematic diagram of each step in the method. DETAILED DESCRIPTION
[0049] In order to make the personnel in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present application.
[0050] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.
[0051] Figure 1 According to the embodiment of the present application, a cross-sectional structure schematic diagram of a semiconductor device is provided. As shown in Figure 1As shown, the semiconductor device comprises: a semiconductor body 100 comprising a first surface 101 and a second surface 102 oppositely arranged; further comprising a first region 104 arranged at the first surface 101 and a well region 103 arranged at a side of the first region 104 away from the first surface 101, the first region 104 is of a first conductivity type, and the well region 103 is of a second conductivity type; the semiconductor body 100 further comprises a first recess 110 and a second recess 107; the first recess 110 comprises a first sub-recess 105 and a second sub-recess 106 which are connected; the first sub-recess 105 extends from the first surface 101 into the semiconductor body 100; the second sub-recess 106 is arranged at a side of the first sub-recess 105 away from the first surface 101; the second recess 107 is arranged between the well region 103 and the first recess 110; a first insulating layer 200 is arranged at a bottom surface and a sidewall of the second sub-recess 106; a shield gate 30 is arranged at a side of the first insulating layer 200 away from the second sub-recess 106; a first isolation layer 300 is arranged in the second sub-recess 106, a vertical projection of the first isolation layer 300 on the second surface 102 covers a vertical projection of the shield gate 30 on the second surface 102 and a vertical projection of the first insulating layer 200 on the second surface 102; a stress providing layer 600 is arranged at a sidewall of the second recess 107; a strain layer 500 is arranged at a side of the stress providing layer 600 away from the well region 103; a vertical projection of the stress providing layer 600 on the second surface 102 does not overlap with a vertical projection of the strain layer 500 on the second surface 102; the stress providing layer 600 is configured to provide stress for the strain layer 500, so as to improve a carrier mobility in the strain layer 500; a second insulating layer 400 is arranged at a sidewall of the first sub-recess 105; a control gate 40 is arranged in the first sub-recess 105 and at a side of the second insulating layer 400 away from the strain layer 500; a source electrode 60 is arranged at the first surface 101; and a drain electrode 70 is arranged at the second surface 102.
[0052] In the embodiments of the present application, the semiconductor device can include but is not limited to an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 can include a silicon carbide semiconductor body or the like third-generation wide-bandgap semiconductor material. For the N-type MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. For the P-type MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type. For example, for the N-type MOSFET, the first region 104 is an N+ doped region, and the N-type doping ions of the N+ doped region can be phosphorus (P) ions or nitrogen (N) ions; and the well region 103 is a P-well region, and the P-type doping ions of the P-well region can be aluminum (Al) ions or boron (B) ions.
[0053] For example, as shown in FIG. 1, the semiconductor device comprises: a semiconductor body 100 comprising a first surface 101 and a second surface 102 oppositely arranged; further comprising a first region 104 arranged at the first surface 101 and a well region 103 arranged at a side of the first region 104 away from the first surface 101, the first region 104 is of a first conductivity type, and the well region 103 is of a second conductivity type; the semiconductor body 100 further comprises a first recess 110 and a second recess 107; the first recess 110 comprises a first sub-recess 105 and a second sub-recess 106 which are connected; the first sub-recess 105 extends from the first surface 101 into the semiconductor body 100; the second sub-recess 106 is arranged at a side of the first sub-recess 105 away from the first surface 101; the second recess 107 is arranged between the well region 103 and the first recess 110; a first insulating layer 200 is arranged at a bottom surface and a sidewall of the second sub-recess 106; a shield gate 30 is arranged at a side of the first insulating layer 200 away from the second sub-recess 106; a first isolation layer 300 is arranged in the second sub-recess 106, a vertical projection of the first isolation layer 300 on the second surface 102 covers a vertical projection of the shield gate 30 on the second surface 102 and a vertical projection of the first insulating layer 200 on the second surface 102; a stress providing layer 600 is arranged at a sidewall of the second recess 107; a strain layer 500 is arranged at a side of the stress providing layer 600 away from the well region 103; a vertical projection of the stress providing layer 600 on the second surface 102 does not overlap with a vertical projection of the strain layer 500 on the second surface 102; the stress providing layer 600 is configured to provide stress for the strain layer 500, so as to improve a carrier mobility in the strain layer 500; a second insulating layer 400 is arranged at a sidewall of the first sub-recess 105; a control gate 40 is arranged in the first sub-recess 105 and at a side of the second insulating layer 400 away from the strain layer 500; a source electrode 60 is arranged at the first surface 101; and a drain electrode 70 is arranged at the second surface 102. Figure 1As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present application, the semiconductor body 100 can also include only the epitaxial layer 20. In other embodiments of the present application, the semiconductor body 100 can also include the substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 by one or more epitaxial processes, including chemical vapor epitaxy (CVE), molecular beam epitaxy (MBE), and atomic layer epitaxy (ALE), etc.
[0054] A strain layer 500 and a stress providing layer 600 are sequentially arranged on the side of the second insulating layer 400 away from the control gate 40. The stress providing layer 600 can only contact the well region 103, or can contact both the well region 103 and the first region 104, on the side of the stress providing layer 600 away from the strain layer 500, which is not specifically limited herein. There is a lattice mismatch between the strain layer 500 and the stress providing layer 600, and the thickness of the strain layer 500 and the stress providing layer 600 can be controlled to generate appropriate stress in the strain layer 500. Since the lattice constant of the stress providing layer 600 is greater than that of the strain layer 500, when the strain layer 500 is grown on the stress providing layer 600, the spacing of the strain layer 500 at the interface will be enlarged, resulting in the generation of tensile stress. The strain layer 500 is located in the channel region of the semiconductor device, and thus the generated tensile stress can improve the carrier mobility of the channel region, effectively reducing the channel resistance, and thus reducing the on-resistance of the semiconductor device.
[0055] The material of the shield gate 30 can be polysilicon. The material of the control gate 40 can also be polysilicon. The first insulating layer 200 is used to insulate the semiconductor body 100 and the shield gate 30. The first insulating layer 201 can be an oxide layer. The shield gate 30 is usually connected to a fixed potential (such as ground) and is used to shield the influence of the high voltage of the drain on the control gate 40. The control gate 40 is used to control the conduction and turn-off of the channel. The second insulating layer 400 is used to insulate the semiconductor body 100 and the control gate 40. The second insulating layer 400 can be an oxide layer. The first isolation layer 300 can be an isolation gate oxide layer. The first isolation layer 300 is used to insulate the shield gate 30 and the control gate 40. Metal is deposited on the first surface 101 to form the source 60. Metal is deposited on the second surface 102 to form the drain 70. The deposited metal can be titanium (Ti), nickel (Ni), or silver (Ag).
[0056] The technical scheme of the embodiment of the present application is characterized in that a strain layer and a stress providing layer are sequentially arranged on the side of the second insulating layer away from the control gate, there is a lattice mismatch between the strain layer and the stress providing layer, the thickness of the strain layer and the stress providing layer is controlled, and appropriate stress can be generated in the strain layer. Since the lattice constant of the stress providing layer is greater than the lattice constant of the strain layer, when the strain layer is grown on the stress providing layer, the spacing of the strain layer at the interface will be enlarged, resulting in the generation of tensile stress, and the strain layer is just located in the channel region of the semiconductor device, so the generated tensile stress can improve the carrier mobility of the channel region, effectively reduce the channel resistance, and thus reduce the on-resistance of the semiconductor device.
[0057] In the optional embodiment of the present application, referring to Figure 1 , the semiconductor body 100 further comprises a third groove 109; the third groove 109 is located on the side of the second groove 107 away from the first surface 101; the semiconductor device further comprises a channel protection layer 700; the channel protection layer 700 is located in the third groove 109.
[0058] In the embodiment of the present application, since there is a lattice mismatch between the strain layer 500 and the stress providing layer 600, lattice defects can be caused, and the leakage current of the semiconductor device under reverse voltage can be increased. The channel protection layer 700 is arranged on the side of the strain layer 500 and the stress providing layer 600 away from the first surface 101. The channel protection layer 700 has the same conductivity type as the well region 103, and is set to the second conductivity type. The channel protection layer 700 can be monocrystalline silicon, has few lattice defects, and the ion concentration of the channel protection layer 700 and the well region 103 is greater than the ion concentration of the strain layer 500, so that the depletion region does not penetrate to the strain layer 500 and the stress providing layer 600 when the semiconductor device is under reverse voltage, the phenomenon of increased reverse leakage caused by the recombination current of the depletion region is weakened, and the performance of the semiconductor device is improved.
[0059] In the optional embodiment of the present application, referring to Figure 1 , the ion concentration of the channel protection layer 700 is positively correlated with the threshold voltage of the semiconductor device.
[0060] In the embodiment of the present application, the threshold voltage is the critical voltage of the semiconductor device from cutoff to conduction, and directly determines the switching characteristics of the semiconductor device. By adjusting the ion concentration of the channel protection layer 700 (such as precisely controlling the amount of dopant by ion implantation process), the threshold voltage can be linearly or regularly improved. The higher the threshold voltage, the stronger the noise resistance (such as power fluctuation, signal interference or environmental electromagnetic noise) of the semiconductor device. By adjusting the ion concentration of the channel protection layer 700, the required threshold voltage can be obtained. The threshold voltage and on-resistance of the semiconductor device can be considered at the same time, and the reliability of the semiconductor device is improved.
[0061] In the optional embodiment of the present application, referring toFigure 1 The stress providing layer 600 and the strain layer 500 in contact with the well region 103 are set to the second conductive type, and the ion concentration is less than the ion concentration of the channel protection layer 700.
[0062] In the embodiment of the present application, the ion concentration of the strain layer 500 of the channel region is low, so that the channel resistance is further reduced, but the threshold voltage of the semiconductor device is not affected, and the semiconductor device is not mistakenly turned on. The ion concentration of the channel protection layer 700 is higher than that of the strain layer 500 of the channel region, so that the channel protection layer 700 is not turned on, and the semiconductor device cannot be turned on. The threshold voltage and the on-resistance of the semiconductor device can be considered at the same time, and the performance of the semiconductor device is improved.
[0063] Figure 2 Another cross-sectional structure of a semiconductor device is provided according to an embodiment of the present application. As shown in Figure 2 The second recess 107 is also located between the first region 104 and the first recess 110; the stress providing layer 600 and the strain layer 500 in contact with the first region 104 are set to the first conductive type, and the ion concentration is the same as that of the first region 104.
[0064] In the embodiment of the present application, the conductive type and the ion concentration of the stress providing layer 600 and the strain layer 500 in contact with the first region 104 are the same as those of the first region 104. The ion implantation to the stress providing layer 600 and the strain layer 500 in contact with the first region 104 can be completed at the same time when the ion implantation to the first region 104 is performed, thereby saving the preparation cost and saving the preparation time.
[0065] In the optional embodiment of the present application, referring to Figure 1 In the direction X perpendicular to the first surface 101 and pointing to the second surface 102, the thickness of the strain layer 500 is greater than or equal to 5 nm and less than or equal to 20 nm, and the thickness of the stress providing layer 600 is greater than or equal to 100 nm and less than or equal to 500 nm.
[0066] In the embodiment of the present application, the strain layer 500 changes the energy band structure of the channel region by introducing lattice strain, thereby improving the mobility of the carriers and ultimately improving the switching speed and current driving capability of the semiconductor device. In the direction X perpendicular to the first surface 101 and pointing to the second surface 102, the thickness of the strain layer 500 is controlled to be greater than or equal to 5 nm and less than or equal to 20 nm, so that efficient stress transmission can be maintained, and the channel region can be accurately covered, avoiding the reduction of stress enhancement effect caused by invalid thickness. The strain layer 500 of 5 nm to 20 nm can reduce the generation of defects and improve the yield of the semiconductor device.
[0067] The stress providing layer 600 is configured to continuously provide stable stress to the strain layer 500 by lattice mismatch. In the direction X which is perpendicular to the first surface 101 and points to the second surface 102, the thickness of the stress providing layer 600 is controlled to be greater than or equal to 100 nm and less than or equal to 500 nm, so that the stress providing layer 600 can provide sufficient stress reserve for the strain layer 500, avoid stress attenuation, and provide sufficient structural support for the semiconductor device to improve the reliability of the semiconductor device.
[0068] In an optional embodiment of the present application, referring to Figure 1 The semiconductor body 100 further comprises a second region 108 which is of the second conductivity type and is located at the first surface 101; the second region 108 is in contact with the first region 104.
[0069] In an embodiment of the present application, the second region 108 is of the same conductivity type as the well region 103, i.e. both are of the second conductivity type. For an N-type MOSFET, the second region 108 can be a P+ doped region with a higher ion concentration than the well region 103. The second region 108 is configured to form a good ohmic contact with the source 60.
[0070] In an optional embodiment of the present application, referring to Figure 1 The semiconductor device further comprises a passivation layer 80 which is located at the first surface 101 and covers the control gate 40, the second insulating layer 400 and the second strain insulating layer 500. The passivation layer 80 is configured to isolate the semiconductor device from water vapor, oxygen or dust in the external environment, and prevent these substances from entering the interior of the semiconductor device to cause corrosion, short circuit or performance degradation. The material of the passivation layer 80 includes but is not limited to silicon oxide, silicon nitride or polyimide.
[0071] In an optional embodiment of the present application, referring to Figure 1 The material of the stress providing layer 600 comprises silicon germanium; and / or, the material of the strain layer 500 comprises silicon.
[0072] In an embodiment of the present application, the material of the stress providing layer 600 comprises silicon germanium (SiGe), and the material of the strain layer 500 comprises silicon (Si). The main difference between SiGe and Si is the lattice constant. The lattice constant of SiGe increases linearly with the increase of germanium content. The lattice mismatch between SiGe and Si is the source of stress. The lattice constant of SiGe is greater than that of Si, so the strain layer 500 which is made of Si is "expanded" by the stress providing layer 600 which is made of SiGe, forming tensile strain and improving the carrier mobility of the channel region.
[0073] It should be noted that when the semiconductor device is an N-type MOSFET, the first conductivity type is N type, the second conductivity type is P type, the stress providing layer 600 provides a tensile stress to the strain layer 500, the strain layer 500 serves as a channel region of the semiconductor device, and the tensile stress provided by the stress providing layer 600 can improve the electron mobility of the channel region. When the semiconductor device is a P-type MOSFET, the first conductivity type is P type, the second conductivity type is N type, the strain layer 500 provides a compressive stress to the stress providing layer 600, the stress providing layer 600 serves as a channel region of the semiconductor device, and the compressive stress provided by the strain layer 500 can improve the hole mobility of the channel region.
[0074] Figure 3 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application. As shown in Figure 3 , the method for manufacturing a semiconductor device includes:
[0075] S110, providing a semiconductor body, the semiconductor body including oppositely arranged first and second surfaces; further including a first region arranged as a first conductivity type and located at the first surface, and a well region arranged as a second conductivity type and located at a side of the first region away from the first surface; the semiconductor body further including a first recess and a second recess; the first recess including a first sub-recess and a second sub-recess in communication; the first sub-recess extending from the first surface into the semiconductor body; the second sub-recess being located at a side of the first sub-recess away from the first surface; the second recess being located at least between the well region and the first recess.
[0076] Referring to Figure 4 , a semiconductor body 100 is provided, the semiconductor body 100 including oppositely arranged first and second surfaces 101 and 102; further including a first region 104 arranged as a first conductivity type and located at the first surface 101, and a well region 103 arranged as a second conductivity type and located at a side of the first region 104 away from the first surface 101; the semiconductor body 100 further including a first recess 110 and a second recess 107; the first recess 110 including a first sub-recess 105 and a second sub-recess 106 in communication; the first sub-recess 105 extending from the first surface 101 into the semiconductor body 100; the second sub-recess 106 being located at a side of the first sub-recess 105 away from the first surface 101; the second recess 107 being located at least between the well region 103 and the first recess 110. The semiconductor body 100 further includes a second region 108 arranged as a second conductivity type and located at the first surface 101; the second region 108 being in contact with the first region 104.
[0077] In this embodiment of the invention, the semiconductor device includes, but is not limited to, an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 may include a third-generation wide-bandgap semiconductor material such as silicon carbide semiconductor body. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type. For example, for an N-type MOSFET, the first region 104 is an N+ doped region, and the N-type dopant ions in the N+ doped region can be phosphorus (P) ions or nitrogen (N) ions; the well region 103 is a P-well region, and the P-type dopant ions in the P-well region can be aluminum (Al) ions or boron (B) ions.
[0078] like Figure 1 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed by one or more epitaxial processes on the substrate 10, including chemical vapor deposition (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).
[0079] S120, A first insulating layer is formed on the bottom surface and sidewalls of the second sub-groove.
[0080] refer to Figure 5 On the bottom surface and sidewalls of the second sub-groove 106, a first insulating layer 200 is grown by deposition or thermal oxidation.
[0081] S130, a shielding gate is formed on the side of the first insulating layer away from the second sub-groove.
[0082] refer to Figure 5 Polysilicon is filled on the side of the first insulating layer 200 away from the second sub-groove 106 to form a shielding gate 30.
[0083] S140, A first isolation layer is formed in the second sub-groove, the vertical projection of the first isolation layer on the second surface covers the vertical projection of the shielding gate on the second surface and the vertical projection of the first insulating layer on the second surface.
[0084] refer to Figure 6 Silicon oxide can be deposited within the second sub-groove 106 to form a first isolation layer 300. The first isolation layer 300 can be an isolation oxide layer. The vertical projection of the first isolation layer 300 onto the second surface 102 covers the vertical projection of the shielding gate 30 onto the second surface 102 and the vertical projection of the first insulating layer 200 onto the second surface 102.
[0085] S150, forming a stress providing layer on the sidewall of the second recess.
[0086] Referring to Figure 7 A thin layer of silicon germanium is grown on the sidewall of the second recess 107 to form a stress providing layer 600.
[0087] S160, forming a strain layer on the side of the stress providing layer away from the well region; the vertical projection of the stress providing layer on the second surface does not overlap with the vertical projection of the strain layer on the second surface; the stress providing layer is configured to provide stress to the strain layer to improve the carrier mobility in the strain layer.
[0088] Referring to Figure 7 A thin layer of silicon is grown on the side of the stress providing layer 600 away from the well region 103 to form a strain layer 500; the vertical projection of the stress providing layer 600 on the second surface 102 does not overlap with the vertical projection of the strain layer 500 on the second surface 102; the stress providing layer 600 is configured to provide stress to the strain layer 500 to improve the carrier mobility in the strain layer 500. The thickness of the thin layer of silicon germanium and the thin layer of silicon is adjusted to achieve a desired stress.
[0089] S170, forming a second insulating layer on the sidewall of the first sub-recess.
[0090] Referring to Figure 8 A second insulating layer 400 is formed on the sidewall of the first sub-recess 105 by chemical vapor deposition, and the second insulating layer 400 is densified by high temperature annealing. The use of thermal oxidation method is avoided to affect the strain layer 500.
[0091] S180, forming a control gate in the first sub-recess and on the side of the second insulating layer away from the strain layer.
[0092] Referring to Figure 8 The first sub-recess 105 is filled with polysilicon on the side of the second insulating layer 400 away from the strain layer 500 to form a control gate 40.
[0093] S190, forming a source electrode on the first surface.
[0094] Referring to Figure 1 A metal is deposited on the first surface 101 to form a source electrode 60.
[0095] S200, forming a drain electrode on the second surface.
[0096] Referring to Figure 1 A metal is deposited on the second surface 102 to form a drain electrode 70.
[0097] The technical scheme of the embodiment of the present application forms a strain layer and a stress providing layer in sequence on the side of the second insulating layer away from the control gate, there is a lattice mismatch between the strain layer and the stress providing layer, the thickness of the strain layer and the stress providing layer is controlled, and proper stress can be generated in the strain layer. Since the lattice constant of the stress providing layer is greater than the lattice constant of the strain layer, when the strain layer is grown on the stress providing layer, the strain layer spacing at the interface will be enlarged, resulting in the generation of tensile stress, and the strain layer is just located in the channel region of the semiconductor device, so the generated tensile stress can improve the carrier mobility of the channel region, effectively reduce the channel resistance, and thus reduce the on-resistance of the formed semiconductor device.
[0098] Figure 9 is provided according to the embodiment of the present application Figure 3 The flowchart included in S110. As shown in Figure 9 S110, the semiconductor body includes:
[0099] S1101, the semiconductor body includes oppositely arranged first and second surfaces; further includes a well region and a first region, the first region is arranged to be of a first conductivity type and is located at the first surface, and the well region is arranged to be of a second conductivity type and is located at the side of the first region away from the first surface.
[0100] Referring to Figure 10 , the semiconductor body 100 includes oppositely arranged first and second surfaces 101 and 102; further includes a well region 103 and a first region 104, the first region 104 is arranged to be of a first conductivity type and is located at the first surface 101, and the well region 103 is arranged to be of a second conductivity type and is located at the side of the first region 104 away from the first surface 101. The semiconductor body 100 further includes a second region 108, the second region 108 is arranged to be of a second conductivity type and is located at the first surface 101; the second region 108 is in contact with the first region 104.
[0101] S1102, a first recess is formed on the first surface; the first recess includes a first sub-recess and a second sub-recess in communication; the first sub-recess extends from the first surface into the semiconductor body; and the second sub-recess is located at the side of the first sub-recess away from the first surface.
[0102] Referring to Figure 11 , a first mask layer 120 is deposited on the first surface 101, and a first recess 110 is formed on the first surface 101 by photolithography and etching. In the first recess 110, a shielding gate oxide layer is grown by deposition or thermal oxidation, and then polycrystalline silicon is filled in the first recess 110 on the side of the shielding gate oxide layer away from the first recess 110. Then the first mask layer 120 is removed.
[0103] Referring to Figure 12The shielding gate oxide layer and polysilicon are etched back. The remaining shielding gate oxide layer is the first insulating layer 200, and the remaining polysilicon is the shielding gate 30. The trench where the first insulating layer 200 and the shielding gate 30 are located is the second sub-groove 106, and the part of the first groove 110 other than the second sub-groove 106 is the first sub-groove 105.
[0104] It should be noted that in the actual preparation process, the first groove 110 can be formed first, followed by the trap region 103, the first region 104, and the second region 108; or the trap region 103, the first region 104, and the second region 108 can be formed first, followed by the first groove 110. The embodiments of the present invention do not make specific limitations here.
[0105] S1103, A second groove is formed at least between the trap area and the first groove.
[0106] refer to Figure 12 A second mask layer 121 is deposited on the first surface 101, and a second groove 107 is formed between the well region 103 and the first groove 110 and between the first region 104 and the first groove 110.
[0107] refer to Figure 13 A third groove 109 is formed on the side of the second groove 107 away from the first surface 101, and a channel protective layer 700 is formed in the third groove 109 by ion implantation.
[0108] exist Figure 13 On this basis, an isolation oxide layer is deposited, with the side of the layer away from the second surface 102 being flush with the side of the trench protective layer 700 away from the second surface 102.
[0109] refer to Figure 2 A SiGe thin layer and a Si thin layer are epitaxially grown on the sidewall of the second recess 107 to form a stress-providing layer 600 and a strain layer 500, respectively. The thicknesses of the SiGe and Si thin layers are adjusted to achieve the desired stress. The isolation oxide layer is then etched back so that the side away from the second surface 102 is flush with or lower than the side of the channel protection layer 700 near the second surface 102. A second insulating layer 400 is then formed on the sidewall of the first sub-recess 105 using chemical vapor deposition, and densified by high-temperature annealing. Thermal oxidation is avoided to prevent it from affecting the strain layer 500. Polysilicon is filled in the first sub-recess 105 on the side of the second insulating layer 400 away from the strain layer 500 to form a control gate 40. The first surface 101 is chemically mechanically polished to remove the second mask layer 121.
[0110] The subsequent manufacturing steps are the same as those in S190-S220, and will not be repeated here.
[0111] It should be understood that the various forms of flow shown above can be used to reorder, add, or delete steps. For example, the steps described in the present application can be performed in parallel, in series, or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, which are not limited herein.
[0112] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.
Claims
1. A semiconductor device, characterized in that, include: A semiconductor body includes a first surface and a second surface disposed opposite to each other; it also includes a well region and a first region, the first region being configured with a first conductivity type and located on the first surface, and the well region being configured with a second conductivity type and located on the side of the first region away from the first surface; the semiconductor body further includes a first groove and a second groove; the first groove includes a first sub-groove and a second sub-groove that are connected; the first sub-groove extends from the first surface into the semiconductor body; the second sub-groove is located on the side of the first sub-groove away from the first surface; the second groove is located at least between the well region and the first groove; The first insulating layer is located on the bottom surface and sidewalls of the second sub-groove; The shielding gate is located on the side of the first insulating layer away from the second sub-groove; A first isolation layer is located within the second sub-groove, and the vertical projection of the first isolation layer on the second surface covers the vertical projection of the shielding gate on the second surface and the vertical projection of the first insulating layer on the second surface. A stress-providing layer is located on the sidewall of the second groove; A strain layer is located on the side of the stress-providing layer away from the well region; the vertical projection of the stress-providing layer on the second surface does not overlap with the vertical projection of the strain layer on the second surface. The stress-providing layer is used to provide stress to the strain layer, thereby improving the carrier mobility within the strain layer; The second insulating layer is located on the sidewall of the first sub-groove; The control gate is located within the first sub-groove and on the side of the second insulating layer away from the strain layer; The source electrode is located on the first surface; The drain electrode is located on the second surface.
2. The semiconductor device according to claim 1, characterized in that, The semiconductor body further includes a third groove; the third groove is located on the side of the second groove away from the first surface; The semiconductor device further includes a channel protection layer; the channel protection layer is located within the third groove.
3. The semiconductor device according to claim 2, characterized in that, The ion concentration of the channel protection layer is positively correlated with the threshold voltage of the semiconductor device.
4. The semiconductor device according to claim 2, characterized in that, The stress-providing layer and the strain layer in contact with the well region are configured as a second conductivity type, and their ion concentrations are lower than those of the channel protection layer.
5. The semiconductor device according to claim 1, characterized in that, The second groove is also located between the first region and the first groove; The stress-providing layer and the strain layer in contact with the first region are configured with a first conductivity type, and the ion concentration is the same as that of the first region.
6. The semiconductor device according to claim 1, characterized in that, In the direction perpendicular to the first surface and pointing to the second surface, the thickness of the strain layer is greater than or equal to 5 nm and less than or equal to 20 nm, and the thickness of the stress-providing layer is greater than or equal to 100 nm and less than or equal to 500 nm.
7. The semiconductor device according to claim 1, characterized in that, The semiconductor body further includes a second region, which is configured with a second conductivity type and is located on the first surface; the second region is in contact with the first region.
8. The semiconductor device according to claim 1, characterized in that, The material of the stress-providing layer includes silicon germanium; and / or, the material of the strain layer includes silicon.
9. A method for manufacturing a semiconductor device, characterized in that, include: A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other; it also includes a well region and a first region, the first region being configured with a first conductivity type and located on the first surface, and the well region being configured with a second conductivity type and located on a side of the first region away from the first surface; the semiconductor body also includes a first groove and a second groove; the first groove includes a first sub-groove and a second sub-groove communicating with each other; the first sub-groove extends from the first surface into the semiconductor body; the second sub-groove is located on the side of the first sub-groove away from the first surface; the second groove is located at least between the well region and the first groove; A first insulating layer is formed on the bottom surface and sidewalls of the second sub-groove; A shielding gate is formed on the side of the first insulating layer away from the second sub-groove; A first isolation layer is formed in the second sub-groove, and the vertical projection of the first isolation layer on the second surface covers the vertical projection of the shielding gate on the second surface and the vertical projection of the first insulating layer on the second surface. A stress-providing layer is formed on the sidewall of the second groove; A strain layer is formed on the side of the stress-providing layer away from the well region; The vertical projection of the stress-providing layer on the second surface does not overlap with the vertical projection of the strain layer on the second surface; The stress-providing layer is used to provide stress to the strain layer, thereby improving the carrier mobility within the strain layer; A second insulating layer is formed on the sidewall of the first sub-groove; A control gate is formed within the first sub-groove and on the side of the second insulating layer away from the strain layer; A source electrode is formed on the first surface; A drain electrode is formed on the second surface.
10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The semiconductor body includes: A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other; it also includes a well region and a first region, the first region being configured with a first conductivity type and located on the first surface, and the well region being configured with a second conductivity type and located on the side of the first region away from the first surface; A first groove is formed on the first surface; the first groove includes a first sub-groove and a second sub-groove that are connected; the first sub-groove extends from the first surface into the semiconductor body; the second sub-groove is located on the side of the first sub-groove away from the first surface; a second groove is formed at least between the well region and the first groove.
Citation Information
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