Semiconductor power device and preparation method thereof

Abstract

The invention discloses a semiconductor power device and a preparation method thereof. The device comprises a plurality of cellular structures arranged in an array; wherein the periphery of the edge of each cellular structure is provided with a trench gate structure, and the trench gate structures surround the channel region; the device comprises a substrate; a first epitaxial layer; the second epitaxial layer is arranged on the side, away from the substrate, of the first epitaxial layer, the second epitaxial layer comprises a body region, and a channel region is arranged on the periphery, close to the edge of the trench gate structure, of the body region; the trench gate structures extend into the first epitaxial layer from the surface of one side, far away from the substrate, of the second epitaxial layer, and at least part of a channel region is arranged between two adjacent trench gate structures; and the strain passivation layers are arranged at the positions of at least two vertex angles of the cellular structure, cover the side walls of the trench gate structures, and are in contact with the channel region in the second epitaxial layer. Stress can be introduced into the channel region of the trench gate power device, the channel carrier mobility is improved, and the channel resistance is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor power device and a preparation method thereof. BACKGROUND

[0002] Power Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has the advantages of fast switching speed, high input impedance and easy driving, and is the most widely used power device.

[0003] The trench gate power MOSFET greatly improves the cell density and eliminates the resistance of the Junction Field-Effect Transistor (JFET) region due to its unique vertical trench gate structure, and is significantly superior to the traditional planar MOSFET device in performance. For low-voltage trench gate power MOSFET, the channel resistance accounts for a large proportion of the on-resistance. In order to reduce the channel resistance, strain can be introduced on the silicon material in the channel region. However, for the trench gate power MOSFET with longitudinal structure, it is difficult to introduce stress in the channel region. SUMMARY

[0004] The present application provides a semiconductor power device and a preparation method thereof to solve the problem that it is difficult to introduce stress in the channel region of the trench gate power device, improve the channel carrier mobility, and reduce the channel resistance.

[0005] According to an aspect of the present application, a semiconductor power device and a preparation method thereof are provided, comprising a plurality of cell structures arranged in an array; wherein a trench gate structure is arranged around the edge of each cell structure, and the trench gate structure surrounds a channel region.

[0006] The semiconductor power device comprises:

[0007] A substrate is arranged as a first conductive type;

[0008] A first epitaxial layer is arranged as the first conductive type and located on one side surface of the substrate;

[0009] A second epitaxial layer is arranged on the side of the first epitaxial layer away from the substrate, and the second epitaxial layer comprises a body region arranged as a second conductive type, and the body region is arranged as a channel region around the edge of the trench gate structure. The trench gate structure extends from the surface of the second epitaxial layer away from the substrate to the inside of the first epitaxial layer, and at least part of the channel region is arranged between two adjacent trench gate structures.

[0010] A strain passivation layer is disposed at at least two of the top corners of the cell structure, covering sidewalls of the trench gate structure, and the strain passivation layer is in contact with the channel region in the second epitaxial layer.

[0011] Optionally, the trench gate structure comprises a gate oxide layer and a gate electrode, the gate oxide layer wrapping the sidewalls and bottom of the gate electrode;

[0012] The width of the strain passivation layer is greater than the thickness of the gate oxide layer wrapping the sidewalls of the gate electrode.

[0013] Optionally, the orthographic projection of the cell structure on the substrate is square;

[0014] Along the extension direction of the edges of the cell structure, the two sides of each channel region correspond to four top corner positions each provided with the strain passivation layer.

[0015] Optionally, the first conductivity type is N-type, and the strain passivation layer comprises a film layer with compressive stress prepared by a first preset process using an insulating material with internal stress;

[0016] Alternatively, the first conductivity type is P-type, and the strain passivation layer comprises a film layer with tensile stress prepared by a second preset process using an insulating material with internal stress;

[0017] The first preset process comprises at least one of a first radio frequency power, a first substrate temperature, a first reaction gas ratio, and a first deposition pressure; and the second preset process comprises at least one of a second radio frequency power, a second substrate temperature, a second reaction gas ratio, and a second deposition pressure.

[0018] The first radio frequency power is greater than the second radio frequency power;

[0019] The first substrate temperature is greater than the second substrate temperature;

[0020] The first reaction gas ratio is less than the second reaction gas ratio;

[0021] The first deposition pressure is less than the second deposition pressure.

[0022] Optionally, the strain passivation layer comprises Si3N4 or Al2O3.

[0023] Optionally, the second epitaxial layer further comprises a source contact region and an active region;

[0024] The source contact region is of the second conductivity type, and the active region is of the first conductivity type;

[0025] The source contact region and the active region are arranged on the same layer on the side of the body region away from the first epitaxial layer, and the active region is arranged around the edge of the source contact region.

[0026] Optionally, the semiconductor power device further comprises:

[0027] A source metal layer and an insulating layer are arranged on the same layer on the side of the second epitaxial layer away from the first epitaxial layer, and the source metal layer covers the source contact region and part of the active region, and the insulating layer is arranged around the edge of the source metal layer.

[0028] A drain metal layer is arranged on the side of the substrate away from the first epitaxial layer.

[0029] According to another aspect of the present application, a semiconductor power device preparation method is provided, comprising:

[0030] A substrate is provided; the substrate is arranged as a first conductive type;

[0031] A first epitaxial layer is formed on one side surface of the substrate; wherein the first epitaxial layer is arranged as the first conductive type, and a groove is arranged around the edge of the first epitaxial layer, the groove is arranged by extending inward from the surface of the side of the first epitaxial layer away from the substrate, and the groove is provided with a recess corresponding to at least two vertex positions.

[0032] A strain passivation layer is formed in the recess;

[0033] A trench gate structure is formed in the groove;

[0034] A second epitaxial layer is formed on the side surface of the first epitaxial layer away from the substrate; wherein the second epitaxial layer comprises a body region, the body region is arranged as a second conductive type, and the body region is a channel region around the edge of the trench gate structure; the strain passivation layer covers the side wall of the trench gate structure, and the strain passivation layer is in contact with the channel region in the second epitaxial layer.

[0035] Optionally, the strain passivation layer formed in the recess comprises:

[0036] A strain material layer is formed in the groove; the strain material layer covers the side wall and the bottom of the groove;

[0037] The strain material layer is subjected to a patterning process and etching, the strain material layer at the bottom of the groove is removed, and the strain passivation layer filling the recess is formed.

[0038] Optionally, the trench gate structure formed in the groove comprises:

[0039] forming a gate oxide layer on the sidewall and the bottom of the trench;

[0040] forming a gate electrode on the surface of the gate oxide layer;

[0041] forming a second epitaxial layer on the side surface of the first epitaxial layer away from the substrate, comprising:

[0042] forming the body region by ion implantation from the side surface of the first epitaxial layer away from the substrate to the inside;

[0043] forming the source contact region by ion implantation from the center region of the side surface of the body region away from the substrate to the inside, and forming the active region by ion implantation from the edge region of the side surface of the body region away from the substrate to the inside, to form the second epitaxial layer;

[0044] the semiconductor power device preparation method further comprises:

[0045] forming a source metal layer and an insulating layer on the side of the second epitaxial layer away from the first epitaxial layer; the source metal layer covers the source contact region and part of the active region, and the insulating layer is arranged around the edge of the source metal layer;

[0046] forming a drain metal layer on the side surface of the substrate away from the first epitaxial layer.

[0047] The semiconductor power device provided by the embodiment of the present application comprises a plurality of cell structures arranged in an array, and a trench gate structure is arranged around the edge of each cell structure, and the trench gate structure surrounds the channel region of each cell structure. The semiconductor power device comprises a substrate, a first epitaxial layer and a second epitaxial layer arranged in layers, wherein the second epitaxial layer comprises a body region and a channel region arranged around the periphery of the body region. The power device further comprises a strain passivation layer arranged at at least two top corner positions of the cell structure, the strain passivation layer extends from the surface of the second epitaxial layer to the inside of the first epitaxial layer and is arranged to cover the sidewall of the trench gate structure at the top corner position, and the strain passivation layer is in direct contact with the channel region. Since the strain passivation layer itself has a certain internal stress, the direct contact between the strain passivation layer and the channel region can introduce corresponding strain in the channel region through the deformation caused by the internal stress of the strain passivation layer, so as to improve the carrier mobility of the power device, effectively reduce the channel resistance, further optimize the relationship between the breakdown voltage and the on-resistance of the power device, and help to improve the performance of the device.

[0048] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent through the following description. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0050] Figure 1 is a top view structural schematic diagram of a semiconductor power device provided according to an embodiment of the present application;

[0051] Figure 2 is Figure 1 is a sectional view structural schematic diagram along the direction of A-A' in the above-mentioned

[0052] Figure 3 is Figure 1 is a sectional view structural schematic diagram along the direction of B-B' in the above-mentioned

[0053] Figure 4 is a top view structural schematic diagram of a semiconductor power device provided by the related art;

[0054] Figure 5 is Figure 4 is a sectional view structural schematic diagram along the direction of C-C' in the above-mentioned

[0055] Figure 6 is Figure 4 is a sectional view structural schematic diagram along the direction of D-D' in the above-mentioned

[0056] Figure 7 is a top view structural schematic diagram of another semiconductor power device provided according to an embodiment of the present application;

[0057] Figure 8 is a top view structural schematic diagram of a semiconductor power device provided according to an embodiment of the present application Figure 7 is a sectional view structural schematic diagram along the direction of E-E' in the above-mentioned

[0058] Figure 9 is a stress direction schematic diagram in a semiconductor power device provided according to an embodiment of the present application;

[0059] Figure 10 is a stress direction schematic diagram in another semiconductor power device provided according to an embodiment of the present application;

[0060] Figure 11 is a flow chart of a semiconductor power device preparation method provided according to an embodiment of the present application;

[0061] Figures 12 to 19 is Figure 11 is a sectional view structural schematic diagram corresponding to each step in the above-mentioned

[0062] Figure 20 is Figure 11 a specific flowchart of step S130 in the method 1000;

[0063] Figure 21 and Figure 22 is Figure 20 a specific flowchart of step S130 in the method 1000;

[0064] Figure 23 is Figure 11 a specific flowchart of step S140 in the method 1000;

[0065] Figure 24 and Figure 25 is Figure 11 a specific flowchart of step S140 in the method 1000;

[0066] Figure 26 is Figure 11 a specific flowchart of step S150 in the method 1000. DETAILED DESCRIPTION

[0067] In order to make the person skilled in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor should belong to the scope of protection of the present application.

[0068] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0069] As described in the background, for low voltage trench gate power MOSFET, the channel resistance accounts for a large proportion in the on-resistance. In order to further optimize the trade-off between the breakdown voltage and the on-resistance of the device, the channel resistance of the device needs to be reduced. The channel carrier mobility is a key parameter to determine the channel resistance, and the improvement of the channel carrier mobility can effectively reduce the channel resistance, thereby reducing the total resistance of the device, so that the device can achieve lower power consumption. Researchers indicate that by applying strain to the silicon material, the average conductivity effective mass of the silicon material can be reduced and the inter-valley scattering can be inhibited, so that the mobility of the carrier in the strained silicon material is improved. The introduction of tensile strain in the channel region can improve the electron mobility, and the introduction of compressive strain in the channel region can improve the hole mobility.

[0070] In a complementary metal-oxide-semiconductor (CMOS) circuit, the strain silicon technology is widely used to improve the channel mobility of small size MOS devices. Since the channel of the small size MOS device in the CMOS circuit is located on the surface of the silicon wafer, it is relatively easy to introduce stress in the channel region in the process. However, for the trench gate power MOSFET with a vertical structure, since the channel region is located inside the silicon wafer and perpendicular to the surface of the silicon wafer, it is difficult to introduce stress in the channel region of the trench gate power MOSFET.

[0071] Based on the above technical problems, the embodiments of the present application provide the following technical solutions:

[0072] The embodiments of the present application provide a semiconductor power device. Figure 1 A top view structural schematic diagram of a semiconductor power device is provided in the embodiments of the present application. Referring to Figure 1 The semiconductor power device includes a plurality of cell structures 01 arranged in an array; wherein a trench gate structure 02 is arranged around the edge of each cell structure 01, and the trench gate structure 02 surrounds the channel region 03. The semiconductor power device includes a plurality of cell structures 01 arranged in an array, and the trench gate structure 02 is arranged between the adjacent two cell structures 01, and the trench gate structure 02 is arranged around each cell structure 01 in the interval between the adjacent two cell structures 01, and the trench gate structure 02 is shared by the adjacent two cell structures 01. The edge of each cell structure 01 is the channel region 03, and the trench gate structure 02 is directly contacted and arranged outside the channel region 03. Figure 2 is Figure 1 A cross-sectional structural schematic diagram of the device along the A-A' direction is shown in Figure 3 is Figure 1 A cross-sectional structural schematic diagram of the device along the B-B' direction is shown in Figures 1 to 3As shown, the semiconductor power device comprises a substrate 100, a first epitaxial layer 110, a second epitaxial layer 120 and a strain passivation layer 130.

[0073] The substrate 100 is of a first conductivity type;

[0074] The first epitaxial layer 110 is of the first conductivity type and is located on one side surface of the substrate 100;

[0075] The second epitaxial layer 120 is located on the side of the first epitaxial layer 110 away from the substrate 100, and comprises a body region 121 of a second conductivity type, and the body region 121 is arranged as a channel region 03 around the edge of the trench gate structure 02. The trench gate structure 02 extends from the surface of the second epitaxial layer 120 away from the substrate 100 to the inside of the first epitaxial layer 110, and at least part of the channel region 03 is arranged between two adjacent trench gate structures 02;

[0076] The strain passivation layer 130 is arranged at least at two top corner positions of the cell structure 01, covers the sidewall of the trench gate structure 02, and the strain passivation layer 130 is in contact with the channel region 03 in the second epitaxial layer 120.

[0077] Specifically, the substrate 100 can be a semiconductor material substrate of a first conductivity type, the first epitaxial layer 110 can be a semiconductor material epitaxial layer of the first conductivity type arranged on the surface of the substrate 100, and the second epitaxial layer 120 can be a semiconductor material epitaxial layer arranged on the side of the first epitaxial layer 110 away from the substrate 100. The second epitaxial layer 120 comprises a plurality of doped regions, for example, a body region 121 of a second conductivity type. The trench gate structure 02 is a longitudinal trench gate, which is arranged extending from the surface of the second epitaxial layer 120 away from the substrate 100 to the inside of the first epitaxial layer 110. The body region 121 and the channel region 03 are located in the same layer, and for the cell structure 01 in the trench gate semiconductor power device provided by the embodiment of the present application, the body region 121 is arranged around the periphery of the contact region in the center of the cell structure 01, and the channel region 03 is arranged around the periphery of the body region 121, i.e., see Figure 2 , the cross-sectional structure along the A-A' direction through the center contact region shows that the body region 121 and part of the channel region 03 located only on the two sides of the body region 121 are included between two adjacent trench gate structures 02; and see Figure 3, along the B-B' direction through the entire channel region 03 section, its cross-sectional structure schematic diagram shows that the adjacent two trench gate structure 02 is all arranged as the body region 121 layer of the channel region 03. Exemplarily, the semiconductor power device of the first conductive type is N type, then the trench gate type semiconductor power device provided by the embodiment of the application can include N type heavily doped semiconductor material substrate, N type lightly doped semiconductor material first epitaxial layer 110, and second epitaxial layer 120 including P type doped body region 121 and N type heavily doped channel region 03;The conductive type of each region of P type semiconductor power device and N type semiconductor power device is opposite, which is not repeated here.

[0078] In the trench gate type semiconductor power device provided by the embodiment of the application, at least two vertexes of each cell structure 01, a strain passivation layer 130 is arranged.The strain passivation layer 130 is arranged by the second epitaxial layer 120 away from the inner surface of the substrate 100 to the first epitaxial layer 110, that is, the strain passivation layer 130 and the trench gate structure 02 are the same, which are longitudinal extension structures;And the depth of the strain passivation layer 130 is the same as the depth of the trench gate structure 02, so that the strain passivation layer 130 can be prepared by the trench etched to form the trench gate structure 02, which simplifies the preparation process of the strain passivation layer 130, and does not need to separately set the trench required for forming the strain passivation layer 130.

[0079] Figure 4 is a top view structure schematic diagram of a semiconductor power device provided by the related art, Figure 5 is Figure 4 is a cross-sectional structure schematic diagram along the C-C' direction in the above-mentioned Figure 6 is Figure 4 is a cross-sectional structure schematic diagram along the D-D' direction in the above-mentioned. Referring to Figures 4 to 6 The trench gate type semiconductor power device provided by the related art does not have a strain passivation layer at the vertex of each cell structure, that is, the trench gate structure 002 of the power device directly contacts the channel region 003.There is no internal stress in the trench gate structure 002 itself, which cannot introduce corresponding direction strain in the channel region 003, therefore, the carrier mobility of the power device cannot be improved, and the channel resistance cannot be reduced. In the embodiment of the application, referring to Figures 1 to 3The sidewall surface of the trench gate structure 02 outside at least two top corners of the cell structure 01 is covered by the formed strain passivation layer 130, which can be in contact with the channel region 03 in the cell structure 01. Since the strain passivation layer 130 itself has a certain internal stress, the direct contact between the strain passivation layer 130 and the channel region 03 can make the strain passivation layer 130 with internal stress produce deformation on the channel region 03, so as to introduce stress in the channel region 03 of the longitudinal trench gate semiconductor power device, so as to cause the semiconductor material in the channel region 03 to be strained by the stress, so that the channel region 03 introduces different strains to improve the mobility of the corresponding carriers. Exemplarily, Figure 1 and Figure 3 It is shown that the strain passivation layer 130 is arranged at two top corner positions of the cell structure 01 in a diagonal direction; for an N-type semiconductor power device, the strain passivation layer 130 introduces tensile strain to the channel region 03 from at least one side of the channel region 03, so as to improve the mobility of electron carriers; for a P-type semiconductor power device, the strain passivation layer 130 introduces compressive strain to the channel region 03 from at least one side of the channel region 03, so as to improve the mobility of hole carriers; thus, the channel resistance of the semiconductor power device can be effectively reduced, the relationship between the breakdown voltage and the on-resistance of the power device is further optimized, and the device performance is improved.

[0080] The semiconductor power device provided by the embodiment of the present application comprises a plurality of cell structures arranged in an array, and a trench gate structure is arranged around the edge of each cell structure, and the trench gate structure surrounds the channel region of each cell structure. The semiconductor power device comprises a substrate, a first epitaxial layer and a second epitaxial layer arranged in layers, wherein the second epitaxial layer comprises a body region and a channel region arranged around the periphery of the body region. The power device further comprises a strain passivation layer arranged at at least two top corner positions of the cell structure, the strain passivation layer extends from the surface of the second epitaxial layer to the inside of the first epitaxial layer and is arranged on the sidewall of the trench gate structure at the top corner position, and the strain passivation layer is in direct contact with the channel region. Since the strain passivation layer itself has a certain internal stress, the direct contact between the strain passivation layer and the channel region can introduce corresponding strain in the channel region through the deformation caused by the internal stress of the strain passivation layer, so as to improve the carrier mobility of the power device, effectively reduce the channel resistance, further optimize the relationship between the breakdown voltage and the on-resistance of the power device, and improve the device performance.

[0081] Based on the above-mentioned embodiment, further referring to Figure 1 and Figure 3 Optionally, the trench gate structure 02 comprises a gate oxide layer 021 and a gate electrode 022, and the gate oxide layer 021 is arranged around the sidewall and bottom of the gate electrode 022.

[0082] The width D of the strain passivation layer 130 is greater than the thickness d of the gate oxide layer 021 covering the sidewall of the gate 022.

[0083] Specifically, the trench gate structure 02 is composed of the gate oxide layer 021 arranged at the bottom and sidewall of the gate trench, and the gate 022 arranged on the surface of the gate oxide layer 021 and filling the gate trench, wherein the gate oxide layer 021 is used to insulate the gate 022 from the second epitaxial layer 120, and the gate oxide layer 021 covering the sidewall of the gate 022 has a certain thickness d. The strain passivation layer 130 arranged at at least two corner positions in the cell structure 01 has a corresponding width D, and the width D of the strain passivation layer 130 is greater than the thickness d of the gate oxide layer 021, so that part of the side surface of the strain passivation layer 130 can protrude out of the gate oxide layer 021 and directly contact the channel region 03. In this way, a certain stress can be applied to the channel region 03 through the part of the strain passivation layer 130 directly contacting the channel region 03, and the direction of the stress is in the channel region 03, i.e. from one trench gate structure 02 to the adjacent trench gate structure 02, so that strain can be introduced in at least one side of the channel region 03, the carrier mobility of the power device is improved, and thus the channel resistance of the device is reduced.

[0084] If the width D of the strain passivation layer 130 is set to be equal to the thickness d of the gate oxide layer 021, or the width D of the strain passivation layer 130 is set to be less than the thickness d of the gate oxide layer 021, only one side of the strain passivation layer 130 contacts the channel region 03, the stress applied to the channel region 03 is limited, and the direction of the stress is not in the channel region 03, so that the effect of introducing strain in the channel region 03 is not good, the carrier mobility cannot be effectively improved, and thus the channel resistance of the device cannot be effectively reduced.

[0085] On the basis of the above-mentioned embodiments, Figure 7 is another top view structure schematic diagram of a semiconductor power device provided by the embodiments, Figure 8 is Figure 7 is a cross-sectional structure schematic diagram along the direction of E-E'. Referring to Figure 2 、 Figure 7 and Figure 8 Optionally, the orthographic projection of the cell structure 01 on the substrate 100 is square;

[0086] Along the extension direction of the edge of the cell structure 01, the strain passivation layer 130 is arranged at both sides of each channel region 03 corresponding to the four corner positions.

[0087] Specifically, each of the cell structures 01 included in the semiconductor power device can be arranged in a square shape, and a plurality of cell structures 01 are arranged in an array and spaced apart from each other. The gate 022 is arranged between any two adjacent cell structures 01. On any one edge of the square-shaped cell structure 01, a strain passivation layer 130 is arranged at the corresponding top corner position on both sides of the channel region 03, that is Figure 7 The strain passivation layer 130 is arranged at the four top corner positions of the square-shaped cell structure 01, Figure 8 The strain passivation layer 130 is arranged on both sides of the channel region 03, and both strain passivation layers 130 are in direct contact with the side surface of the channel region 03, and Figure 7 The cross-sectional structure schematic diagram along the F-F' direction is exactly the same as that shown in Figure 2 Therefore, the strain passivation layer 130 is not described here. Compared with the strain passivation layer 130 arranged at the two top corner positions in the diagonal direction of the cell structure 01 in the above embodiment, the strain passivation layer 130 arranged on both sides of the channel region 03 of the four edges of the square-shaped cell structure 01 can introduce effective strain in the channel region 03, which can further improve the carrier mobility and effectively reduce the channel resistance of the device.

[0088] On the basis of the above embodiments, optionally, the first conductivity type is N-type, and the strain passivation layer includes a film layer with compressive stress prepared by a first preset process using an insulating material with internal stress; or the first conductivity type is P-type, and the strain passivation layer includes a film layer with tensile stress prepared by a second preset process using an insulating material with internal stress.

[0089] The first preset process includes at least one of a first radio frequency power, a first substrate temperature, a first reaction gas ratio, and a first deposition pressure; and the second preset process includes at least one of a second radio frequency power, a second substrate temperature, a second reaction gas ratio, and a second deposition pressure.

[0090] The first radio frequency power is greater than the second radio frequency power; the first substrate temperature is greater than the second substrate temperature; the first reaction gas ratio is less than the second reaction gas ratio; and the first deposition pressure is less than the second deposition pressure.

[0091] Specifically, for the case where the first conductivity type is N-type, that is, the N-type semiconductor power device, the strain passivation layer should be a film layer with internal compressive stress. Figure 9 is a stress direction schematic diagram of a semiconductor power device provided by an embodiment of the present application, which is described with reference to Figure 9The strain passivation layer 130 is set as a film layer with internal compressive stress, that is, the strain passivation layer 130 has inwardly shrinking stress, then the channel region 03 with the strain passivation layer 130 on both sides generates outwardly stretching tensile stress, so as to improve the electron mobility of the channel region 03, and further reduce the channel resistance of the device.

[0092] For the case that the first conductive type is P type, that is, the P type semiconductor power device, the strain passivation layer 130 should be a film layer with internal tensile stress. Figure 10 is another stress direction diagram in a semiconductor power device provided by the embodiment of the present application, referring to Figure 10 The strain passivation layer 130 is set as a film layer with internal tensile stress, that is, the strain passivation layer 130 has outwardly expanding stress, then the channel region 03 with the strain passivation layer 130 on both sides generates inwardly extruding compressive stress, so as to improve the hole mobility of the channel region 03, and further reduce the channel resistance of the device.

[0093] For the same insulating material used for preparing the strain passivation layer 130, the material film layer with different stress directions can be realized by adjusting the growth process conditions. Exemplarily, the strain passivation layer 130 includes Si3N4 or Al2O3. Among them, the strain passivation layer can be prepared by using the Plasma-Enhanced Chemical Vapor Deposition (PECVD) method. The factors affecting the stress direction of the material in the growth process mainly include the radio frequency power, the substrate temperature, the reaction gas ratio and the deposition pressure.

[0094] Exemplarily, the strain passivation layer 130 with compressive stress can be prepared by a first preset process, and the strain passivation layer 130 with tensile stress can be prepared by a second preset process. Among them, the difference between the first preset process and the second preset process is as follows: the first radio frequency power is greater than the second radio frequency power, that is, the high-energy ion bombardment is enhanced, which can make the atoms densely packed, and the low-energy ion bombardment is weakened, which can make the thin film loose and porous; the first substrate temperature is greater than the second substrate temperature, that is, the high temperature makes the atomic mobility high, which can form a dense and non-porous structure, and the low temperature makes the atomic mobility low, which forms an amorphous loose structure; the first reaction gas ratio is less than the second reaction gas ratio, and the reaction gas ratio is the ratio of SiH4 gas to NH3 gas, the smaller the reaction gas ratio, the more N-H bonds, which makes the volume expand, and the larger the reaction gas ratio, the less N-H bonds, which makes the dangling bond increase; the first deposition pressure is less than the second deposition pressure, and the lower deposition pressure can make the particle kinetic energy higher, which is beneficial to improve the film density, and the higher deposition pressure can make the deposition rate fast, which is beneficial to reduce the film density.

[0095] On the basis of the above-mentioned embodiments, referring to Figure 2 ,Figure 7 and Figure 8 Optionally, the second epitaxial layer 120 further comprises a source contact region 122 and an active region 123.

[0096] The source contact region 122 is of the second conductivity type, and the active region 123 is of the first conductivity type.

[0097] The source contact region 122 is disposed on the same layer as the active region 123 on the side of the body region 121 away from the first epitaxial layer 110, and the active region 123 is disposed around the edge of the source contact region 122.

[0098] Specifically, the source contact region 122 of the second conductivity type is disposed on the side surface of the body region 121 away from the first epitaxial layer 110, and the source contact region 122 corresponds to the central region of the cell structure 01. Still taking the N-type semiconductor power device as an example, the body region 121 is connected to the source potential through the source contact region 122, so that the potential of the body region 121 is not in a floating state. The active region 123 is disposed on the same layer as the source contact region 122 on the side surface of the body region 121 away from the first epitaxial layer 110, and the active region 123 is disposed around the periphery of the source contact region 122. Taking the N-type semiconductor power device as an example, the active region 123 is an N-type heavily doped region. The active region 123 is electrically connected to the source, and can generate working current flowing from the substrate to the active region 123 through the channel region 03 in the body region 121, thereby realizing normal working of the semiconductor power device.

[0099] Based on the above embodiments, further referring to Figure 2 , Figure 7 and Figure 8 Optionally, the semiconductor power device further comprises:

[0100] The source metal layer 140 and the insulating layer 150 are disposed on the same layer on the side of the second epitaxial layer 120 away from the first epitaxial layer 110, and the source metal layer 140 covers the source contact region 122 and part of the active region 123, and the insulating layer 150 is disposed around the edge of the source metal layer 140.

[0101] The drain metal layer 160 is disposed on the side of the substrate 100 away from the first epitaxial layer 110.

[0102] Specifically, in each cell structure 01, an insulating layer 150 is provided on the surface of the second epitaxial layer 120 away from the first epitaxial layer 110. An opening is provided on the insulating layer 150 at a position corresponding to the source contact region 122 in the cell structure 01, and the area of ​​the opening is slightly larger than the area of ​​the source contact region 122, thus exposing all of the source contact region 122 and part of the active region 123. A source metal layer 140 is provided in the opening, filling it completely. It is disposed on the same layer as the insulating layer 150 and covers the source contact region 122 and part of the active region 123. This allows the body region 121 to be electrically connected to the source metal layer 140 through the source contact region 122, giving the body region 121 the same source potential as the source metal layer 140. On the back side of the substrate 100, i.e. the side away from the first epitaxial layer 110, a drain metal layer 160 is provided to provide the voltage required for the operation of the semiconductor power device together with the source metal layer 140, so that the semiconductor power device can operate normally.

[0103] This invention also provides a method for fabricating a semiconductor power device. Figure 11 This is a schematic flowchart of a semiconductor power device fabrication method provided in an embodiment of the present invention. Figures 12 to 19 for Figure 11 Schematic diagrams of the cross-sectional structures corresponding to each step. See also... Figures 11 to 19 The method for fabricating this semiconductor power device specifically includes the following steps:

[0104] S110, Provide a substrate; the substrate is configured as a first conductivity type.

[0105] See Figure 12 For example, taking an N-type semiconductor power device as an example, the first conductivity type is N-type, and the substrate 100 can be an N-type heavily doped semiconductor material substrate.

[0106] S120. A first epitaxial layer is formed on one side surface of the substrate; wherein the first epitaxial layer is configured with a first conductivity type, a trench is provided around the edge of the first epitaxial layer, the trench extends inward from the surface of the first epitaxial layer away from the substrate, and a groove is provided at at least two apex positions corresponding to the trench.

[0107] Specifically, see Figure 13 and Figure 14 , Figure 13 The corresponding step S120 is shown. Figure 7 A schematic diagram of the cross-sectional structure along the E-E' direction. Figure 14 The corresponding step S120 is shown. Figure 7A cross-sectional view along the F-F' direction is shown in the diagram. A first epitaxial layer 110 is formed on one side surface of the substrate 100. An epitaxial growth process can be used to epitaxially grow the first epitaxial layer 110 on the surface of the substrate 100. Exemplarily, the first epitaxial layer 110 can be an N-type lightly doped semiconductor material epitaxial layer, and the doping concentration of the first epitaxial layer 110 can be determined by the breakdown voltage of the semiconductor power device, and is not limited here. At the center of the first epitaxial layer 110 between two adjacent cell structures, trenches T1 of a certain width are etched towards the direction of the adjacent cell structures, and the trenches T1 are shared by the adjacent cell structures. It should be noted that... Figure 13 and Figure 14 The diagram shown is a cross-sectional view of a cellular structure. Therefore, the edge of the first epitaxial layer 110 is etched to form one half of the trench T1. The trench T1 extends a certain depth from the surface of the first epitaxial layer 110 away from the substrate 100 into the interior of the first epitaxial layer 110. See also... Figure 13 At the apex of the cell structure, i.e., at the corner of the etched trench T1, a groove T2 of a certain width is etched again from the side of the first epitaxial layer 110 inwards to reserve space for forming a strain passivation layer; while Figure 14 Groove T2 is not included.

[0108] S130, A strain passivation layer is formed inside the groove.

[0109] Specifically, see Figure 15 It shows the corresponding step S130 Figure 7 A cross-sectional view along the E-E' direction is shown. A strain passivation layer 130 is formed inside the groove T2. Using chemical vapor deposition (CVD), a material with inherent internal stress is grown and deposited in the groove T2 to fill it completely, forming the strain passivation layer 130, such that the side surface of the strain passivation layer 130 is flush with the side surface of the first epitaxial layer 110. A cross-sectional view along the F-F' direction corresponding to this step is shown. Figure 14 The structures shown are the same, so they will not be repeated here.

[0110] S140. A trench gate structure is formed inside the trench.

[0111] Specifically, see Figure 16 and Figure 17 ,in, Figure 16 The corresponding step S140 is shown. Figure 7 A schematic diagram of the cross-sectional structure along the E-E' direction. Figure 17 The corresponding step S140 is shown. Figure 7A cross-sectional structure schematic diagram along the direction of F-F'. The trench gate structure 02 is formed inside the trench T1, so that the trench gate structure 02 fills the trench T1.

[0112] S150, forming a second epitaxial layer on a side surface of the first epitaxial layer away from the substrate; wherein the second epitaxial layer comprises a body region, the body region is set as a second conductive type, and the body region is a channel region around an edge of the trench gate structure; and a strain passivation layer covers a sidewall of the trench gate structure and contacts the channel region in the second epitaxial layer.

[0113] Specifically, referring to Figure 18 and Figure 19 , wherein, Figure 18 a cross-sectional structure schematic diagram corresponding to step S150 is shown. Figure 7 A cross-sectional structure schematic diagram along the direction of E-E' in step S130, Figure 19 a cross-sectional structure schematic diagram corresponding to step S150 is shown. Figure 7 A cross-sectional structure schematic diagram along the direction of F-F'. The second epitaxial layer 120 is formed on a side surface of the first epitaxial layer 110 away from the substrate 100 by ion implantation; wherein the second epitaxial layer 120 comprises a body region 121, the body region 121 is set as a second conductive type, and the body region 121 is a channel region 03 around an edge of the trench gate structure 02; and a strain passivation layer 130 covers a sidewall of the trench gate structure 02 and contacts the channel region 03 in the second epitaxial layer 120.

[0114] In the semiconductor power device preparation method provided by the embodiment of the application, a groove is formed by etching the side of the first epitaxial layer at each corner position of the etched trench, and a strain passivation layer is grown in the groove to fill the groove, so that the strain passivation layer can directly contact the channel region included in the body region of the second epitaxial layer formed by ion implantation through the side surface. In this way, the internal stress existing in the strain passivation layer itself can act on both sides of the channel region, so that the channel region generates strain in a corresponding direction under the action of the stress in a certain direction applied on both sides, and thus the carrier mobility can be improved, which is beneficial to reducing the channel resistance of the device.

[0115] On the basis of the above embodiment, Figure 20 is Figure 11 a specific flowchart of step S130 in the embodiment, Figure 21 and Figure 22 is Figure 20 a cross-sectional structure schematic diagram corresponding to each step in the embodiment. Referring to Figure 14 , Figure 15 Figures 20 to 22 Optionally, the step of forming the strain passivation layer in the groove in step S130 specifically comprises the following steps:

[0116] S131, form a strain material layer inside the trench; the strain material layer covers the side wall and bottom of the trench.

[0117] Specifically, referring to Figure 21 and Figure 22 , wherein, Figure 21 shows the corresponding Figure 7 in the cross-sectional structure diagram along the E-E' direction, Figure 22 shows the corresponding Figure 7 in the cross-sectional structure diagram along the F-F' direction. The strain material layer 131 is formed inside the trench T1; the strain material layer 131 covers the side wall and bottom of the trench T1. By growing and depositing a strain material layer 131 with a certain thickness on the bottom and side wall inside the trench T1 by CVD method, the strain material layer 131 can completely fill the recess T2 and cover the side wall of the trench T1 with a certain thickness. Referring to Figure 22 , the strain material layer 131 at the corresponding position on the edge of the cell structure is thinner; referring to Figure 21 , the strain material layer 131 at the corresponding position of the top corner of the cell structure is thicker.

[0118] S132, pattern and etch the strain material layer, remove the strain material layer at the bottom of the trench, and form a strain passivation layer that fills the recess.

[0119] Specifically, continuing to refer to Figure 15 and Figure 14 , the strain material layer 131 is patterned and etched, and the strain material layer 131 at the bottom of the trench T1 is removed, forming a strain passivation layer 130 that fills the recess T2. By depositing a strain material layer 131 with a certain thickness inside the trench T1, it is ensured that the recess T2 is filled, and then the strain material layer 131 outside the recess T2 is removed by patterning and etching process, only the strain material layer 131 located in the recess T2 is retained as the strain passivation layer 130, so that the strain passivation layer 130 can apply stress to the channel region in the body region and introduce strain.

[0120] On the basis of the above embodiments, Figure 23 is Figure 11 a specific flowchart of step S140 in Figure 24 and Figure 25 are respectively Figure 11 the corresponding cross-sectional structure diagram of each step in Figure 16 , Figure 17 , Figures 23 to 25 Optionally, the step S140 of forming a trench gate structure inside the trench specifically comprises the following steps:

[0121] S141, form a gate oxide layer on the side wall and bottom of the trench.

[0122] Specifically, see Figure 24 and Figure 25 ,in, Figure 24 The corresponding step S141 is shown. Figure 7 A schematic diagram of the cross-sectional structure along the E-E' direction. Figure 25 The corresponding step S141 is shown. Figure 7 A schematic cross-sectional view along the F-F' direction. The gate oxide layer 021 is formed on the sidewalls and bottom of trench T1 using a thermal growth process. See also... Figure 24 No gate oxide layer 021 is formed on the sidewall of the strain passivation layer 130 at the apex position; the gate oxide layer 021 is only formed at the bottom. (See also...) Figure 25 A gate oxide layer 021 is formed on both the sidewall and the bottom at the edge position, and the surface of the gate oxide layer 021 on the sidewall at the edge position is flush with the surface of the strain passivation layer 130.

[0123] S142. A gate is formed on the surface of the gate oxide layer.

[0124] Specifically, see [link to relevant documentation] Figure 16 and Figure 17 A gate 022 is formed on the surface of the gate oxide layer 021, such that the gate 022 fills the trench T1.

[0125] Based on the above embodiments, Figure 26 yes Figure 11 A detailed flowchart of step S150 is shown below. (See attached diagram.) Figure 18 , Figure 19 and Figure 26 Optionally, the formation of a second epitaxial layer on the surface of the first epitaxial layer away from the substrate in step S150 specifically includes the following steps:

[0126] S151. Ion implantation is performed from the surface of the first epitaxial layer away from the substrate into the interior to form a bulk region.

[0127] Specifically, see [link to relevant documentation] Figure 18 and Figure 19 Ion implantation is performed from the central region of the surface of the first epitaxial layer 110 away from the substrate 100 inward to form a body region 121. The periphery of the edge of the body region 121 is a channel region 03.

[0128] S152. Ion implantation is performed from the center region of the surface of the body region away from the substrate to form the source contact region; ion implantation is performed from the edge region of the surface of the body region away from the substrate to form the active region, so as to form the second epitaxial layer.

[0129] Specifically, see [link to relevant documentation] Figure 18 and Figure 19The source contact region 122 is formed by ion implantation from the center region of the surface of the second epitaxial layer 120 away from the substrate 100 to the inside; and the active region 123 is formed by ion implantation from the edge region of the surface of the second epitaxial layer 120 away from the substrate 100 to the inside, so as to form the second epitaxial layer 120.

[0130] Based on the above embodiments, the semiconductor power device manufacturing method further comprises the following steps:

[0131] The source metal layer and the insulating layer are formed on the side of the second epitaxial layer away from the first epitaxial layer; the source metal layer covers the source contact region and part of the active region, and the insulating layer is arranged around the edge of the source metal layer;

[0132] The drain metal layer is formed on the surface of the substrate away from the first epitaxial layer.

[0133] Specifically, an insulating material is deposited on the surface of the second epitaxial layer, and the center region is patterned and etched to form an opening, thereby forming the insulating layer. A metal material is deposited in the opening to form the source metal layer, and a metal material is deposited on the back surface of the substrate to form the drain metal layer.

[0134] The above specific embodiments do not constitute a limitation on the protection scope of the present application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor power device, characterized in that, It includes multiple cell structures arranged in an array; wherein, a trench gate structure is provided around the edge of each cell structure, and the trench gate structure surrounds the channel region; The semiconductor power device includes: The substrate is configured with the first conductivity type. The first epitaxial layer is configured to the first conductivity type and is located on one side surface of the substrate; A second epitaxial layer is disposed on the side of the first epitaxial layer away from the substrate. The second epitaxial layer includes a body region, which is configured with a second conductivity type. The periphery of the body region near the edge of the trench gate structure is configured as a channel region. The trench gate structure extends from the surface of the second epitaxial layer away from the substrate to the interior of the first epitaxial layer, and at least a portion of the channel region is disposed between two adjacent trench gate structures. A strain passivation layer is disposed at at least two vertices of the cell structure, covering the sidewalls of the trench gate structure, and the strain passivation layer is in contact with the channel region in the second epitaxial layer.

2. The semiconductor power device according to claim 1, characterized in that, The trench gate structure includes a gate oxide layer and a gate, wherein the gate oxide layer is disposed covering the sidewalls and bottom of the gate; The width of the strain passivation layer is greater than the thickness of the gate oxide layer that surrounds the gate sidewall.

3. The semiconductor power device according to claim 1, characterized in that, The orthographic projection of the cellular structure onto the substrate is square; Along the extension direction of the edge of the cell structure, the strain passivation layer is provided on both sides of each of the channel regions corresponding to the four vertex positions.

4. The semiconductor power device according to claim 1, characterized in that, The first conductivity type is N-type, and the strain passivation layer includes a film layer with compressive stress prepared by an insulating material with internal stress through a first preset process; Alternatively, the first conductivity type is P-type, and the strain passivation layer includes a tensile stress film layer prepared by a second preset process from an insulating material with internal stress. The first preset process includes at least one parameter selected from the following: first radio frequency power, first substrate temperature, first reactant gas ratio, and first deposition pressure; the second preset process includes at least one parameter selected from the following: second radio frequency power, second substrate temperature, second reactant gas ratio, and second deposition pressure. The first radio frequency power is greater than the second radio frequency power; The temperature of the first substrate is greater than the temperature of the second substrate; The proportion of the first reactant gas is less than the proportion of the second reactant gas; The first deposition pressure is less than the second deposition pressure.

5. The semiconductor power device according to claim 4, characterized in that, The strain passivation layer includes Si3N4 or Al2O3.

6. The semiconductor power device according to claim 1, characterized in that, The second epitaxial layer further includes a source contact region and an active region; The source contact region is configured with the second conductivity type, and the active region is configured with the first conductivity type; The source contact region and the active region are disposed on the same layer of the body region away from the first epitaxial layer, and the active region is disposed around the edge of the source contact region.

7. The semiconductor power device according to claim 6, characterized in that, Also includes: A source metal layer and an insulating layer are disposed in the same layer on the side of the second epitaxial layer away from the first epitaxial layer, and the source metal layer covers the source contact area and part of the active area, and the insulating layer is disposed around the edge of the source metal layer. A drain metal layer is disposed on the side of the substrate away from the first epitaxial layer.

8. A method for fabricating a semiconductor power device, characterized in that, include: A substrate is provided; the substrate is configured with a first conductivity type; A first epitaxial layer is formed on one side surface of the substrate; wherein the first epitaxial layer is configured with the first conductivity type, a trench is provided around the edge of the first epitaxial layer, the trench extends inward from the surface of the first epitaxial layer away from the substrate, and a groove is provided at at least two apex positions of the trench. A strain passivation layer is formed inside the groove; A trench gate structure is formed inside the trench; A second epitaxial layer is formed on the surface of the first epitaxial layer away from the substrate; wherein the second epitaxial layer includes a body region configured as a second conductivity type, and the periphery of the body region near the edge of the trench gate structure is a channel region; the strain passivation layer covers the sidewall of the trench gate structure, and the strain passivation layer is in contact with the channel region in the second epitaxial layer.

9. The method for fabricating a semiconductor power device according to claim 8, characterized in that, The process of forming a strain passivation layer inside the groove includes: A strain material layer is formed inside the trench; the strain material layer covers the sidewalls and bottom of the trench; The strain material layer is patterned and etched to remove the strain material layer located at the bottom of the trench, forming the strain passivation layer that fills the groove.

10. The method for fabricating a semiconductor power device according to claim 8, characterized in that, The formation of a trench gate structure inside the trench includes: A gate oxide layer is formed on the sidewalls and bottom of the trench; A gate is formed on the surface of the gate oxide layer; The step of forming a second epitaxial layer on the surface of the first epitaxial layer away from the substrate includes: Ion implantation is performed from the surface of the first epitaxial layer away from the substrate inward to form the bulk region; Ion implantation is performed from the central region of the surface of the body region away from the substrate inward to form a source contact region; ion implantation is performed from the edge region of the surface of the body region away from the substrate inward to form an active region, thereby forming the second epitaxial layer; The method for fabricating the semiconductor power device further includes: A source metal layer and an insulating layer are formed on the side of the second epitaxial layer away from the first epitaxial layer; the source metal layer covers the source contact area and part of the active area, and the insulating layer is disposed around the edge of the source metal layer; A drain metal layer is formed on the surface of the substrate away from the first epitaxial layer.

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