Semiconductor device

Abstract

Provided is a semiconductor device that improves control of dV / dt and reduces on-state loss. A transistor and a diode are formed on a common semiconductor substrate, and the semiconductor substrate has a transistor region and a diode region. The diode region has: a first semiconductor layer of an n type provided on a second main surface side of the semiconductor substrate; a second semiconductor layer of an n type provided on the first semiconductor layer; a third semiconductor layer of a p type provided on a first main surface side of the semiconductor substrate compared to the second semiconductor layer; a first main electrode that applies a first potential to the diode; a second main electrode that applies a second potential to the diode; and a dummy active trench gate provided so as to reach the second semiconductor layer from the first main surface of the semiconductor substrate. The dummy active trench gate has the third semiconductor layer, which is not applied with the first potential but is in a floating state, on at least one of both side surfaces, and a gate potential of the transistor is applied to the dummy active trench gate.

Description

Technical Field

[0001] This invention relates to semiconductor devices, and more particularly to semiconductor devices having trench gates. Background Technology

[0002] As a semiconductor device with a trench gate, an example typically includes the insulated gate bipolar transistor (IGBT).

[0003] The basic structure of an IGBT is as follows: a trench is formed in one main surface of a semiconductor substrate, and the inner surface of the trench is covered by a gate insulating film. Multiple trench gates have gate electrodes embedded in the trenches whose inner surfaces are covered by the gate insulating film.

[0004] In contrast, the IGBT disclosed in Patent Document 1 has a structure in which one or more dummy trench gates that do not function as gates are provided between adjacent trench gates. For example, in Patent Document 1... Figure 1 In this design, three dummy trench gates are arranged between adjacent trench gates. The central dummy trench gate is given a gate potential and becomes an active dummy trench gate, while the dummy trench gates on both sides become isolated dummy trench gates that are given emitter potentials.

[0005] These dumb trench gates are covered by a continuous interlayer insulating film, and the p-type base region between the dumb trench gates is not connected to the emitter potential but is in a floating state.

[0006] By employing this structure, with an active dumb trench gate imparted with a gate potential and floating p-type base regions on either side not imparted with emitter potentials, the gate-collector capacitance (feedback capacitance) Cgc between the gate and collector of the IGBT is increased. The reason for increasing the feedback capacitance (Cgc) is to reduce conduction losses under the condition that the drain voltage V varies with time t (dV / dt) remains constant, thereby increasing the gate capacitance ratio Cgc / Cge, which is defined by the capacitance ratio of the feedback capacitance (Cgc) to the gate-emitter capacitance Cge.

[0007] Patent Document 1: Japanese Patent No. 6253769

[0008] As described above, in existing semiconductor devices, since an active dumb trench gate is provided in one of the main surfaces of the semiconductor substrate, i.e. above the collector layer, the holes injected from the collector layer when the device is turned on cause the potential of the floating p-type base region to change. As a result, a displacement current flows through the active dumb trench gate, and the gate voltage is biased. Therefore, even if the gate resistance (Rg) is increased, dV / dt cannot be reduced, i.e., the gate resistance controllability of dV / dt is reduced. In the region where dV / dt is low, it may lead to an increase in conduction loss. Summary of the Invention

[0009] The present invention was proposed to solve the problems mentioned above, and its purpose is to provide a semiconductor device that improves the controllability of dV / dt and reduces conduction losses.

[0010] The semiconductor device of the present invention forms a transistor and a diode on a common semiconductor substrate, the semiconductor substrate having: a transistor region on which the transistor is formed; and a diode region on which the diode is formed, the diode region having: a first semiconductor layer of a first conductivity type disposed on a second main surface side of the semiconductor substrate; a second semiconductor layer of a first conductivity type disposed above the first semiconductor layer; a third semiconductor layer of a second conductivity type disposed on the first main surface side of the semiconductor substrate compared to the second semiconductor layer; a first main electrode that imparts a first potential to the diode; a second main electrode that imparts a second potential to the diode; and at least one dumb active trench gate configured to extend from the first main surface of the semiconductor substrate to the second semiconductor layer, the at least one dumb active trench gate having a third semiconductor layer that is not imparted the first potential but is in a floating state on at least one of its two sides, the at least one dumb active trench gate being imparted the gate potential of the transistor.

[0011] The effects of the invention

[0012] According to the semiconductor device of the present invention, in the diode region, a third semiconductor layer is provided on at least one of the two sides, which is not given a first potential but is in a floating state, and at least one dummy active trench gate is provided with the gate potential of the transistor. Therefore, a semiconductor device with improved controllability of the drain voltage V relative to time t, i.e., dV / dt, and reduced conduction loss can be obtained. Attached Figure Description

[0013] Figure 1 This is a top view of an RC-IGBT, or semiconductor device.

[0014] Figure 2 This is a top view of an RC-IGBT, or semiconductor device.

[0015] Figure 3 This is a partial top view of the IGBT region in an RC-IGBT.

[0016] Figure 4 This is a partial cross-sectional view of the IGBT region in an RC-IGBT.

[0017] Figure 5 This is a partial cross-sectional view of the IGBT region in an RC-IGBT.

[0018] Figure 6 This is a partial top view of the diode region in an RC-IGBT.

[0019] Figure 7 This is a partial cross-sectional view of the diode region in an RC-IGBT.

[0020] Figure 8 This is a partial cross-sectional view of the diode region in an RC-IGBT.

[0021] Figure 9 This is a cross-sectional view of the boundary between the IGBT region and the diode region of an RC-IGBT.

[0022] Figure 10 This is a cross-sectional view of the boundary between the IGBT region and the end region of an RC-IGBT.

[0023] Figure 11 This is a cross-sectional view of the boundary between the IGBT region and the end region of an RC-IGBT.

[0024] Figure 12 This is a cross-sectional view illustrating the manufacturing method of RC-IGBT.

[0025] Figure 13 This is a cross-sectional view illustrating the manufacturing method of RC-IGBT.

[0026] Figure 14 This is a cross-sectional view illustrating the manufacturing method of RC-IGBT.

[0027] Figure 15 This is a cross-sectional view illustrating the manufacturing method of RC-IGBT.

[0028] Figure 16 This is a cross-sectional view illustrating the manufacturing method of RC-IGBT.

[0029] Figure 17 This is a cross-sectional view illustrating the manufacturing method of RC-IGBT.

[0030] Figure 18 This is a cross-sectional view illustrating the manufacturing method of RC-IGBT.

[0031] Figure 19This is a cross-sectional view illustrating the manufacturing method of RC-IGBT.

[0032] Figure 20 This is a cross-sectional view illustrating the manufacturing method of RC-IGBT.

[0033] Figure 21 This is a cross-sectional view illustrating the manufacturing method of RC-IGBT.

[0034] Figure 22 This is a cross-sectional view illustrating the manufacturing method of RC-IGBT.

[0035] Figure 23 This is a partial cross-sectional view showing the structure of the RC-IGBT according to Embodiment 1.

[0036] Figure 24 This is a partial cross-sectional view showing the structure of a modified example of the RC-IGBT according to Embodiment 1.

[0037] Figure 25 This is a partial cross-sectional view showing the structure of the RC-IGBT involved in Embodiment 2.

[0038] Figure 26 This is a partial cross-sectional view showing the structure of a modified example 1 of the RC-IGBT involved in Embodiment 2.

[0039] Figure 27 This is a partial cross-sectional view showing the structure of a modified example 2 of the RC-IGBT involved in embodiment 2.

[0040] Figure 28 This is a partial cross-sectional view showing the structure of the RC-IGBT involved in Embodiment 3.

[0041] Figure 29 This is a partial cross-sectional view showing the structure of a modified example of the RC-IGBT according to Embodiment 3.

[0042] Figure 30 This is a partial cross-sectional view showing the structure of the RC-IGBT involved in Embodiment 4.

[0043] Figure 31 This is a top view of the semiconductor device involved in Embodiment 5.

[0044] Figure 32 This is a partial cross-sectional view of the diode region in the semiconductor device according to Embodiment 5.

[0045] Figure 33 This is a partial cross-sectional view of the IGBT region in the semiconductor device according to Embodiment 5.

[0046] Figure 34This is a partial top view of the diode region in the semiconductor device according to Embodiment 5.

[0047] Figure 35 This is a partial cross-sectional view of the diode region in the semiconductor device according to Embodiment 5.

[0048] Figure 36 This is a partial cross-sectional view of the diode region in the semiconductor device according to Embodiment 5. Detailed Implementation

[0049] <Foreword>

[0050] In the following description, n-type and p-type refer to the conductivity type of the semiconductor. In this invention, the first conductivity type is described as n-type and the second conductivity type as p-type, but it is also possible to describe the first conductivity type as p-type and the second conductivity type as n-type. Additionally, n... - Type n indicates a concentration of impurities lower than that of type n. + The p-type indicates a higher concentration of impurities than the n-type. Similarly, p... - p-type indicates a lower concentration of impurities than p-type. + The type indicates a higher concentration of impurities than the p-type.

[0051] Furthermore, the accompanying drawings are only schematic illustrations, and the dimensions and positions of the images shown in different drawings may not be accurately depicted and can be appropriately modified. Additionally, in the following description, the same structural elements are illustrated with the same reference numerals, and their names and functions are also identical. Therefore, detailed descriptions of them may sometimes be omitted.

[0052] In addition, in the following description, terms such as "upper", "lower", "side", "top" and "back" are sometimes used to indicate specific positions and directions. These terms are used for convenience only to facilitate the understanding of the implementation content and have nothing to do with the actual direction during implementation.

[0053] Before describing the implementation method, a reverse conducting IGBT (RC-IGBT) with an IGBT and a freewheeling diode (FWD) disposed on a common semiconductor substrate will be described below.

[0054] Figure 1 This is a top view of an RC-IGBT, or semiconductor device. Additionally, Figure 2 This is a top view showing other structures of RC-IGBT, i.e., semiconductor devices. Figure 1The semiconductor device 100 shown has IGBT regions 10 and diode regions 20 arranged in a strip-like pattern, which can be simply referred to as a "strip type". Figure 2 In the semiconductor device 101 shown, a plurality of diode regions 20 are arranged in the vertical and horizontal directions, and an IGBT region 10 is arranged around the diode regions 20, which can be simply referred to as "island type".

[0055] (1) Strip-type integral planar structure

[0056] exist Figure 1 In this semiconductor device 100, an IGBT region 10 and a diode region 20 are included within a single semiconductor device. The IGBT region 10 and the diode region 20 extend from one end of the semiconductor device 100 to the other end, and are alternately arranged in a strip shape in a direction orthogonal to the extending direction of the IGBT region 10 and the diode region 20. Figure 1 The diagram shows three IGBT regions 10 and two diode regions, arranged in a structure where all diode regions 20 are sandwiched between IGBT regions 10. However, the number of IGBT regions 10 and diode regions 20 is not limited to this. The number of IGBT regions 10 can be greater than or equal to three, or less than or equal to three, and the number of diode regions 20 can be greater than or equal to two, or less than or equal to two. Alternatively, it could also be... Figure 1 The structure can be configured such that the positions of the IGBT region 10 and the diode region 20 are interchanged, or the entire IGBT region 10 is sandwiched between the diode regions 20. Alternatively, the IGBT region 10 and the diode region 20 can be arranged one on each side, adjacent to each other.

[0057] like Figure 1As shown, a pad region 40 is provided adjacent to the IGBT region 10 on the lower side of the paper. The pad region 40 is a region where control pads 410 for controlling the semiconductor device 100 are provided. The IGBT region 10 and the diode region 20 together are referred to as a cell region. In order to maintain the withstand voltage of the semiconductor device 100, an end region 30 is provided around the region that combines the cell region and the pad region 40. Known withstand voltage maintenance structures can be appropriately and selectively provided in the end region 30. The withstand voltage maintenance structure may be, for example, a field-limiting ring (FLR) surrounding the cell region by a p-type end well layer of a p-type semiconductor and a volume-lowering ring (VLD) surrounding the cell region by a p-type well layer with a concentration gradient are provided on the surface side of the semiconductor device 100, i.e., the first main surface side. The number of annular p-type end well layers used in the FLR and the concentration distribution used in the VLD can be appropriately selected according to the withstand voltage design of the semiconductor device 100. Alternatively, a p-type terminal well layer can be provided over approximately the entire area of ​​the pad region 40, or IGBT units and diode units can be provided in the pad region 40.

[0058] The control pad 410 can be, for example, a current sensing pad 410a, a Kelvin emitter pad 410b, a gate pad 410c, or a temperature sensing diode pad 410d or 410e. The current sensing pad 410a is a control pad used to detect the current flowing in the cell region of the semiconductor device 100, and is electrically connected to a portion of the IGBT cells or diode cells in the cell region in such a way that a fraction to a few ten-thousandths of the total current flowing in the cell region flows through it when the current flows in the cell region of the semiconductor device 100.

[0059] Kelvin emitter pad 410b and gate pad 410c are control pads to which a gate drive voltage is applied for controlling the on / off state of the semiconductor device 100. Kelvin emitter pad 410b is electrically connected to the p-type base layer of the IGBT cell, and gate pad 410c is electrically connected to the gate trench electrode of the IGBT cell. Kelvin emitter pad 410b and the p-type base layer can also be connected via p... + The temperature sensing diode pads 410d and 410e are control pads electrically connected to the anode and cathode of the temperature sensing diode disposed in the semiconductor device 100. The temperature of the semiconductor device 100 is measured by measuring the voltage between the anode and cathode of the temperature sensing diode (not shown) disposed in the cell area.

[0060] (2) Overall planar structure of the island

[0061] exist Figure 2In this semiconductor device 101, there are IGBT regions 10 and diode regions 20 within a single semiconductor device. Multiple diode regions 20 are arranged longitudinally and laterally within the semiconductor device, and each diode region 20 is surrounded by the IGBT regions 10. That is, the multiple diode regions 20 are arranged in an island-like configuration within the IGBT regions 10. Figure 2 The diagram shows a structure in which the diode regions 20 are arranged in a matrix with 4 columns in the left-right direction and 2 rows in the top-bottom direction. However, the number and arrangement of the diode regions 20 are not limited to this. As long as one or more diode regions 20 are distributed within the IGBT region 10 and each diode region 20 is surrounded by the IGBT region 10, it is acceptable.

[0062] like Figure 2 As shown, a pad region 40 is provided adjacent to the IGBT region 10 on the lower side of the paper. The pad region 40 is a region where control pads 410 for controlling the semiconductor device 101 are provided. The IGBT region 10 and the diode region 20 together are referred to as a cell region. In order to maintain the withstand voltage of the semiconductor device 101, an end region 30 is provided around the region that combines the cell region and the pad region 40. Known withstand voltage maintenance structures can be appropriately and selectively provided in the end region 30. The withstand voltage maintenance structure can be, for example, a Field Limiting Ring (FLR) that surrounds the region that combines the cell region and the pad region 40 by a p-type end well layer of a p-type semiconductor and a Variation of Lateral Doping (VLD) that surrounds the cell region by a p-type well layer with a concentration gradient is provided on the surface side of the semiconductor device 101, i.e., the first main surface side. The number of annular p-type end well layers used in the FLR and the concentration distribution used in the VLD can be appropriately selected according to the withstand voltage design of the semiconductor device 101. Alternatively, a p-type terminal well layer can be provided over approximately the entire area of ​​the pad region 40, or IGBT units and diode units can be provided in the pad region 40.

[0063] The control pad 410 can be, for example, a current sensing pad 410a, a Kelvin emitter pad 410b, a gate pad 410c, or a temperature sensing diode pad 410d or 410e. The current sensing pad 410a is a control pad used to detect the current flowing in the cell region of the semiconductor device 101, and is electrically connected to a portion of the IGBT cells or diode cells in the cell region in such a way that a fraction to a few ten-thousandths of the total current flowing in the cell region flows through it when the current flows in the cell region of the semiconductor device 101.

[0064] Kelvin emitter pad 410b and gate pad 410c are control pads to which a gate drive voltage is applied for controlling the on / off state of the semiconductor device 101. Kelvin emitter pad 410b is connected to the p-type base layer and n-type base layer of the IGBT cell. + The source layer is electrically connected, and the gate pad 410c is electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 410b and the p-type base layer can also be connected via p... + The temperature sensing diode pads 410d and 410e are control pads electrically connected to the anode and cathode of the temperature sensing diode disposed in the semiconductor device 101. The temperature of the semiconductor device 101 is measured by measuring the voltage between the anode and cathode of the temperature sensing diode (not shown) disposed in the cell area.

[0065] (3) Typical structure of IGBT region 10

[0066] Figure 3 This is a partially enlarged top view showing the structure of the IGBT region in an RC-IGBT, i.e., a semiconductor device. Additionally, Figure 4 and Figure 5 This is a cross-sectional view showing the structure of the IGBT region of an RC-IGBT, i.e., a semiconductor device. Figure 3 Magnification Figure 1 The semiconductor device 100 shown or Figure 2 The region 82 enclosed by the dashed line in the semiconductor device 101 shown. Figure 4 yes Figure 3 The cross-sectional view of semiconductor device 100 or semiconductor device 101 shown at the direction of the arrow at the dashed line AA. Figure 5 yes Figure 3 A cross-sectional view of the semiconductor device 100 or semiconductor device 101 at the point indicated by the arrow at the dashed line BB.

[0067] like Figure 3 As shown, in the IGBT region 10, the active trench gate 11 and the dumb trench gate 12 are arranged in a strip shape. In the semiconductor device 100, the active trench gate 11 and the dumb trench gate 12 extend along the length direction of the IGBT region 10, and the length direction of the IGBT region 10 becomes the length direction of the active trench gate 11 and the dumb trench gate 12. On the other hand, in the semiconductor device 101, in the IGBT region 10, there is no particular distinction between the length direction and the width direction; the left-right direction on the paper can be defined as the length direction of the active trench gate 11 and the dumb trench gate 12, or the up-down direction on the paper can be defined as the length direction of the active trench gate 11 and the dumb trench gate 12.

[0068] The active trench gate 11 is constructed by providing a gate trench electrode 11a in a trench formed in a semiconductor substrate, separated by a gate trench insulating film 11b. The dumb trench gate 12 is constructed by providing a dumb trench electrode 12a in a trench formed in a semiconductor substrate, separated by a dumb trench insulating film 12b. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 410c. The dumb trench electrode 12a of the dumb trench gate 12 is electrically connected to the emitter electrode disposed on the first main surface of the semiconductor device 100 or semiconductor device 101.

[0069] n + The source layer 13 is configured to contact the gate trench insulating film 11b on both sides in the width direction of the active trench gate 11. + The source layer 13 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0 × 10⁻⁶. 17 / cm 3 ~1.0×10 20 / cm 3 n + The source layer 13 is along the extension direction of the active trench gate 11 and p + The contact layers 14 are alternately arranged. A p-type contact layer is also provided between two adjacent dumb trench gates 12. + Type contact layer 14. p + The p-type contact layer 14 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0 × 10⁻⁶. 15 / cm 3 ~1.0×10 20 / cm 3 .

[0070] like Figure 3 As shown, the IGBT region 10 of semiconductor device 100 or semiconductor device 101 has the following structure: three dumb trench gates 12 are arranged next to three side-by-side active trench gates 11, and three active trench gates 11 are arranged next to the three side-by-side dumb trench gates 12. As described above, the IGBT region 10 has a structure in which groups of active trench gates 11 and groups of dumb trench gates 12 are arranged alternately. Figure 3 In this configuration, a group of active trench gates 11 may contain three active trench gates 11, but any group containing one or more active trench gates is acceptable. Conversely, a group of dumb trench gates 12 may contain one or more dumb trench gates 12, or the number of dumb trench gates 12 may be zero. That is, all trenches in the IGBT region 10 may be designated as active trench gates 11.

[0071] Figure 4 It is semiconductor device 100 or semiconductor device 101 Figure 3 The cross-sectional view along the arrow at the dashed line AA is a cross-sectional view of the IGBT region 10. Semiconductor device 100 or semiconductor device 101 has a second semiconductor layer, i.e., n, formed of a semiconductor substrate. - Type 1 drift layer. - The n-type drift layer 1 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0 × 10⁻⁶. 12 / cm 3 ~1.0×10 15 / cm 3 Semiconductor substrates in Figure 4 The middle is from n + Type source layer 13 and p + The range from the p-type contact layer 14 to the p-type collector layer 16. Figure 4 n + Type source layer 13 and p + The upper end of the p-type contact layer 14 on the paper surface is referred to as the first main surface of the semiconductor substrate, and the lower end of the p-type collector layer 16 on the paper surface is referred to as the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the surface side of the semiconductor device 100, and the second main surface of the semiconductor substrate is the main surface on the back side of the semiconductor device 100. In the cell region, i.e., the IGBT region 10, the semiconductor device 100 has an n-type contact layer between the first main surface and the second main surface opposite to the first main surface. - Type 1 drift layer.

[0072] like Figure 4 As shown, in IGBT region 10, in n - The first principal surface of the drift layer 1 is provided with a concentration ratio of n-type impurities to n - The n-type carrier accumulation layer 2 has a high n-type drift layer 1. The n-type carrier accumulation layer 2 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0 × 10⁻⁶. 13 / cm 3 ~1.0×10 17 / cm 3 Furthermore, semiconductor device 100 or semiconductor device 101 may also omit the n-type carrier accumulation layer 2, while... Figure 4 The region of the n-type carrier accumulation layer 2 shown also has n - The structure of the n-type drift layer 1. By setting the n-type carrier accumulation layer 2, the current loss when the IGBT region 10 flows can be reduced. Alternatively, the n-type carrier accumulation layer 2 and n... - The drift layers 1 and 2 are collectively referred to as the drift layers.

[0073] The n-type carrier accumulation layer 2 is formed by introducing n-type impurities into the n-type carrier accumulation layer. -Ion implantation is performed on the semiconductor substrate of the n-type drift layer 1, followed by annealing to allow the implanted n-type impurities to migrate to the n-type drift layer. - Type drift layer 1 is formed by diffusion within the semiconductor substrate.

[0074] A p-type base layer 15 is provided on the first main surface side of the n-type carrier accumulation layer 2. The p-type base layer 15 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0 × 10⁻⁶. 12 / cm 3 ~1.0×10 19 / cm 3 The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11. An n-type base layer 15 is disposed on the first main surface side of the p-type base layer 15 in contact with the gate trench insulating film 11b of the active trench gate 11. + Type source layer 13, with p in the remaining region + Type contact layer 14. + Type source layer 13 and p + The p-type contact layer 14 constitutes the first main surface of the semiconductor substrate. Furthermore, p... + The contact layer 14 is a region where the concentration of p-type impurities is higher than that of the p-type base layer 15, where it is necessary to distinguish between p-type and p-type impurities. + In the case of p-type contact layer 14 and p-type base layer 15, they can be referred to separately, or p can be referred to as... + The p-type contact layer 14 and the p-type base layer 15 together are called the p-type base layer.

[0075] Furthermore, regarding semiconductor device 100 or semiconductor device 101, in n - The second main surface of the drift layer 1 is provided with a concentration ratio of n-type impurities to n - The n-type buffer layer 3 is a high-density n-type drift layer 1. The n-type buffer layer 3 is provided to suppress depletion layer breakdown extending from the p-type base layer 15 to the second main surface when the semiconductor device 100 is in an off state. The n-type buffer layer 3 can be, for example, implanted phosphorus (P) or protons (H). + It can be formed by injecting phosphorus (P) and protons (H). + This is formed by these two factors. The concentration of n-type impurities in n-type buffer layer 3 is 1.0 × 10⁻⁶. 12 / cm 3 ~1.0×10 18 / cm 3 .

[0076] Furthermore, semiconductor device 100 or semiconductor device 101 may also omit the n-type buffer layer 3, while... Figure 4 The area of ​​the n-type buffer layer 3 shown also has n... -The structure of type n drift layer 1. Alternatively, type n buffer layer 3 and type n... - The drift layers 1 and 2 are collectively referred to as the drift layers.

[0077] Semiconductor device 100 or semiconductor device 101 has a p-type collector layer 16 disposed on the second main surface side of the n-type buffer layer 3. That is, on the n-type buffer layer 3... - A p-type collector layer 16 is disposed between the p-type drift layer 1 and the second main surface. The p-type collector layer 16 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0 × 10⁻⁶. 16 / cm 3 ~1.0×10 20 / cm 3 The p-type collector layer 16 constitutes the second main surface of the semiconductor substrate. The p-type collector layer 16 is disposed not only in the IGBT region 10 but also in the terminal region 30, and the portion of the p-type collector layer 16 disposed in the terminal region 30 constitutes the p-type terminal collector layer 16a. Alternatively, a portion of the p-type collector layer 16 may be configured to extend from the IGBT region 10 into the diode region 20.

[0078] like Figure 4 As shown, in semiconductor device 100 or semiconductor device 101, a p-type base layer 15 is formed extending from the first main surface of the semiconductor substrate to the n-type base layer 15. - The trench of the drift layer 1. An active trench gate 11 is formed by providing a gate trench electrode 11a within the trench, separated by a gate trench insulating film 11b. The gate trench electrode 11a is separated from the n by the gate trench insulating film 11b. - The drift layer 1 is opposite to the type. Furthermore, a dumb trench gate 12 is formed by providing a dumb trench electrode 12a within the trench, separated by a dumb trench insulating film 12b. The dumb trench electrode 12a is separated from the n by the dumb trench insulating film 12b. - The drift layer 1 is opposite to the active trench gate 11. The gate trench insulating film 11b of the active trench gate 11 is opposite to the p-type base layer 15 and the n-type base layer 15. + The p-type source layer 13 is in contact. If a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 that is in contact with the gate trench insulating film 11b of the active trench gate 11.

[0079] like Figure 4 As shown, an interlayer insulating film 4 is disposed on the gate trench electrode 11a of the active trench gate 11. A barrier metal 5 is formed on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not disposed, and on the interlayer insulating film 4. The barrier metal 5 may be, for example, a conductor containing titanium (Ti), such as titanium nitride, or TiSi alloyed from titanium and silicon (Si). Figure 4 As shown, the blocking metal 5 and n +Type source layer 13, p + The contact layer 14 and the dummy trench electrode 12a make ohmic contact with n. + Type source layer 13, p + The contact layer 14 and the trench electrode 12a are electrically connected. An emitter electrode 6 is disposed on top of the barrier metal 5. The emitter electrode 6 can be formed, for example, of an aluminum alloy such as an aluminum-silicon alloy (Al-Si alloy), or it can be an electrode composed of multiple metal films on which a coating has been formed by chemical plating or electroplating on an electrode formed of an aluminum alloy. The coating formed by chemical plating or electroplating can be, for example, a nickel (Ni) coating. Furthermore, in cases where there are small areas, such as between adjacent interlayer insulating films 4, where the emitter electrode 6 cannot be well embedded, tungsten, which has better embedding properties than the emitter electrode 6, can be disposed in the small area, and the emitter electrode 6 can be disposed on top of the tungsten. Alternatively, the barrier metal 5 may not be provided, and the emitter electrode 6 can be disposed on top of the trench electrode 12a. + Type source layer 13, p + An emitter electrode 6 is disposed on the contact layer 14 and the dummy trench electrode 12a. Alternatively, an emitter electrode 6 may be disposed only on n. + A barrier metal 5 is disposed on top of an n-type semiconductor layer such as the source layer 13. The barrier metal 5 and the emitter electrode 6 can be combined and referred to as the emitter electrode. Furthermore, in... Figure 4 The diagram shows a scenario where the interlayer insulating film 4 is not formed on the dumb trench electrode 12a of the dumb trench gate 12, but the interlayer insulating film 4 can also be formed on the dumb trench electrode 12a of the dumb trench gate 12. When the interlayer insulating film 4 is formed on the dumb trench electrode 12a of the dumb trench gate 12, the emitter electrode 6 and the dumb trench electrode 12a can be electrically connected in other cross-sections.

[0080] A collector electrode 7 is disposed on the second main surface side of the p-type collector layer 16. The collector electrode 7 may also be made of aluminum alloy or a combination of aluminum alloy and a coating, similar to the emitter electrode 6. Alternatively, the collector electrode 7 may have a different structure than the emitter electrode 6. The collector electrode 7 makes an ohmic contact with the p-type collector layer 16 and is electrically connected to it.

[0081] Figure 5 It is semiconductor device 100 or semiconductor device 101 Figure 3 The cross-sectional view along the arrow at the dashed line BB is a cross-sectional view of IGBT region 10. Figure 4 The cross-sectional view at the point indicated by the arrow at the dashed line AA differs in the following ways: Figure 5 In the cross-section along the arrow direction at the dashed line BB, the n-type ground plane on the first main surface of the semiconductor substrate, which is in contact with the active trench gate 11, cannot be observed. + Type source layer 13. That is, as shown in Figure 13. Figure 3As shown, n + The source layer 13 is selectively disposed on the first main surface side of the p-type base layer. Furthermore, the p-type base layer referred to here means a p-type base layer 15 and a p-type base layer 16. + The p-type base layer is referred to as the p-type contact layer 14 together.

[0082] (4) Typical construction of diode region 20

[0083] Figure 6 This is a partially enlarged top view showing the structure of the diode region of an RC-IGBT, i.e., a semiconductor device. Additionally, Figure 7 and Figure 8 This is a cross-sectional view showing the structure of the diode region of an RC-IGBT, i.e., a semiconductor device. Figure 6 Enlarged display Figure 1 The region 83 enclosed by the dashed line in the semiconductor device 100 or semiconductor device 101 shown. Figure 7 yes Figure 6 A cross-sectional view of the semiconductor device 100 shown, with the arrow pointing in the direction of the dashed line CC. Figure 8 yes Figure 6 A cross-sectional view of the semiconductor device 100 shown, with the arrow pointing in the direction of the dashed line DD.

[0084] The diode trench gate 21 extends along the first main surface of the semiconductor device 100 or semiconductor device 101 from one end of the unit region, i.e., the diode region 20, to the opposite end. The diode trench gate 21 is constructed by providing a diode trench electrode 21a in a trench formed on the semiconductor substrate within the diode region 20, separated by a diode trench insulating film 21b. The diode trench electrode 21a is separated from the diode trench insulating film 21b by n... - The drift layer 1 is opposite to the type. A p-type drift layer is disposed between the gates 21 of two adjacent diode trenches. + The p-type contact layer 24 and the third semiconductor layer, namely the p-type anode layer 25. + The p-type contact layer 24 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, with a p-type impurity concentration of 1.0 × 10⁻⁶. 15 / cm 3 ~1.0×10 20 / cm 3 The p-type anode layer 25 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, with a p-type impurity concentration of 1.0 × 10⁻⁶. 12 / cm 3 ~1.0×10 19 / cm 3 p + The p-type contact layer 24 and the p-type anode layer 25 are alternately arranged along the length of the diode trench gate 21.

[0085] Figure 7 It is semiconductor device 100 or semiconductor device 101 Figure 6 The cross-sectional view at the point indicated by the arrow at the dashed line CC is a cross-sectional view of the diode region 20. The semiconductor device 100 or semiconductor device 101 also has an n-shaped structure made of a semiconductor substrate in the diode region 20, similar to the IGBT region 10. - Type drift layer 1. Diode region 20 n - n-type drift layer 1 and IGBT region 10 - The drift layer 1 is integrally formed continuously on the same semiconductor substrate. Figure 7 In the middle, the semiconductor substrate is from p + Type contact layer 24 to the first semiconductor layer, i.e., n + The range up to cathode layer 26. Figure 7 p + The upper end of the contact layer 24 on the paper is called the first main surface of the semiconductor substrate, and n + The lower end of the cathode layer 26 is called the second main surface of the semiconductor substrate. The first main surface of the diode region 20 and the first main surface of the IGBT region 10 are the same surface, and the second main surface of the diode region 20 and the second main surface of the IGBT region 10 are the same surface.

[0086] like Figure 7 As shown, in diode region 20, the same as in IGBT region 10, in n - An n-type carrier accumulation layer 2 is disposed on the first main surface side of the n-type drift layer 1. - An n-type buffer layer 3 is provided on the second main surface side of the n-type drift layer 1. The n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the diode region 20 have the same structure as the n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the IGBT region 10. Furthermore, it is not necessary to provide the n-type carrier accumulation layer 2 in both the IGBT region 10 and the diode region 20. Even if the n-type carrier accumulation layer 2 is provided in the IGBT region 10, it can be configured such that the n-type carrier accumulation layer 2 is not provided in the diode region 20. Additionally, similar to the IGBT region 10, the n-type carrier accumulation layer 2 can be... - The n-type drift layer 1, the n-type carrier accumulation layer 2, and the n-type buffer layer 3 are collectively referred to as the drift layer.

[0087] A p-type anode layer 25 is disposed on the first main surface side of the n-type carrier storage layer 2. The p-type anode layer 25 is disposed on the n-type carrier storage layer 2. -Between the p-type drift layer 1 and the first main surface. Alternatively, the concentration of p-type impurities in the p-type anode layer 25 can be set to the same concentration as the p-type base layer 15 of the IGBT region 10, thus forming both the p-type anode layer 25 and the p-type base layer 15 simultaneously. Alternatively, the concentration of p-type impurities in the p-type anode layer 25 can be set to be lower than the concentration of p-type impurities in the p-type base layer 15 of the IGBT region 10, thereby reducing the amount of holes injected into the diode region 20 during diode operation. By reducing the amount of holes injected during diode operation, the recovery loss during diode operation can be reduced.

[0088] A p-type anode layer 25 is provided on the first main surface side. + Type contact layer 24. p + The concentration of p-type impurities in the contact layer 24 can be set to be the same as that in the IGBT region 10. + The concentration of p-type impurities in the contact layer 14 can be the same, or different. + The contact layer 24 forms the first main surface of the semiconductor substrate. Furthermore, p... + The contact layer 24 is a region where the concentration of p-type impurities is higher than that of the p-type anode layer 25, where it is necessary to distinguish between p-type and p-type impurities. + In the case of p-type contact layer 24 and p-type anode layer 25, they can be referred to separately, or p can be referred to as... + The p-type contact layer 24 and the p-type anode layer 25 together are called the p-type anode layer.

[0089] In diode region 20, an n-type buffer layer 3 is provided on the second main surface side. + Type 26 cathode layer. + Type 26 cathode layer is disposed in n - Between drift layer 1 and the second principal surface. + The cathode layer 26 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, with an n-type impurity concentration of 1.0 × 10⁻⁶. 16 / cm 3 ~1.0×10 21 / cm 3 .like Figure 2 As shown, n + The cathode layer 26 is disposed in part or all of the diode region 20. + The p-type cathode layer 26 constitutes the second main surface of the semiconductor substrate. Furthermore, although not shown, p-type impurities can be selectively implanted into the n-type cathode layer formed as described above. + The region of the type cathode layer 26 forms an n + A portion of the region of the cathode layer 26 becomes a p-type semiconductor and is set as a p-type semiconductor. + Type-n cathode layer. n layers are thus alternately arranged along the second main surface of the semiconductor substrate. +Type Cathode Layer and p + A diode with a type-shaped cathode layer is called an RFC (Relaxed Field of Cathode) diode.

[0090] like Figure 7 As shown, in the diode region 20 of semiconductor device 100 or semiconductor device 101, a p-type anode layer 25 is formed that extends from the first main surface of the semiconductor substrate to the n-type anode layer 25. - The trench of the drift layer 1. A diode trench electrode 21a is formed by providing a diode trench electrode 21a within the trench of the diode region 20, separated by a diode trench insulating film 21b. The diode trench electrode 21a is separated from the diode trench insulating film 21b by the n... - Type drift layer 1 relative.

[0091] like Figure 7 As shown, in the diode trench electrode 21a and p + A barrier metal 5 is disposed above the contact layer 24. The barrier metal 5 is connected to the diode trench electrode 21a and p. + The contact layer 24 forms an ohmic contact with the diode trench electrode and p-type contact layer 24. + The contact layer 24 is electrically connected. The barrier metal 5 can have the same structure as the barrier metal 5 in the IGBT region 10. The emitter electrode 6 is disposed on the barrier metal 5. The emitter electrode 6 disposed in the diode region 20 is continuously formed with the emitter electrode 6 disposed in the IGBT region 10. Alternatively, similar to the case of the IGBT region 10, the barrier metal 5 can be omitted, and the diode trench electrode 21a and p can be made to... + The contact layer 24 makes an ohmic contact with the emitter electrode 6. Furthermore, in... Figure 7 The diagram shows a configuration where the interlayer insulating film 4 is not formed on the diode trench electrode 21a of the diode trench gate 21, but the interlayer insulating film 4 can also be formed on the diode trench electrode 21a of the diode trench gate 21. When the interlayer insulating film 4 is formed on the diode trench electrode 21a of the diode trench gate 21, the emitter electrode 6 and the diode trench electrode 21a can be electrically connected in other cross-sections.

[0092] In n + A collector electrode 7 is disposed on the second main surface side of the cathode layer 26. Similar to the emitter electrode 6, the collector electrode 7 of the diode region 20 is continuously formed with the collector electrode 7 disposed in the IGBT region 10. The collector electrode 7 and n + The cathode layer 26 makes an ohmic contact with n. + The cathode layer 26 is electrically connected and also functions as a cathode electrode.

[0093] Figure 8It is semiconductor device 100 or semiconductor device 101 Figure 6 The cross-sectional view at the dashed line DD, pointing in the direction of the arrow, is the cross-sectional view of diode region 20 pointing in the direction of the arrow. Figure 7 The difference in the cross-sectional view shown by the arrow at the dashed line CC is that there is no p-type anode layer 25 between the p-type anode layer 25 and the barrier metal 5. + The p-type contact layer 24 and the p-type anode layer 25 constitute the first main surface of the semiconductor substrate. That is, Figure 7 p shown + The p-type contact layer 24 is selectively disposed on the first main surface side of the p-type anode layer 25.

[0094] (5) Boundary region between IGBT region 10 and diode region 20

[0095] Figure 9 It is a cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of an RC-IGBT, i.e., a semiconductor device. Figure 9 yes Figure 1 A cross-sectional view of the semiconductor device 100 or semiconductor device 101 at the direction of the arrow at the dashed line GG.

[0096] like Figure 9 As shown, the p-type collector layer 16 disposed on the second main surface side of the IGBT region 10 is configured to extend a distance U1 from the boundary between the IGBT region 10 and the diode region 20 toward the diode region 20. In this way, by configuring the p-type collector layer 16 to extend into the diode region 20, the n-type collector layer of the diode region 20 can be increased. + The distance between the cathode layer 26 and the active trench gate 11 allows current to flow from the channel formed adjacent to the active trench gate 11 in the IGBT region 10 to the n-type cathode layer 26, even when a gate drive voltage is applied to the gate trench electrode 11a during freewheeling diode operation. + The cathode layer 26 is used for suppression. The distance U1 can be, for example, 100 μm. In addition, depending on the application of the RC-IGBT, i.e., semiconductor device 100 or semiconductor device 101, the distance U1 can also be zero or less than 100 μm.

[0097] (6) Typical structure of the terminal region 30

[0098] Figure 10 and Figure 11 This is a cross-sectional view showing the structure of the end region of an RC-IGBT, i.e., a semiconductor device. Figure 10 yes Figure 1 or Figure 2 The cross-sectional view along the arrow at the dashed line EE is a cross-sectional view from IGBT region 10 to end region 30. Additionally, Figure 11 yes Figure 1The cross-sectional view with the arrow pointing to the dashed line FF is a cross-sectional view from diode region 20 to end region 30.

[0099] like Figure 10 and Figure 11 As shown, the end region 30 of the semiconductor device 100 has n regions between the first main surface and the second main surface of the semiconductor substrate. - Type 1 drift layer. The first and second main surfaces of the end region 30 are the same as the first and second main surfaces of the IGBT region 10 and the diode region 20, respectively. Additionally, the n-type drift layer of the end region 30... - Type-type drift layer 1 is respectively connected to the n-type IGBT region 10 and diode region 20. - The drift layers 1 are of the same structure and are formed continuously as a single unit.

[0100] In n - The first main surface side of the drift layer 1, i.e., the first main surface of the semiconductor substrate and n - A p-type end-well layer 31 is disposed between the p-type drift layers 1. The p-type end-well layer 31 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0 × 10⁻⁶. 14 / cm 3 ~1.0×10 19 / cm 3 The p-type end-well layer 31 is configured to surround the cell region containing the IGBT region 10 and the diode region 20. The p-type end-well layers 31 are configured in multiple rings, and the number of p-type end-well layers 31 is appropriately selected based on the voltage withstand design of the semiconductor device 100 or semiconductor device 101. Additionally, n-type end-well layers 31 are provided at a further outer edge of the p-type end-well layer 31. + Type 32, n channel truss layer + The p-type channel cut-off layer 32 surrounds the p-type end trap layer 31.

[0101] In n - A p-type terminal collector layer 16a is provided between the p-type drift layer 1 and the second main surface of the semiconductor substrate. The p-type terminal collector layer 16a is integrally formed continuously with the p-type collector layer 16 provided in the cell region. Therefore, it can also be referred to as the p-type collector layer 16, including the p-type terminal collector layer 16a. Furthermore, in cases such as... Figure 1 In the structure of the semiconductor device 100 shown, where the diode region 20 and the terminal region 30 are arranged adjacently, such as... Figure 11 As shown, the p-type terminal collector layer 16a is configured to extend a distance U2 from the end of the diode region 20 towards the diode region 20. In this way, by configuring the p-type terminal collector layer 16a to extend into the diode region 20, the n-value of the diode region 20 can be increased. +The distance between the p-type cathode layer 26 and the p-type end-well layer 31 can suppress the p-type end-well layer 31 from operating as the anode of the diode. The distance U2 can be, for example, 100 μm.

[0102] A collector electrode 7 is provided on the second main surface of the semiconductor substrate. The collector electrode 7 is integrally formed continuously from the cell region including the IGBT region 10 and the diode region 20 to the end region 30. On the other hand, an emitter electrode 6 continuous with the cell region and an end electrode 6a separate from the emitter electrode 6 are provided on the first main surface of the semiconductor substrate in the end region 30.

[0103] Emitter electrode 6 and terminal electrode 6a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 may be, for example, sinSiN (semi-insulating silicon nitride). Terminal electrode 6a is connected to the p-type terminal well layer 31 and n-type terminal well layer 32. + The channel cut-off layer 32 is electrically connected via contact holes formed by the interlayer insulating film 4 disposed on the first main surface of the end region 30. Additionally, an end protective film 34 is provided in the end region 30, covering the emitter electrode 6, the end electrode 6a, and the semi-insulating film 33. The end protective film 34 may be formed of polyimide, for example.

[0104] (7) Common manufacturing methods of RC-IGBT

[0105] Figures 12-22 This diagram illustrates the manufacturing process of RC-IGBT, or semiconductor devices. Figures 12-19 This diagram illustrates the processes involved in forming the surface side of semiconductor device 100 or semiconductor device 101. Figures 20-22 This is a diagram showing the process of forming the back side of semiconductor device 100 or semiconductor device 101.

[0106] First, such as Figure 12 The preparation shown constitutes n - The semiconductor substrate is a type-drift layer 1. The semiconductor substrate can be, for example, an FZ wafer fabricated by the FZ (Floating Zone) method or an MCZ wafer fabricated by the MCZ (Magnetic Field Applied Czochralski) method, or an n-type wafer containing n-type impurities. The concentration of n-type impurities in the semiconductor substrate is appropriately selected based on the breakdown voltage of the semiconductor device being manufactured. For example, for a semiconductor device with a breakdown voltage of 1200V, the concentration of n-type impurities is adjusted so that the n-type impurities constituting the semiconductor substrate... - The resistivity of drift layer 1 is approximately 40–120 Ω·cm. For example... Figure 12As shown, in the process of preparing a semiconductor substrate, the entire semiconductor substrate is n. - The semiconductor device 100 or semiconductor device 101 is manufactured by implanting p-type or n-type impurity ions from the first main surface side or the second main surface side of such a semiconductor substrate, and then allowing them to diffuse within the semiconductor substrate through heat treatment or the like, thereby forming a p-type or n-type semiconductor layer.

[0107] like Figure 12 As shown, n constitutes - The semiconductor substrate of the drift layer 1 has regions that become IGBT region 10 and diode region 20. Additionally, although not shown, there is a region called end region 30 surrounding the regions that become IGBT region 10 and diode region 20. Hereinafter, a method for manufacturing the structure of IGBT region 10 and diode region 20 of semiconductor device 100 or semiconductor device 101 will be mainly described, but the end region 30 of semiconductor device 100 or semiconductor device 101 can be fabricated using known manufacturing methods. For example, when an FLR with a p-type end well layer 31 is formed in the end region 30 as a voltage withstand holding structure, it can be formed by implanting p-type impurity ions before processing the IGBT region 10 and diode region 20 of semiconductor device 100 or semiconductor device 101, or by simultaneously implanting p-type impurity ions when ion implanting p-type impurities into the IGBT region 10 or diode region 20 of semiconductor device 100.

[0108] Next, as Figure 13 As shown, an n-type carrier accumulation layer 2 is formed by implanting n-type impurities such as phosphorus (P) from the first main surface of the semiconductor substrate. Additionally, a p-type base layer 15 and a p-type anode layer 25 are formed by implanting p-type impurities such as boron (B) from the first main surface of the semiconductor substrate. The n-type carrier accumulation layer 2, the p-type base layer 15, and the p-type anode layer 25 are formed by diffusing impurity ions through heat treatment after implanting them into the semiconductor substrate. Since the n-type and p-type impurities are selectively formed on the first main surface of the semiconductor substrate after ion implantation with a mask, the n-type and p-type impurities are formed selectively on the first main surface of the semiconductor substrate. The n-type carrier accumulation layer 2, the p-type base layer 15, and the p-type anode layer 25 are formed in the IGBT region 10 and the diode region 20, and are connected to the p-type end-well layer 31 in the end region 30. In addition, masking is a process in which a photoresist is applied to a semiconductor substrate, and an opening is formed in a specified area of ​​the photoresist using photolithography. In order to perform ion implantation or etching on a specified area of ​​the semiconductor substrate through the opening, a mask is formed on the semiconductor substrate.

[0109] The p-type base layer 15 and the p-type anode layer 25 can also be formed by simultaneously implanting p-type impurities with ions. In this case, the p-type base layer 15 and the p-type anode layer 25 have the same depth and p-type impurity concentration and are identical in structure. Alternatively, p-type impurities can be implanted into the p-type base layer 15 and the p-type anode layer 25 separately using a mask process, thereby making the depth and p-type impurity concentration of the p-type base layer 15 and the p-type anode layer 25 different.

[0110] Alternatively, the p-type end-well layer 31 formed in other cross-sections can also be formed by simultaneously implanting p-type impurities into the p-type anode layer 25. In this case, the depth and p-type impurity concentration of the p-type end-well layer 31 and the p-type anode layer 25 can be set to be the same, and they can be set to have the same structure. Alternatively, the p-type end-well layer 31 and the p-type anode layer 25 can be formed by simultaneously implanting p-type impurities, and the p-type impurity concentrations of the p-type end-well layer 31 and the p-type anode layer 25 can be set to be different. In this case, one or both masks can be set as a grid-like mask, and the aperture ratio can be changed.

[0111] Alternatively, p-type impurities can be ion implanted into the p-type end-well layer 31 and the p-type anode layer 25 separately using masking, thereby resulting in different depths and p-type impurity concentrations in the p-type end-well layer 31 and the p-type anode layer 25. P-type impurities can also be ion implanted simultaneously to form the p-type end-well layer 31, the p-type base layer 15, and the p-type anode layer 25.

[0112] Next, as Figure 14 As shown, n-type impurities are selectively implanted into the first main surface of the p-type base layer 15 of the IGBT region 10 through masking to form n-type impurities. + The source layer 13 is an n-type impurity. The implanted n-type impurity can be, for example, arsenic (As) or phosphorus (P). Additionally, through masking, p-type impurities are selectively implanted into the first main surface side of the p-type base layer 15 of the IGBT region 10 to form a p-type base layer. + The p-type contact layer 14 selectively implants p-type impurities into the first main surface side of the p-type anode layer 25 of the diode region 20 to form a p-type contact layer 14. + Type contact layer 24. The implanted p-type impurities can be, for example, boron (B) or aluminum (Al).

[0113] Next, as Figure 15 As shown, a structure is formed that extends from the first main surface of the semiconductor substrate through the p-type base layer 15 and the p-type anode layer 25 to reach the n-type anode layer. - The trench 8 of the drift layer 1. In the IGBT region 10, it penetrates n + The sidewalls of the trench 8 in the source electrode layer 13 constitute n +A portion of the source layer 13. The trench 8 can also be formed by depositing an oxide film such as SiO2 on a semiconductor substrate, then creating openings in the oxide film at the portion forming the trench 8 using a mask, and using the oxide film with the openings as a mask to etch the semiconductor substrate. Figure 15 In this design, trenches 8 are formed in both the IGBT region 10 and the diode region 20 with the same spacing, but the spacing of the trenches 8 can also be different in the IGBT region 10 and the diode region 20. The pattern of the trench spacing when viewed from above can be appropriately changed according to the mask pattern of the masking process.

[0114] Next, as Figure 16 As shown, an oxide film 9 is formed on the inner wall of the trench 8 and the first main surface of the semiconductor substrate by heating the semiconductor substrate in an oxygen-containing environment. Among the oxide films 9 formed on the inner wall of the trench 8, the oxide films 9 formed in the trench 8 of the IGBT region 10 are the gate trench insulating film 11b of the active trench gate 11 and the dumb trench insulating film 12b of the dumb trench gate 12. Additionally, the oxide film 9 formed in the trench 8 of the diode region 20 is the diode trench insulating film 21b. The oxide film 9 formed on the first main surface of the semiconductor substrate will be removed in a subsequent process.

[0115] Next, as Figure 17 As shown, in the trench 8 with an oxide film 9 formed on the inner wall, polysilicon doped with n-type or p-type impurities is deposited by CVD (chemical vapor deposition) and other methods to form a gate trench electrode 11a, a dumb trench electrode 12a and a diode trench electrode 21a.

[0116] Next, as Figure 18 As shown, after forming an interlayer insulating film 4 on the gate trench electrode 11a of the active trench gate 11 in the IGBT region 10, the oxide film 9 formed on the first main surface of the semiconductor substrate is removed. The interlayer insulating film 4 can be, for example, SiO2. Then, contact holes are formed on the deposited interlayer insulating film 4 through a masking process. The contact holes are formed on n + Above the source electrode layer 13, p + Above the contact layer 14, p + Above the contact layer 24, above the dumb trench electrode 12a, and above the diode trench electrode 21a.

[0117] Next, as Figure 19 As shown, a barrier metal 5 is formed on the first main surface of the semiconductor substrate and on the interlayer insulating film 4, and an emitter electrode 6 is further formed on the barrier metal 5. The barrier metal 5 is formed by forming a titanium nitride film using PVD (physical vapor deposition) or CVD.

[0118] For example, an aluminum-silicon alloy (Al-Si alloy) can be deposited onto the barrier metal 5 by PVD, such as sputtering or evaporation, to form the emitter electrode 6. Alternatively, a nickel alloy (Ni alloy) can be further formed on the formed aluminum-silicon alloy by chemical plating or electroplating to serve as the emitter electrode 6. If the emitter electrode 6 is formed by plating, a thick metal film can be easily formed as the emitter electrode 6, thereby increasing the heat capacity of the emitter electrode 6 and improving its heat resistance. Furthermore, if the emitter electrode 6 made of aluminum-silicon alloy is formed by PVD, and a nickel alloy is further formed by plating, the plating process for forming the nickel alloy can be performed after processing the second main surface side of the semiconductor substrate.

[0119] Next, as Figure 20 As shown, the second main surface of the semiconductor substrate is ground to thin the semiconductor substrate to a predetermined thickness. The thickness of the ground semiconductor substrate can be, for example, 80 μm to 200 μm.

[0120] Next, as Figure 21 As shown, an n-type buffer layer 3 is formed by implanting an n-type impurity from the second main surface of the semiconductor substrate. Furthermore, a p-type collector layer 16 is formed by implanting a p-type impurity from the second main surface of the semiconductor substrate. The n-type buffer layer 3 can be formed in the IGBT region 10, the diode region 20, and the terminal region 30, or it can be formed only in the IGBT region 10 or the diode region 20.

[0121] The n-type buffer layer 3 can be formed, for example, by implanting phosphorus (P) ions. Alternatively, it can be formed by implanting protons (H) ions. + It can be formed by implanting both protons and phosphorus. Protons can be implanted to a deeper location from the second main surface of the semiconductor substrate with relatively low acceleration energy. In addition, the implantation depth of protons can be easily changed by altering the acceleration energy. Therefore, if multiple implantations are performed while forming the n-type buffer layer 3 using protons, by varying the acceleration energy, a wider n-type buffer layer 3 in the thickness direction of the semiconductor substrate can be formed compared to formation using phosphorus.

[0122] Furthermore, compared to protons, phosphorus can improve the activation rate as an n-type impurity. Therefore, even in semiconductor substrates thinned by forming an n-type buffer layer 3 using phosphorus, depletion layer breakdown can be suppressed more reliably. To further thin the semiconductor substrate, it is preferable to form the n-type buffer layer 3 by implanting both protons and phosphorus. In this case, protons are implanted to a deeper location from the second main surface compared to phosphorus.

[0123] The p-type collector layer 16 can be formed, for example, by implanting boron (B). The p-type collector layer 16 is also formed in the end region 30, and the p-type collector layer 16 in the end region 30 is called the p-type end collector layer 16a. After ion implantation from the second main surface of the semiconductor substrate, laser annealing is performed by irradiating the second main surface with a laser, thereby activating the implanted boron and forming the p-type collector layer 16. At this time, the phosphorus used to implant from the second main surface of the semiconductor substrate to a relatively shallow position in the n-type buffer layer 3 is also activated simultaneously. On the other hand, since protons are activated at a relatively low annealing temperature of 350°C to 500°C, care must be taken to prevent the entire semiconductor substrate from reaching a temperature higher than 350°C to 500°C, except for the process of activating protons after implantation. Since laser annealing can only raise the temperature near the second main surface of the semiconductor substrate, it can be used to activate both n-type and p-type impurities after proton implantation.

[0124] Next, as Figure 22 As shown, n is formed in diode region 20. + Type 26 cathode layer. + The cathode layer 26 can be formed, for example, by implanting phosphorus (P). Figure 22 As shown, with p-type collector layer 16 and n + The boundary of the cathode layer 26 is located at a distance U1 from the boundary between the IGBT region 10 and the diode region 20 towards the diode region 20 side, and phosphorus is selectively implanted from the second main surface side through a mask process. This is used to form n + The amount of n-type impurities implanted in the p-type cathode layer 26 is greater than the amount of p-type impurities implanted to form the p-type collector layer 16. Figure 22 The diagram shows the p-type collector layer 16 and n-type collector layer starting from the second main surface. + The depth of the cathode layer 26 is the same, but n + The depth of the n-type cathode layer 26 is greater than or equal to the depth of the p-type collector layer 16. This is due to the formation of the n-type cathode layer 26. + The region of the p-type cathode layer 26 needs to be implanted with n-type impurities to become an n-type semiconductor, thus forming an n-type semiconductor. + The concentration of p-type impurities injected into the entire region of the cathode layer 26 is set to be higher than the concentration of n-type impurities.

[0125] Next, by forming a collector electrode 7 on the second main surface of the semiconductor substrate, it is possible to obtain... Figure 9The cross-sectional structure is shown. The collector electrode 7 is formed over the entire surface of the IGBT region 10, diode region 20, and terminal region 30 on the second main surface. Alternatively, the collector electrode 7 can be formed over the entire surface of the second main surface of the semiconductor substrate, i.e., the n-type wafer. The collector electrode 7 can be formed by PVD deposition of aluminum-silicon alloy (Al-Si alloy) or titanium (Ti), such as by sputtering or evaporation, or by stacking multiple metals such as aluminum-silicon alloy, titanium, nickel, or gold. Furthermore, a metal film can be further formed on the metal film formed by PVD through chemical plating or electroplating to form the collector electrode 7.

[0126] The semiconductor device 100 or semiconductor device 101 is manufactured through the processes described above. As for the semiconductor device 100 or semiconductor device 101, since multiple semiconductor devices 100 or semiconductor devices 101 are manufactured in a matrix on a single n-type wafer, they are divided into individual semiconductor devices 100 or semiconductor devices 101 by laser cutting or blade cutting, thereby completing the semiconductor device 100 or semiconductor device 101.

[0127] <Implementation Method 1>

[0128] <Structure>

[0129] Figure 23 This is a partial cross-sectional view showing the structure of the RC-IGBT 1000 according to Embodiment 1, and is related to... Figure 1 The semiconductor device 100 shown or Figure 2 The cross-sectional view corresponding to the arrow direction at the dashed line GG of the semiconductor device 101 shown. Furthermore, for... Figure 9 The cross-sectional view of semiconductor device 100 or semiconductor device 101 shown is... Figure 9 The same structure is labeled with the same number, and repeated descriptions are omitted.

[0130] like Figure 23 As shown, the p-type collector layer 16 disposed on the second main surface side of the IGBT region 10 is configured to extend a distance U1 from the boundary between the IGBT region 10 and the diode region 20 toward the diode region 20. In this way, by configuring the p-type collector layer 16 to extend into the diode region 20, the n-type collector layer of the diode region 20 can be increased. + The distance between the cathode layer 26 and the active trench gate 11 allows current to flow from the channel formed adjacent to the active trench gate 11 in the IGBT region 10 to the n-type cathode layer 26, even when a gate drive voltage is applied to the gate trench electrode 11a during freewheeling diode operation. + The cathode layer 26 is used for suppression.

[0131] At once Figure 23In the case of the RC-IGBT 1000 shown, the diode region 20 has the first principal surface of the semiconductor substrate, i.e., n. + Type source layer 13, p + Type contact layer 14, from p + The upper end of the paper surface of the type contact layer 24 and the type anode layer 25 reaches n - The drift layer 1 includes multiple active trench gates 11, multiple dumb trench gates 12, multiple diode trench gates 21, multiple diode semi-trench gates 22, and diode dumb active trench gates 41.

[0132] Furthermore, the present invention is characterized by the structure of the diode region 20, and therefore the following description will focus on the structure of the diode region 20.

[0133] like Figure 23 As shown, the diode's dumb active trench gate 41 is sandwiched between two diode half-trench gates 22, and a third semiconductor layer, namely a p-type anode layer 41c, is disposed between the diode's dumb active trench gate 41 and the diode half-trench gates 22. Moreover, the two diode half-trench gates 22 and the diode's dumb active trench gate 41 are covered by a continuous interlayer insulating film 4, and the p-type anode layer 41c is not given a first potential, namely the emitter potential, but is in a floating state.

[0134] The diode trench gate 21 is in the p + The p-type contact layer 24, the p-type anode layer 25, and the n-type carrier accumulation layer 2 penetrate to reach the n-type anode layer 25. - Within the trench of the drift layer 1, a diode trench electrode 21a is disposed with a diode trench insulating film 21b in between, and the diode trench electrode 21a is electrically connected to the emitter electrode 6.

[0135] The diode's half-trench gate 22 penetrates the p-type anode layer 25 and the n-type carrier accumulation layer 2 to reach the n-type anode. - Within the trench of the drift layer 1, a diode half-trench electrode 22a is disposed with a diode half-trench insulating film 22b in between, and the diode half-trench electrode 22a is electrically connected to the emitter electrode 6.

[0136] A p-type anode layer 25 electrically connected to the emitter electrode 6 is provided on one side of the two sides of the diode semi-trench gate 22, and a p-type anode layer 41c that is not electrically connected to the emitter electrode 6 and is in a floating state is provided on the other side. This trench gate with such a structure having a p-type anode layer in a floating state on one side of the trench gate is called a "semi-trench gate".

[0137] The diode's dumb active trench gate 41 penetrates the p-type anode layer 41c and the n-type carrier accumulation layer 2 to reach the n-type anode. -Within the trench of the drift layer 1, a diode dumb active trench electrode 41a is disposed with a diode dumb active trench insulating film 41b in between, and the diode dumb active trench electrode 41a is electrically connected to a gate electrode (not shown).

[0138] On both sides of the side of the diode's dummy active trench gate 41, there are p-type anode layers 41c that are not electrically connected to the emitter electrode 6 but are in a floating state. This structure, in which the trench electrode is electrically connected to the gate electrode and there is a p-type anode layer in a floating state on one side of the gate, is called a "dummy active trench gate".

[0139] As described above, in diode region 20, the RC-IGBT 1000 applies an emitter potential E to the diode trench electrode 21a of the diode trench gate 21 and the diode half-trench electrode 22a of the diode half-trench gate 22, and applies a gate potential G to the diode dumb active trench electrode 41a of the diode dumb active trench gate 41.

[0140] Thus, by configuring the diode dummy active trench gate 41 in the diode region, displacement current can be suppressed. That is, in the diode region, since holes are injected from the anode but not from the cathode when the diode operates, the potential of the p-type anode layer 41c will not change due to holes injected from the cathode, and the displacement current flowing through the diode dummy active trench gate 41 can be suppressed.

[0141] Furthermore, the p-type collector layer 16 provided on the second main surface side of the IGBT region 10 is configured to extend a distance U1 from the boundary between the IGBT region 10 and the diode region 20 toward the diode region 20, but no diode dumb active trench gate 41 is provided on the first main surface side corresponding to the region where the p-type collector layer 16 extends. This allows for the suppression of displacement current flowing through the diode dumb active trench gate 41.

[0142] Furthermore, since no dummy active trench gate is provided in the IGBT region, the holes injected from the collector layer when the IGBT is turned on will not cause the potential of the floating p-type base layer 15 to change. Therefore, the displacement current flowing through the dummy active trench gate can be suppressed, and the gate resistance controllability reduction of dV / dt can be suppressed.

[0143] In addition, a p-type anode layer 41c is provided between the diode dumb active trench gate 41 and the diode half trench gate 22 by sandwiching the diode half active trench gate 22. The p-type anode layer 41c is not connected to the emitter potential but is in a floating state.

[0144] Therefore, through the diode dumb active trench gate 41, the diode dumb active trench electrode 41a, the diode dumb active trench insulating film 41b, the floating p-type anode layer 41c, and the n...- A capacitor is formed in the drift layer 1. This means that a capacitor is formed between the diode's dummy active trench electrode 41a and the collector electrode 7, i.e., the cathode electrode that imparts the second potential. This means increasing the gate-collector capacitance (feedback capacitance) Cgc between the gate and collector of the IGBT. By increasing the feedback capacitance (Cgc), conduction losses can be reduced under the condition that the drain voltage V varies with time t, i.e., dV / dt, remains constant.

[0145] In addition, Figure 23 In this diode, the p-type anode layer 41c disposed on both sides of the dummy active trench gate 41 is at a floating potential, but within the cell region, the p-type anode layer 41c can also be connected to the emitter electrode 6. Additionally, in the end region, it can be connected to the p-type end well layer 31 (… Figure 11 The p-type end-well layer 31 can be electrically connected to the emitter electrode 6, or it can be disconnected. In this case, the p-type end-well layer 31 can also be electrically connected to the emitter electrode 6. That is, the p-type anode layer 41c can be electrically connected to the emitter electrode 6 and the electrode in the end region, or it can be disconnected. By making the p-type anode layer 41c not electrically connected to the emitter electrode 6 directly above, but electrically connected to the emitter electrode 6 at a position far away, it is connected to the emitter electrode 6 through a high resistance, simulating a floating state, and thus the effect of increasing the feedback capacitance (Cgc) can be obtained.

[0146] <Effect>

[0147] As described above, according to the RC-IGBT 1000 of Embodiment 1, the displacement current flowing through the diode dummy active trench gate 41 can be suppressed. In addition, the diode dummy active trench gate 41 is provided in the diode region 20, and a floating p-type anode layer 41c is provided next to it, thereby increasing the feedback capacitance Cgc between the gate and collector of the IGBT. Therefore, the conduction loss can be reduced under the condition of constant dV / dt.

[0148] <Variation Example>

[0149] At once Figure 23 In the case of the RC-IGBT 1000 shown, a structure with only one diode dumb active trench gate 41 sandwiched between two diode half trench gates 22 is disclosed, but it is not limited to this and multiple diode dumb active trench gates 41 can also be provided.

[0150] For example, Figure 24 The RC-IGBT 1001 shown has a structure in which two diode dumb active trench gates 41 are disposed between two diode half trench gates 22.

[0151] The diode's dummy active trench gate 41 is configured to be sandwiched between two diode half-trench gates 22. Thus, when the diode's dummy active trench gate 41 and diode half-trench gates 22 are arranged adjacently, a coupling capacitance, namely the gate-emitter capacitance Cge, is generated between the diode's dummy active trench gate 41 at its gate potential and the diode's half-trench gate 22 at its emitter potential. If the gate-emitter capacitance Cge is generated, the gate capacitance ratio Cgc / Cge becomes smaller, which is detrimental to reducing conduction losses.

[0152] Therefore, as Figure 24 As shown in the RC-IGBT 1001, by increasing the number of dummy active trench gates 41 of the diodes, the gate capacitance ratio Cgc / Cge can be further increased, thereby further reducing the conduction loss.

[0153] <Implementation Method 2>

[0154] <Structure>

[0155] Figure 25 This is a partial cross-sectional view showing the structure of the RC-IGBT 2000 according to Embodiment 2, and is related to... Figure 1 The semiconductor device 100 shown or Figure 2 The cross-sectional view corresponding to the arrow direction at the dashed line GG of the semiconductor device 101 shown. Furthermore, for... Figure 9 The cross-sectional view of semiconductor device 100 or semiconductor device 101 shown is... Figure 9 The same structure is labeled with the same number, and repeated descriptions are omitted.

[0156] At once Figure 25 In the RC-IGBT 2000 shown, the diode region 20 extends from the upper end of the paper plane of the first main surface of the semiconductor substrate, i.e., the p-type anode layer 25, to the n-type anode layer. - The drift layer 1 comprises multiple diode trench gates 21 and two adjacently arranged diode semi-dull active trench gates 51. Furthermore, a p-type anode layer 41c is disposed between the two diode semi-dull active trench gates 51. The two diode semi-dull active trench gates 51 are covered by a continuous interlayer insulating film 4, and the p-type anode layer 41c is not given an emitter potential but is in a floating state.

[0157] The diode's semi-dull active trench gate 51 penetrates the p-type anode layer 41c and the n-type carrier accumulation layer 2 to reach the n-type anode. - Within the trench of the drift layer 1, a diode semi-dull active trench electrode 51a is disposed with a diode semi-dull active trench insulating film 51b in between, and the diode semi-dull active trench electrode 51a is electrically connected to a gate electrode (not shown).

[0158] A p-type anode layer 25 electrically connected to the emitter electrode 6 is provided on one side of the two sides of the diode semi-dull active trench gate 51, and a p-type anode layer 41c in a floating state is provided on the other side.

[0159] As described above, in diode region 20, the RC-IGBT 2000 applies an emitter potential E to the diode trench electrode 21a of the diode trench gate 21 and the diode half-trench electrode 22a of the diode half-trench gate 22, and applies a gate potential G to the diode half-dumb active trench electrode 51a of the diode half-dumb active trench gate 51.

[0160] Thus, by configuring the diode semi-dull active trench gate 51 in the diode region, displacement current can be suppressed. That is, in the diode region, since holes are injected from the anode but not from the cathode when the diode is operating, the potential of the p-type anode layer 41c will not change due to holes injected from the cathode, and the displacement current flowing through the diode semi-dull active trench gate 51 can be suppressed.

[0161] Furthermore, the p-type collector layer 16 provided on the second main surface side of the IGBT region 10 is configured to extend a distance U1 from the boundary between the IGBT region 10 and the diode region 20 toward the diode region 20, but no diode semi-dull active trench gate 51 is provided on the first main surface side corresponding to the region where the p-type collector layer 16 extends. This also allows for suppression of the displacement current flowing through the diode semi-dull active trench gate 51.

[0162] Furthermore, since no dummy active trench gate is provided in the IGBT region, the holes injected from the collector layer when the IGBT is turned on will not cause the potential of the floating p-type base layer 15 to change. Therefore, the displacement current flowing through the dummy active trench gate can be suppressed, and the gate resistance controllability reduction of dV / dt can be suppressed.

[0163] In addition, a p-type anode layer 41c is provided between the two diode semi-dummy active trench gates 51. The p-type anode layer 41c is not connected to the emitter potential but is in a floating state.

[0164] Therefore, through the diode semi-dull active trench gate 51, the diode semi-dull active trench electrode 51a, the diode semi-dull active trench insulating film 51b, the floating p-type anode layer 41c, and the n... -A capacitor is formed in the drift layer 1. This means that a capacitor is formed between the diode semi-dull active trench electrode 51a and the collector electrode 7, i.e., the cathode electrode that imparts the second potential. This means increasing the gate-collector capacitance (feedback capacitance) Cgc between the gate and collector of the IGBT. By increasing the feedback capacitance (Cgc), conduction losses can be reduced under the condition that the drain voltage V varies with time t, i.e., dV / dt, remains constant.

[0165] <Effect>

[0166] As described above, according to the RC-IGBT 2000 of Embodiment 2, the displacement current flowing through the diode semi-dull active trench gate 51 can be suppressed. In addition, the diode semi-dull active trench gate 51 is provided in the diode region 20, and a floating p-type anode layer 41c is provided next to it. This increases the feedback capacitance Cgc between the gate and collector of the IGBT, thereby reducing the conduction loss under the condition of constant dV / dt.

[0167] <Variation Example 1>

[0168] At once Figure 25 The RC-IGBT 2000 shown depicts a structure in which a floating p-type anode layer 41c is disposed between the diode's semi-dull active trench gate 51, but it can also be configured as follows: Figure 26 As shown in the RC-IGBT 2001, it is configured such that a diode dumb active trench gate 41 is provided next to the diode semi-dumb active trench gate 51.

[0169] like Figure 26 As shown, the diode's dumb active trench gate 41 penetrates the p-type anode layer 41c and the n-type carrier accumulation layer 2 to reach the n-type anode. - Within the trench of the p-type drift layer 1, a diode dumb active trench electrode 41a is disposed, separated by a diode dumb active trench insulating film 41b. The diode dumb active trench electrode 41a is electrically connected to a gate electrode (not shown). Furthermore, the two diode half-dumb active trench gates 51 and the diode dumb active trench gate 41 are covered by a continuous interlayer insulating film 4, and the p-type anode layer 41 is not given an emitter potential but is in a floating state.

[0170] Thus, by arranging the diode's dumb active trench gate 41 adjacent to the diode's semi-dumb active trench gate 51 in the diode region, displacement current can be suppressed. That is, in the diode region, since holes are injected from the anode but not from the cathode during diode operation, the potential of the p-type anode layer 41c will not change due to holes injected from the cathode, thereby suppressing the displacement current flowing through the diode's dumb active trench gate 41.

[0171] Furthermore, by configuring the diode dumb active trench gate 41, the diode dumb active trench electrode 41a, the diode dumb active trench insulating film 41b, the floating p-type anode layer 41c, and the n-type anode layer 41 are formed by the diode dumb active trench gate 41. - A type-type drift layer 1 forms a capacitor. This allows for a further increase in the gate-collector capacitance (feedback capacitance) Cgc between the gate and collector of the IGBT. By further increasing the feedback capacitance (Cgc), conduction losses can be further reduced while the drain voltage V varies with time t, i.e., dV / dt remains constant.

[0172] Furthermore, since the diode dummy active trench gate 41 and the diode semi-dummy active trench gate 51, which are given gate potential, are arranged adjacent to each other, no coupling capacitance, i.e., gate-emitter capacitance Cge, is generated between them. This increases the gate capacitance ratio Cgc / Cge, thereby reducing conduction losses.

[0173] At once Figure 26 In the case of the RC-IGBT 2001 shown, a structure with only one diode dumb active trench gate 41 sandwiched between two diode semi-dumb active trench gates 51 is disclosed, but it is not limited to this and multiple diode dumb active trench gates 41 can also be provided.

[0174] By increasing the number of dummy active trench gates 41 of the diode, the gate capacitance ratio Cgc / Cge can be further increased, thereby further reducing the conduction loss.

[0175] <Variation Example 2>

[0176] At once Figure 26 As shown in the RC-IGBT 2001, a layer extending from the upper end of the paper surface of the first main surface of the semiconductor substrate, namely the p-type anode layer 25, to the n-type anode layer is provided. - The structure of multiple diode trench gates 21 in the drift layer 1 is as follows, but it can also be like... Figure 27 As shown in the RC-IGBT 2002, it is configured to replace multiple diode trench gates 21 and have a distance from the first main surface of the semiconductor substrate to n - The structure of multiple diode active trench gates 61 in the drift layer 1.

[0177] The active trench gate 61 of the diode is in the p + The p-type contact layer 24, the p-type anode layer 25, and the n-type carrier accumulation layer 2 penetrate to reach the n-type anode layer 25. - Within the trench of the drift layer 1, a diode active trench electrode 61a is disposed with a diode active trench insulating film 61b in between, and the diode active trench electrode 61a is electrically connected to a gate electrode (not shown).

[0178] Therefore, a capacitor is formed by the diode active trench electrode 61a of the diode active trench gate 61, the diode active trench insulating film 61b, and the p-type anode layer 25 electrically connected to the emitter electrode 6, generating a gate-emitter capacitance Cge. However, simultaneously, a capacitor is also formed by the diode active trench electrode 61a, the diode active trench insulating film 61b, and the n-type anode layer 25. - The capacitor formed by the drift layer 1 also generates a gate-collector capacitance (feedback capacitance) Cgc. Therefore, in conjunction with the gate-collector capacitance (feedback capacitance) Cgc formed by the diode-configured dumb active trench gate 41 and the diode-configured half-dumb active trench gate 51, the feedback capacitance (Cgc) can be further increased, and the conduction loss can be further reduced under the condition that the drain voltage V varies with time t, i.e., dV / dt, is constant.

[0179] <Implementation Method 3>

[0180] <Structure>

[0181] Figure 28 This is a partial cross-sectional view showing the structure of the RC-IGBT 3000 according to Embodiment 3, and is related to... Figure 1 The semiconductor device 100 shown or Figure 2 The cross-sectional view corresponding to the arrow direction at the dashed line GG of the semiconductor device 101 shown. Furthermore, for... Figure 9 The cross-sectional view of semiconductor device 100 or semiconductor device 101 shown is... Figure 9 The same structure is labeled with the same number, and repeated descriptions are omitted.

[0182] At once Figure 28 Regarding the RC-IGBT 3000 shown, compared to Figure 26 The RC-IGBT2001 shown is similar in that it has a structure in which a diode dumb active trench gate 41 is disposed next to the diode half-dumb active trench gate 51, but the spacing between the diode dumb active trench gate 41 and the diode half-dumb active trench gate 51 is set to be shorter than the spacing between adjacent diode trench gates 21, or adjacent active trench gates 11, or adjacent active trench gates 11 and dumb trench gates 12.

[0183] In addition, Figure 28 In this example, the number of diode dummy active trench gates 41 is set to 1, but it is not limited to this; multiple diode dummy active trench gates 41 can be configured.

[0184] In this case, the spacing between the diode dumb active trench gate 41 and the diode half-dumb active trench gate 51, and the spacing between adjacent diode dumb active trench gates 41, can be set to 1 / 2 to 1 / 4 of the spacing between other adjacent trench gates.

[0185] <Effect>

[0186] By narrowing the spacing between the diode dumb active trench gate 41 and the diode half-dumb active trench gate 51, the diode dumb active trench gate 41 and the diode half-dumb active trench gate 51 can be configured with high density. Therefore, by increasing the number of diode dumb active trench gates 41, the gate-collector capacitance (feedback capacitance) Cgc between the gate and collector of the IGBT can be increased, and the conduction loss can be reduced under the condition that the drain voltage V varies with time t, i.e., dV / dt is constant.

[0187] <Variation Example>

[0188] Regarding the RC-IGBT 3000 of Embodiment 3 described above, a structure is disclosed in which the number of diode dumb active trench gates 41 is increased by making the spacing between the diode dumb active trench gate 41 and the diode half-dumb active trench gate 51 narrower than the spacing between other adjacent trench gates, thereby increasing the structure of the feedback capacitor Cgc. However, as... Figure 29 As shown in the RC-IGBT3001, the feedback capacitance Cgc can also be increased by setting the configuration pattern of the diode's dummy active trench gate 41 to a grid pattern.

[0189] Figure 29 This is a partial top view showing the structure of the RC-IGBT 3001, specifically a view of the diode region 20 from above, showing the diode's dull active trench gate 41 and semi-dull active trench gate 51. Furthermore, for convenience, in... Figure 29 The diagram of the emitter electrode 6 and other structures is omitted.

[0190] like Figure 29 As shown, the diode dumb active trench gate 41 branches in multiple portions along the trench's extension direction, perpendicular to the trench's extension direction, and connects to the adjacent diode semi-dumb active trench gate 51. As a result, a lattice-shaped trench gate is formed by the diode dumb active trench gate 41 and the diode semi-dumb active trench gate 51, and the p-type anode layer 41c becomes a rectangular region surrounded by the lattice-shaped trench gate when viewed from above.

[0191] Therefore, the gate-collector capacitance (feedback capacitance) Cgc formed by the configuration of the diode dumb active trench gate 41 and the diode semi-dumb active trench gate 51 increases, which can reduce the conduction loss under the condition that the drain voltage V varies with time t, i.e., dV / dt is constant.

[0192] Furthermore, there is no particular limitation on the number of rectangular p-type anode layers 41c formed when viewed from above, as long as they fall within the range of the length of the strip-shaped diode dumb active trench gate 41 and the size range that can form the diode dumb active trench insulating film 41b and the diode dumb active trench electrode 41a.

[0193] <Implementation Method 4>

[0194] <Structure>

[0195] Figure 30 This is a partial cross-sectional view showing the structure of the RC-IGBT 4000 according to Embodiment 4, and is related to... Figure 1 The semiconductor device 100 shown or Figure 2 The cross-sectional view corresponding to the arrow direction at the dashed line GG of the semiconductor device 101 shown. Furthermore, for... Figure 9 The cross-sectional view of semiconductor device 100 or semiconductor device 101 shown is... Figure 9 The same structure is labeled with the same number, and repeated descriptions are omitted.

[0196] At once Figure 30 Regarding the RC-IGBT 4000 shown, compared to Figure 23 Similar to the RC-IGBT1001 shown, the diode's dumb active trench gate 41 is configured to be sandwiched between two diode half-trench gates 22, but no p-type anode layer 41c is provided in the mesa region between the diode's dumb active trench gate 41 and the diode half-trench gate 22, becoming an n-type anode. - There is no n-type drift layer 1, nor is there an n-type carrier accumulation layer 2.

[0197] <Effect>

[0198] When a p-type anode layer 41c is provided in the mesa region between the diode's dummy active trench gate 41 and the diode's half-trench gate 22, a small number of holes caused by the reverse recovery current during the diode's recovery operation cause the potential of the floating p-type anode layer 41c to fluctuate, sometimes generating a displacement current. However, by not forming a p-type semiconductor layer at this location, the effect of the displacement current on the diode's dummy active trench gate 41 can be suppressed.

[0199] <Implementation Method 5>

[0200] <Structure>

[0201] Figure 31 As shown in Embodiment 5, a top view of an island-type semiconductor device 102 is presented, comprising an IGBT region 10 and a diode region 20 within a single semiconductor device. Figure 31 In the diagram, arrow AR indicates the extension direction of the trench gate. For example... Figure 31As shown, the trench gate extends along the arrangement direction of the control pads 410. Furthermore, regarding... Figure 2 The semiconductor device 101 shown has the same structure and is labeled with the same reference numerals, and repeated descriptions are omitted.

[0202] Figure 32 yes Figure 31 The cross-sectional view with the arrow pointing in the direction of the EE line. Figure 32 The cross-sectional structure of the IGBT region 10 shown is similar to Figure 4 The cross-sectional structures of the IGBT regions 10 shown are identical, and the same labels are used for the same structures, omitting repeated descriptions.

[0203] Figure 33 yes Figure 31 The cross-sectional view with the arrow pointing in the direction of the GG line. Figure 33 The cross-sectional structure of diode region 20 shown is similar to Figure 26 The cross-sectional structure of the RC-IGBT 2001 shown is basically the same, consisting of a diode dumb active trench gate 41 disposed next to the diode semi-dumb active trench gate 51. Furthermore, structures identical to the RC-IGBT 2001 are labeled with the same reference numerals, and repeated descriptions are omitted.

[0204] like Figure 31 As shown, the IGBT region 10 and the diode region 20 are alternately arranged in the extension direction of the trench gate, and the trench gate has a structure that penetrates the IGBT region 10 and the diode region 20 when viewed from above.

[0205] In this structure, in IGBT region 10, such as Figure 32 As shown, for example, in a configuration with gate pad 410c ( Figure 31 The active trench gate 11 of the gate trench electrode 11a, which is electrically connected, has an n-shaped outer side provided on either of the two sides. + Type source layer 13, n + The source electrode layer 13 is electrically connected to the emitter electrode 6.

[0206] On the other hand, in diode region 20, such as Figure 33 As shown, at the two diode semi-dummy active trench gates 51 and the diode dumb active trench gate 41 disposed between them, each diode semi-dummy active trench electrode 51a and diode dumb active trench electrode 41a are connected to the gate pad 410c. Figure 31 Electrical connection. In addition, the p-type anode layer 41c disposed between the diode dumb active trench gate 41 and the diode semi-dumb active trench gate 51 is not electrically connected to the emitter electrode 6, and is in a floating state.

[0207] <Effect>

[0208] As described above, by making the active trench gate 11 in the IGBT region 10, the diode dumb active trench gate 41 in the diode region 20, and the diode semi-dumb active trench gate 51 composed of continuous trench gates, the feedback capacitance Cgc can be increased. This is because the feedback capacitance Cgc is increased by adding a continuous trench gate composed of the gate trench electrode 11a, the gate trench insulating film 11b, and the n... - The feedback capacitance Cgc generated by the capacitor formed by the drift layer 1.

[0209] <Variation Example>

[0210] Figure 34 It is an enlarged representation Figure 31 A partial top view of region 83, enclosed by dashed lines, of the diode region 20 in the semiconductor device 102 shown. Figure 34 As shown, in diode region 20, diode trench gate 21 extends along the first main surface of semiconductor device 102 from one end of unit region, i.e., diode region 20, to the opposite end. A p-type junction is provided between two adjacent diode trench gates 21. + The diode has a p-type contact layer 24 and a p-type anode layer 25. Additionally, a diode dumb active trench gate 41 is provided, sandwiched between two diode trench gates 21.

[0211] Furthermore, in the extending direction of the diode active trench gate 41, a portion thereof is formed as the diode active trench gate 61, the upper part of which is covered by the interlayer insulating film 4. However, the p-type active trench gate 61 is positioned in a manner that sandwiches the diode active trench gate 61. + A portion of the p-type contact layer 24 and the p-type anode layer 25 are electrically connected to the emitter electrode.

[0212] On the other hand, the upper part of the p-type anode layer 41c, which is provided in such a way as to sandwich the diode dumb active trench gate 41, is covered by the interlayer insulating film 4 and is not electrically connected to the emitter electrode but is in a floating state.

[0213] Figure 35 yes Figure 34 The cross-sectional view showing the direction of the arrow at the CC line. (See example...) Figure 35 As shown, the upper part of the active trench gate 61 of the diode is covered by the interlayer insulating film 4, but the p-values ​​on the outer sides of the two sides of the active trench gate 61 of the diode are not fully exposed. + The contact layer 24 is electrically connected to the emitter electrode 6.

[0214] Figure 36 yes Figure 34 A cross-sectional view showing the direction of the arrow at the DD line. (See example...) Figure 36As shown, the diode's dumb active trench gate 41 and the two diode trench gates 21 sandwiched between it are covered by a continuous interlayer insulating film 4, and the p-type anode layer 41c is not given an emitter potential but is in a floating state.

[0215] Thus, in diode region 20, the regions that become diode dumb active trench gate 41 and diode active trench gate 61 are alternately arranged in the extension direction of the trench gate, and the trench electrodes of these trench gates are electrically connected to the gate pad 410c. Furthermore, the trench electrodes of these trench gates become the gate trench electrodes 11a of the active trench gate 11 in IGBT region 10. The active trench gate 11, diode dumb active trench gate 41, and diode active trench gate 61 are composed of continuous trench gates. Alternatively, a diode semi-dumb active trench gate 51 may be provided instead of the diode dumb active trench gate 41.

[0216] <Effect>

[0217] As described above, by making the active trench gate 11 in the IGBT region 10, the diode dumb active trench gate 41 in the diode region 20, and the diode active trench gate 61 composed of continuous trench gates, the feedback capacitance Cgc can be increased. This is because the feedback capacitance Cgc is increased by adding a continuous trench gate composed of the gate trench electrode 11a, the gate trench insulating film 11b, and the n... - The feedback capacitance Cgc generated by the capacitor formed by the drift layer 1.

[0218] <Applicable semiconductor materials>

[0219] The semiconductor substrate is not mentioned in the embodiments 1 to 5 described above, but it can be made of either silicon (Si) or silicon carbide (SiC).

[0220] Switching elements made of SiC have low switching losses and can perform high-speed switching operations.

[0221] Furthermore, switching elements made of SiC exhibit low power loss and high heat resistance. Therefore, when constructing a power module with a cooling section, the heat sink fins can be miniaturized, thus enabling further miniaturization of the semiconductor module.

[0222] Furthermore, switching elements made of SiC are suitable for high-frequency switching operations. Therefore, in the case of converter circuits with high frequency requirements, by increasing the switching frequency, it is also possible to miniaturize reactors or capacitors connected to the converter circuit.

[0223] As a wide-bandgap semiconductor besides SiC, it can also be composed of gallium nitride-based materials, gallium oxide-based materials, or diamond, etc.

[0224] Furthermore, within the scope of the invention, the various embodiments can be freely combined, and appropriate modifications or omissions can be made to each embodiment.

[0225] Explanation of the label

[0226] 1n - Type-3 drift layer, 6 emitter electrode, 7 collector electrode, 10 IGBT region, 11 active trench gate, 16p-type collector layer, 20 diode region, 25, 41 c p-type anode layer, 26n + Type 41 cathode layer, 41 diode dumb active trench gate, 51 diode semi-dumb active trench gate, 61 diode active trench gate.

Claims

1. A semiconductor device having a transistor and a diode formed on a common semiconductor substrate, wherein, The semiconductor substrate has: Transistor region, on which the transistor is formed; and A diode region, on which the aforementioned diode is formed. The diode region has: A first semiconductor layer of a first conductivity type is disposed on the second main surface side of the semiconductor substrate; A second semiconductor layer of a first conductivity type is disposed on the first semiconductor layer; A third semiconductor layer of a second conductivity type is disposed on the first main surface side of the semiconductor substrate compared to the second semiconductor layer; The first main electrode imparts a first potential to the diode; The second main electrode imparts a second potential to the diode; as well as At least one dumb active trench gate is configured to extend from the first main surface of the semiconductor substrate to the second semiconductor layer. The at least one dumb active trench gate has a third semiconductor layer that is not given the first potential but is in a floating state on at least one of its two sides. The transistor is given a gate potential to the at least one dumb active trench gate.

2. The semiconductor device according to claim 1, wherein, The diode region has a plurality of trench gates arranged in such a manner that they extend from the first main surface of the semiconductor substrate to the second semiconductor layer. The at least one dumb active trench gate is configured to be sandwiched between two half-trench gates. A third semiconductor layer, which is in a floating state, is provided between the at least one dumb active trench gate and the two half-trench gates. The plurality of trench gates have a third semiconductor layer on each of their two sides, which is imparted with the first potential. The two half-trench gates have a third semiconductor layer in a floating state on one of their respective two sides, which is the side that becomes the at least one dumb active trench gate, and a third semiconductor layer that is imparted with the first potential on the other side. The first potential is applied to the plurality of trench gates and the two half-trench gates.

3. The semiconductor device according to claim 2, wherein, The at least one dumb active trench gate is disposed in multiple locations between the two half-trench gates.

4. The semiconductor device according to claim 1, wherein, The diode region has a plurality of trench gates arranged in such a manner that they extend from the first main surface of the semiconductor substrate to the second semiconductor layer. The at least one dumb active trench gate is provided as two half-dumb active trench gates configured opposite to each other. The two semi-dull active trench gates each have a third semiconductor layer in a floating state on one of their respective opposite sides, and a third semiconductor layer that is imparted with the first potential on the other side. The plurality of trench gates have a third semiconductor layer on each of their two sides, which is imparted with the first potential. The gate potential of the transistor is applied to the two semi-dummy active trench gates. The first potential is applied to the plurality of trench gates.

5. The semiconductor device according to claim 1, wherein, The diode region has a plurality of trench gates arranged in such a manner that they extend from the first main surface of the semiconductor substrate to the second semiconductor layer. The at least one dumb active trench gate is configured to be sandwiched between two half-dumb active trench gates. A third semiconductor layer, which is in a floating state, is provided between the at least one dumb active trench gate and the two half-dumb active trench gates. The plurality of trench gates have a third semiconductor layer on each of their two sides, which is imparted with the first potential. The two semi-dull active trench gates each have a third semiconductor layer in a floating state on one of their respective two sides that forms the at least one dumb active trench gate side, and a third semiconductor layer that is imparted with the first potential on the other side. The gate potential of the transistor is applied to the two semi-dummy active trench gates. The first potential is applied to the plurality of trench gates.

6. The semiconductor device according to claim 1, wherein, The diode region has a plurality of active trench gates and a plurality of trench gates, which are arranged from the first main surface of the semiconductor substrate to the second semiconductor layer. The at least one dumb active trench gate is configured to be sandwiched between two half-dumb active trench gates. A third semiconductor layer, which is in a floating state, is provided between the at least one dumb active trench gate and the two half-dumb active trench gates. The plurality of active trench gates have a third semiconductor layer on each of their two sides, which is imparted with the first potential. The two semi-dull active trench gates each have a third semiconductor layer in a floating state on one of their respective two sides that forms the at least one dumb active trench gate side, and a third semiconductor layer that is imparted with the first potential on the other side. The transistor is given a gate potential on the plurality of active trench gates and the two semi-dummy active trench gates.

7. The semiconductor device according to claim 5 or 6, wherein, The at least one dumb active trench gate is disposed between the two half-dumb active trench gates.

8. The semiconductor device according to claim 5 or 6, wherein, The configuration spacing of the at least one dumb active trench gate and the two half-dumb active trench gates is at least narrower than the configuration spacing of the plurality of trench gates.

9. The semiconductor device according to claim 5 or 6, wherein, At multiple points along the extension direction, the at least one dumb active trench gate branches in a direction perpendicular to the extension direction and connects to the two semi-dumb active trench gates, forming a lattice-like planar pattern.

10. A semiconductor device having a transistor and a diode formed on a common semiconductor substrate, wherein, The semiconductor substrate has: Transistor region, on which the transistor is formed; and A diode region, on which the aforementioned diode is formed. The diode region has: A first semiconductor layer of a first conductivity type is disposed on the second main surface side of the semiconductor substrate; A second semiconductor layer of a first conductivity type is disposed on the first semiconductor layer; A third semiconductor layer of a second conductivity type is disposed on the first main surface side of the semiconductor substrate compared to the second semiconductor layer; The first main electrode imparts a first potential to the diode; The second main electrode imparts a second potential to the diode; as well as At least one dumb active trench gate is configured to extend from the first main surface of the semiconductor substrate to the second semiconductor layer. The at least one dumb active trench gate has a second semiconductor layer on at least one of its two sides that is not given the first potential but is in a floating state. The transistor is given a gate potential to the at least one dumb active trench gate.

11. The semiconductor device according to claim 1, wherein, The transistor region and the diode region are alternately arranged in the extension direction of the trench gate. The trench gate is configured to penetrate both the transistor region and the diode region when viewed from above. In the transistor region, the at least one dummy active trench gate is configured to extend from the first main surface of the semiconductor substrate to the second semiconductor layer, and is configured to be continuous with the active trench gate to which the gate potential of the transistor is applied.

12. The semiconductor device according to claim 1, wherein, The transistor region and the diode region are alternately arranged in the extension direction of the trench gate. The trench gate is configured to penetrate both the transistor region and the diode region when viewed from above. The diode region is configured such that, The region having at least one dumb active trench gate is alternately configured with the region having at least one active trench gate disposed in such a manner that it extends from the first main surface of the semiconductor substrate to the second semiconductor layer. In the transistor region, the at least one dumb active trench gate and the at least one active trench gate are configured to extend from the first main surface of the semiconductor substrate to the second semiconductor layer, and are configured to be continuous with the active trench gate to which the gate potential of the transistor is applied.

13. The semiconductor device according to claim 1, wherein, The semiconductor substrate is made of a material selected from silicon, silicon carbide, gallium nitride, gallium oxide, or diamond.

Images