Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprises a substrate, a channel layer, a barrier layer and a first P-type semiconductor layer which are stacked in sequence, the channel layer and the barrier layer form a heterojunction, and the first P-type semiconductor layer exhausts 2DEG at a channel to realize an enhanced device; the first P-type semiconductor layer, the aluminum-containing film layer and the gate contact layer of which the side walls are aligned are sequentially arranged above the barrier layer of the gate region, so that the gate leakage current can be reduced, and the breakdown voltage can be improved by increasing the Schottky barrier height between the gate contact layer and the first P-type semiconductor layer; and meanwhile, side wall alignment is realized through a metal self-alignment process with a relatively simple process.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor structure and its fabrication method. Background Technology

[0002] Compared to first- and second-generation semiconductor materials, third-generation semiconductor materials, especially GaN (gallium nitride)-based materials, have advantages such as large bandgap, high breakdown field strength, high electron mobility, and strong radiation resistance. GaN-based HEMT (High Electron Mobility Transistor) devices have great development potential in high-frequency, high-power fields such as wireless communication base stations, radar, and automotive electronics.

[0003] Typically, GaN-based HEMT devices are depletion-mode field-effect transistors. In RF and microwave applications, negative turn-on voltages are required, which complicates the circuit structure and affects the circuit's anti-false-start protection, reducing circuit safety. Therefore, it is necessary to research enhancement-mode GaN-based HEMT devices. Traditional GaN-based HEMT devices can achieve enhancement mode using a P-type gate, but they still suffer from problems such as low breakdown voltage. Summary of the Invention

[0004] In view of this, embodiments of this application provide a semiconductor structure and a method for fabricating the same, to solve the technical problem of low breakdown voltage in the prior art.

[0005] According to one aspect of this application, an embodiment of this application provides a semiconductor structure comprising a substrate, a channel layer, and a barrier layer stacked sequentially. The channel layer and the barrier layer include a gate region, and a source region and a drain region located on opposite sides of the gate region. The gate region includes a first P-type semiconductor layer, an aluminum-containing film layer, and a gate contact layer stacked sequentially on the side of the barrier layer away from the substrate. The sidewalls of the first P-type semiconductor layer, the sidewalls of the aluminum-containing film layer, and the sidewalls of the gate contact layer are aligned. The aluminum-containing film layer is made of at least one of AlN, AlON, and Al2O3. The source region includes a source contact layer located on the side of the channel layer away from the substrate. The drain region includes a drain contact layer located on the side of the channel layer away from the substrate.

[0006] According to another aspect of this application, one embodiment of this application provides a method for fabricating a semiconductor structure. The method includes: sequentially epitaxially fabricating a channel layer and a barrier layer on a substrate, wherein the channel layer and the barrier layer include a gate region, and a source region and a drain region located on both sides of the gate region; epitaxially fabricating a P-type semiconductor material layer on the side of the barrier layer away from the substrate; depositing an aluminum-containing material layer and a metal material layer on the side of the P-type semiconductor material layer away from the substrate; wherein the material of the aluminum-containing film layer includes at least one of AlN, AlON, and Al2O3; etching away the material located on the gate region. The metal material layer between the gate region and the source region, and the metal material layer between the gate region and the drain region, form a gate contact layer in the gate region, a source contact layer in the source region, and a drain contact layer in the drain region; using the gate contact layer, the source contact layer, and the drain contact layer as masks, the aluminum-containing material layer and the P-type semiconductor material layer are etched to form a first P-type semiconductor layer and an aluminum-containing film layer in the gate region, such that the sidewalls of the first P-type semiconductor layer, the sidewalls of the aluminum-containing film layer, and the sidewalls of the gate contact layer are aligned.

[0007] This application provides a semiconductor structure and its fabrication method. The semiconductor structure includes a substrate, a channel layer, a barrier layer, and a first P-type semiconductor layer stacked sequentially. The channel layer and the barrier layer form a heterojunction. The first P-type semiconductor layer depletes the 2DEG at the channel to realize an enhancement-mode device. A first P-type semiconductor layer with sidewall alignment, an aluminum film layer, and a gate contact layer are sequentially disposed above the barrier layer in the gate region. This can reduce gate leakage current and increase the breakdown voltage by increasing the Schottky barrier height between the gate contact layer and the first P-type semiconductor layer. Meanwhile, the sidewall alignment is achieved through a relatively simple metal self-alignment process. Attached Figure Description

[0008] Figure 1 The diagram shown is a schematic representation of a semiconductor structure according to an embodiment of this application.

[0009] Figure 2 The diagram shown is a schematic representation of a gate region according to an embodiment of this application.

[0010] Figure 3 The diagram shown is a schematic diagram of another gate region structure provided in an embodiment of this application;

[0011] Figure 4 The diagram shown is a schematic diagram of another gate region structure provided in an embodiment of this application;

[0012] Figure 5 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0013] Figure 6 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0014] Figure 7 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0015] Figure 8 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0016] Figures 9 to 13 The diagram shown is an intermediate structure diagram for fabricating a semiconductor structure according to an embodiment of this application;

[0017] Figures 14 to 19 The diagram shown is an intermediate structure schematic diagram for fabricating another semiconductor structure according to an embodiment of this application;

[0018] Figure 20 The diagram shown is a schematic diagram of another intermediate structure provided in an embodiment of this application. Detailed Implementation

[0019] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0020] To address the aforementioned problems, this application provides a semiconductor structure and a method for fabricating the same. The following describes the method in conjunction with... Figures 1 to 15 Further examples illustrate the semiconductor structures and fabrication methods mentioned in this application.

[0021] Figure 1 The diagram shown is a schematic representation of a semiconductor structure according to an embodiment of this application. Figure 1 As shown, the semiconductor structure includes: a substrate 10, a channel layer 20, and a barrier layer 30 stacked sequentially. The channel layer 20 and the barrier layer 30 include a gate region 40a, and a source region 40b and a drain region 40c located on both sides of the gate region 40a. The gate region 40a includes: a first P-type semiconductor layer 51, an aluminum-containing film layer 61, and a gate contact layer 71 stacked sequentially on the side of the barrier layer 30 away from the substrate 10. The sidewalls of the first P-type semiconductor layer 51, the sidewalls of the aluminum-containing film layer 61, and the sidewalls of the gate contact layer 71 are aligned. The aluminum-containing film layer 61 is made of at least one of AlN, AlON, and Al2O3. The source region 40b includes a source contact layer 72 located on the side of the channel layer 20 away from the substrate 10. The drain region 40c includes a drain contact layer 73 located on the side of the channel layer 20 away from the substrate 10.

[0022] Specifically, such as Figure 1 As shown, the channel layer 20 and the barrier layer 30 form a heterojunction, and a 2DEG channel is formed on the surface of the channel layer 20 near the barrier layer 30. When no voltage is applied to the semiconductor device, the first P-type semiconductor layer 51 can deplete the 2DEG at the channel, realizing an enhancement-mode device. In the gate region 40a, the first P-type semiconductor layer 51, the aluminum-containing film layer 61, and the gate contact layer 71 are disposed above the barrier layer 30. The bandgap of the aluminum-containing film layer 61, located in the middle layer, is larger than the bandgap of the first P-type semiconductor layer 51, which can increase the Schottky barrier height between the gate contact layer 71 and the first P-type semiconductor layer 51, thereby increasing the breakdown voltage. At the same time, the sidewall alignment of the first P-type semiconductor layer 51, the aluminum-containing film layer 61, and the gate contact layer 71 can be achieved through a metal self-alignment process of the gate contact layer 71, which is simple. Secondly, the sidewall alignment of the gate contact layer 71 and the first P-type semiconductor layer 51 is prone to leakage current. Inserting the aluminum-containing film layer 61 in the middle can reduce the gate leakage current.

[0023] Specifically, insulating AlN, AlON, or Al2O3 is located between the first P-type semiconductor layer 51 and the gate contact layer 71, which can improve the device breakdown voltage. Its dense characteristics can reduce electron scattering on the surface of the first P-type semiconductor layer and reduce gate leakage current.

[0024] In one embodiment, such as Figure 1 As shown, the sidewalls of the first P-type semiconductor layer 51, the aluminum-containing film layer 61, and the gate contact layer 71 are all perpendicular to the plane of the substrate 10. Specifically, the gate contact layer 71 is made of metal, such as Ni and Au. Using the gate contact layer 71 as a mask, the aluminum-containing film layer 61 and the first P-type semiconductor layer 51 are etched to achieve sidewalls perpendicular to the plane of the substrate.

[0025] In one embodiment, the thickness of the aluminum-containing film layer 61 is 2-10 nm. Specifically, the thickness of the aluminum-containing film layer is greater than or equal to 2 nm, and appropriately increasing the thickness of the aluminum-containing film layer can improve the insulation properties; the thickness of the aluminum-containing film layer is less than or equal to 10 nm, and the thickness of the aluminum-containing film layer should not be excessively increased to avoid reducing the gate control capability and affecting the performance of the semiconductor device.

[0026] In one embodiment, the aluminum-containing film layer 61 is a multilayer structure composed of any two or three of AlN, AlON, and Al2O3.

[0027] Specifically, the aluminum-containing film layer 61 has a two-layer structure, and the materials may include AlN and AlON, AlON and Al2O3, or AlN and Al2O3. Alternatively, the aluminum-containing film layer 61 may have a three-layer structure, and the materials may include AlN, AlON, and Al2O3.

[0028] In one embodiment, in the aluminum-containing film layer 61, the film layer with a higher oxygen content is located on the side of the film layer with a lower oxygen content away from the substrate; and / or, the film layer with a higher oxygen content constitutes a sidewall of the film layer with a lower oxygen content.

[0029] Optionally, Figure 2 The diagram shown is a schematic representation of a gate region according to an embodiment of this application. Figure 2 As shown, in the aluminum-containing film layer 61, the film layer 601 with a higher oxygen content is located on the side of the film layer 602 with a lower oxygen content away from the substrate 10. Specifically, before fabricating the gate contact layer 71, the upper surface of the aluminum-containing film layer 61 is oxidized to make the oxygen content of the upper surface of the aluminum-containing film layer 61 higher, so the film layer 601 with a higher oxygen content is located above the film layer 602 with a lower oxygen content; then the gate contact layer 71 is fabricated, and the desired result is obtained through a metal self-alignment process. Figure 2 The gate region is shown. Optionally, to avoid the oxidation process affecting the underlying semiconductor film, the thickness of the film layer 601 with a higher oxygen content is lower than the thickness of the film layer 602 with a lower oxygen content. For example, the thickness of the film layer 601 with a higher oxygen content ranges from 5 to 40 nm, and the thickness of the film layer 602 with a lower oxygen content ranges from 20 to 100 nm.

[0030] Optionally, Figure 3 The diagram shown is a schematic representation of another gate region provided in an embodiment of this application. Figure 3 As shown, in the aluminum-containing film layer 61, the film layer 601 with a higher oxygen content forms the sidewall of the film layer 602 with a lower oxygen content; that is, the film layer 602 with a lower oxygen content is surrounded by the film layer 601 with a higher oxygen content. Specifically, this is achieved through a metal self-alignment process... Figure 1 After the gate region shown, the sidewalls of the aluminum-containing film layer 61 are oxidized to obtain the final product as shown. Figure 3 The gate region is shown. Optionally, in the direction parallel to the plane of the substrate 10, the thickness of the film layer 601 with higher oxygen content near the drain region is greater than the thickness of the film layer 601 with higher oxygen content near the source region. This is because leakage current is prone to occur on the side of the gate region near the drain region. Appropriately increasing the thickness of the film layer 601 with higher oxygen content near the drain region can improve device reliability.

[0031] Specifically, the oxygen content of Al2O3 is greater than that of AlON, and the oxygen content of AlON is greater than that of AlN. Therefore, when AlN is used for the film layer 602 with a lower oxygen content, Al2O3 or AlON is used for the film layer 601 with a higher oxygen content; or, when AlON is used for the film layer 602 with a lower oxygen content, Al2O3 is used for the film layer 601 with a higher oxygen content. Optionally, when the aluminum-containing film layer 61 is a three-layer structure containing AlN, AlON, and Al2O3, AlN, AlON, and Al2O3 are arranged sequentially in the direction from the substrate 10 to the channel layer 20; or, in the plane of the substrate 10, AlN, AlON, and Al2O3 are arranged sequentially in the direction from the center point of the aluminum-containing film layer 61 to the side.

[0032] Optionally, Figure 4 The diagram shown is a schematic representation of another gate region provided in an embodiment of this application. Figure 4 As shown, in the aluminum-containing film layer 61, the film layer 601 with a higher oxygen content is located on the side of the film layer 602 with a lower oxygen content away from the substrate; and the film layer 601 with a higher oxygen content constitutes the sidewall of the film layer 602 with a lower oxygen content. Specifically, before fabricating the gate contact layer 71, the upper surface of the aluminum-containing film layer 61 is oxidized so that a portion of the film layer 601 with a higher oxygen content is located on top; then the gate contact layer 71 is fabricated, and the desired result is obtained through a metal self-alignment process. Figure 2 The gate region shown; then the sidewalls of the aluminum-containing film layer 61 are oxidized to finally obtain the following... Figure 4 The gate region shown.

[0033] In one embodiment, Figure 5 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 5 As shown, source region 40b includes a source N-type doped region 81, located between source contact layer 72 and channel layer 20; drain region 40c includes a drain N-type doped region 82, located between drain contact layer 73 and channel layer 20. Because gate region 40a improves breakdown resistance, gate region 40a has a relatively high resistance. Therefore, in source region 40b, the source N-type doped region 81 is located between source contact layer 72 and channel layer 20, forming an ohmic contact between source contact layer 72 and channel layer 20. This reduces the ohmic contact resistance between source contact layer 72 and channel layer 20. Similarly, the drain N-type doped region 82 in drain region 40c reduces the ohmic contact resistance between drain contact layer 73 and channel layer 20, thereby reducing the overall resistance of the semiconductor structure and improving its electrical performance.

[0034] In one embodiment, Figure 6The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 6 As shown, the source N-type doped region 81 and / or the drain N-type doped region 82 include a superlattice structure. Specifically, the superlattice structure can further reduce the resistance and increase the 2DEG concentration at the channel through the polarization effect, thereby increasing the 2DEG mobility. Optionally, the superlattice structure includes a stacked structure formed by periodically alternating GaN layers and AlGaN layers in a direction perpendicular to the plane of the substrate 10, or the superlattice structure includes a stacked structure formed by periodically alternating GaN layers and InGaN layers in a direction perpendicular to the plane of the substrate 10. Optionally, the source N-type doped region 81 and the drain N-type doped region 82 are heavily N-type doped with a doping concentration greater than 1E18 / cm³. 3 .

[0035] In one embodiment, the channel formed between the channel layer 20 and the barrier layer 30 extends away from the substrate 10, and the N-type doping concentration of the source N-type doped region 81 and / or the drain N-type doped region 82 gradually decreases. Specifically, the resistance between the channel formed between the channel layer 20 and the barrier layer 30 and the source N-type doped region 81 and the drain N-type doped region 82 significantly affects the on-resistance of the device. Therefore, increasing the N-type doping concentration of the source N-type doped region 81 and / or the drain N-type doped region 82 corresponding to the channel formed between the channel layer 20 and the barrier layer 30 reduces the overall on-resistance and improves device performance.

[0036] Furthermore, the channel formed between the channel layer 20 and the barrier layer 30 extends away from the substrate 10, and the N-type doping concentration of the source N-type doped region 81 and / or the drain N-type doped region 82 first decreases and then increases. Specifically, the resistance between the source contact layer 72 and the source N-type doped region 81, and the resistance between the drain contact layer 73 and the drain N-type doped region 82, are the second largest factors affecting the on-resistance of the device. Therefore, increasing the N-type doping concentration of the source N-type doped region 81 near the source contact layer 72, and increasing the N-type doping concentration of the drain N-type doped region 82 near the drain contact layer 73, can reduce the on-resistance of the device and improve its performance.

[0037] In one embodiment, Figure 7 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 7As shown, the semiconductor structure also includes an insulating protective layer 90 with an opening. The insulating protective layer 90 covers the gate contact layer 71, the source contact layer 72, the drain contact layer 73, and the barrier layer 30, and exposes the gate contact layer 71, the source contact layer 72, and the drain contact layer 73 at the opening 901. Specifically, the insulating protective layer 90 covers the upper surface of the semiconductor structure to protect its internal structure; the opening 901 is provided with a metal structure to provide electrical signals to the lower gate contact layer 71, the source contact layer 72, and the drain contact layer 73. Optionally, the material of the insulating protective layer 90 is selected from SiO2 or SiN.

[0038] In one embodiment, Figure 8 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 8 As shown, the semiconductor structure also includes a second P-type semiconductor layer 52 located on the side of the barrier layer 30 away from the substrate 10, between the gate region 40a and the drain region 40c. Specifically, the second P-type semiconductor layer 52 provides a gentle electric field distribution on the drain region 40c side, which can reduce current collapse.

[0039] Optionally, such as Figure 8 As shown, the insulating protective layer 90 also covers the second P-type semiconductor layer 52, protecting the second P-type semiconductor layer 52.

[0040] Optionally, such as Figure 8 As shown, in the direction perpendicular to the plane of the substrate 10, the thickness of the second P-type semiconductor layer 52 is less than the thickness of the first P-type semiconductor layer 51. The function of the second P-type semiconductor layer 52 is to reduce the 2DEG concentration of the channel below, rather than to achieve the normally off state.

[0041] Optionally, the P-type doping concentration of the second P-type semiconductor layer 52 is lower than that of the first P-type semiconductor layer 51. The function of the second P-type semiconductor layer 52 is to reduce the 2DEG concentration of the underlying channel, rather than to achieve a normally off state.

[0042] Optionally, the second P-type semiconductor layer 52 and the first P-type semiconductor layer 51 are made of the same material and are formed simultaneously, simplifying the manufacturing process.

[0043] In one embodiment, this application provides a method for fabricating a semiconductor structure. Figures 9 to 13 The diagram shown is an intermediate structure diagram for fabricating a semiconductor structure according to an embodiment of this application. The fabrication method includes the following steps:

[0044] Step S1, as follows Figure 9As shown, a channel layer 20 and a barrier layer 30 are epitaxially fabricated sequentially on a substrate 10. The channel layer 20 and the barrier layer 30 include a gate region 40a, and a source region 40b and a drain region 40c located on both sides of the gate region 40a. A P-type semiconductor material layer 50 is epitaxially fabricated on the side of the barrier layer 30 away from the substrate 10.

[0045] Specifically, the substrate 10 can be sapphire, Si, SiC, diamond, or GaN.

[0046] Specifically, the channel layer 20 and the barrier layer 30 form a heterojunction, and a 2DEG channel is formed on the surface of the channel layer 20 near the barrier layer 30. When no voltage is applied to the semiconductor device, the first P-type semiconductor layer 51 can deplete the 2DEG at the channel to realize an enhancement-mode device. Optionally, the channel layer 20 and the barrier layer 30 can be GaN-based semiconductor materials, with the channel layer 20 being GaN and the barrier layer 30 being AlGaN. The epitaxial process of the channel layer 20 and the barrier layer 30 is achieved through atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), physical vapor deposition (PVD), metal-organic molecular beam epitaxy (MOMBE), metal-organic chemical vapor deposition (MOCVD), or a combination thereof.

[0047] Specifically, the P-type semiconductor material layer 50 has undergone P-type activation treatment.

[0048] Step S2, as follows Figure 10 As shown, an aluminum-containing material layer 60 is deposited on the side of the P-type semiconductor material layer 50 away from the substrate 10. Specifically, the material of the aluminum-containing material layer 60 includes at least one of AlN, AlON, and Al2O3.

[0049] Step S3, as follows Figure 11As shown, the aluminum-containing material layer 60 and the P-type semiconductor material layer 5 are etched into the source region 40b and the drain region 40c.

[0050] Step S4, as follows Figure 12 As shown, a metallic material layer 70 is deposited. Specifically, the material of the metallic material layer 70 includes Ni and Au.

[0051] Step S5, as follows Figure 13 As shown, the metal material layer 70 located between the gate region 40a and the source region 40b, and the metal material layer 70 located between the gate region 40a and the drain region 40c are etched away to form a gate contact layer 71 located in the gate region 40a, a source contact layer 72 located in the source region 40b, and a drain contact layer 73 located in the drain region 40c.

[0052] Step S6, as follows Figure 1 As shown, using the gate contact layer 71, source contact layer 72, and drain contact layer 73 as masks, an aluminum-containing material layer 60 and a P-type semiconductor material layer 50 are etched to form a first P-type semiconductor layer 51 and an aluminum-containing film layer 61 located in the gate region 40a, such that the sidewalls of the first P-type semiconductor layer 51, the sidewalls of the aluminum-containing film layer 61, and the sidewalls of the gate contact layer 71 are aligned. Specifically, by using a metal self-alignment process, the sidewall-aligned first P-type semiconductor layer 51, aluminum-containing film layer 61, and gate contact layer 71 can be fabricated relatively easily, which can reduce the gate leakage current of the semiconductor device. Furthermore, the bandgap of the aluminum-containing film layer 61 is larger than the bandgap of the first P-type semiconductor layer 51, which can increase the Schottky barrier height between the gate contact layer 71 and the first P-type semiconductor layer 51, thereby increasing the breakdown voltage.

[0053] In one embodiment, when etching the aluminum-containing material layer 60 and the P-type semiconductor material layer 50, the etching direction is perpendicular to the plane of the substrate 10, such that the sidewalls of the first P-type semiconductor layer 51, the sidewalls of the aluminum-containing film layer 61, and the sidewalls of the gate contact layer 71 are all perpendicular to the plane of the substrate 10. Specifically, the etching angle is controlled so that the sidewalls of the above three are perpendicular to the plane of the substrate.

[0054] In one embodiment, Figures 14 to 19 The diagram shown is an intermediate structure diagram for fabricating another semiconductor structure according to an embodiment of this application. After depositing an aluminum-containing material layer 60 on the side of the P-type semiconductor material layer 50 away from the substrate 10, the fabrication method further includes:

[0055] Step S21, as follows Figure 14 As shown, a sacrificial layer 62 is deposited over an aluminum-containing material layer 60. Optionally, the material of the sacrificial layer 62 is SiO2.

[0056] Step S22, as follows Figure 15As shown, the sacrificial layer 62, the aluminum-containing material layer 60, the P-type semiconductor material layer 50, the barrier layer 30, and at least part of the channel layer 20 of the source region 40b and the drain region 40c are etched to form a groove 31 located in the source region 40b and the drain region 40c. Specifically, the groove 31 is formed by etching the etched sacrificial layer 62 as a mask.

[0057] Step S23, as Figure 16 As shown, using the sacrificial layer 62 as a mask, source N-type doped regions 81 and drain N-type doped regions 82 are epitaxially fabricated in the grooves 31 of the source region 40b and drain region 40c, respectively. It should be noted that in step S23, the area covered by the sacrificial layer 62 cannot be epitaxially formed into a semiconductor film; only N-type doped regions are formed in the grooves 31. Optionally, GaN-based material is epitaxially grown a second time in the grooves 31, followed by N-type doping to obtain source N-type doped regions 81 and drain N-type doped regions 82; alternatively, N-type in-situ doping is performed simultaneously with the second epitaxial growth of GaN-based material in the grooves 31 to form source N-type doped regions 81 and drain N-type doped regions 82.

[0058] Optionally, such as Figure 16 As shown, the source N-type doped region 81 and the drain N-type doped region 82 are epitaxially extended to be flush with the surface of the P-type semiconductor material layer 50.

[0059] Step S24, as Figure 17 As shown, the sacrificial layer 62 is removed by etching.

[0060] Step S25, as Figure 18 As shown, a metal material layer 70 is then deposited. Specifically, the material of the metal material layer 70 includes Ni and Au.

[0061] Step S26, as follows Figure 19 As shown, similar to step S5, the metal material layer 70 located between the gate region 40a and the source region 40b, and the metal material layer 70 located between the gate region 40a and the drain region 40c are etched away, so that the source N-type doped region 81 is located between the source contact layer 72 and the channel layer 20, and the drain N-type doped region 82 is located between the drain contact layer 73 and the channel layer 20.

[0062] Step S27, as follows Figure 5As shown, similar to step S6, using the gate contact layer 71, source contact layer 72, and drain contact layer 73 as masks, the aluminum-containing material layer 60 and the P-type semiconductor material layer 50 located between the gate region 40a and the source region 40b, and between the gate region 40a and the drain region 40c, are etched to form a sidewall-aligned first P-type semiconductor layer 51, an aluminum-containing film layer 61, and a gate contact layer 71. Because the gate region 40a improves the breakdown resistance, its resistance is relatively high. Specifically, the source N-type doped region 81 and the source contact layer 72 form an ohmic contact, which can reduce the ohmic contact resistance between the source contact layer 72 and the channel layer 20. The drain N-type doped region 82 can reduce the ohmic contact resistance between the drain contact layer 73 and the channel layer 20. This arrangement reduces the overall resistance of the semiconductor structure and improves its electrical performance.

[0063] In one embodiment, Figure 20 The diagram shown is a structural schematic of another intermediate structure provided in an embodiment of this application, as follows: Figure 20 As shown, the fabrication method further includes: depositing an insulating protective layer 90, the insulating protective layer 90 covering the gate contact layer 71, the source contact layer 72, the drain contact layer 73, and the barrier layer 30; as shown Figure 8 As shown, the insulating protective layer 90 is etched to form an opening 901 that exposes the gate contact layer 71, the source contact layer 72, and the drain contact layer 73. The opening 901 is used for subsequent metal interconnects.

[0064] This application provides a semiconductor structure and its fabrication method. The semiconductor structure includes a substrate, a channel layer, a barrier layer, and a first P-type semiconductor layer stacked sequentially. The channel layer and the barrier layer form a heterojunction. The first P-type semiconductor layer depletes the 2DEG at the channel to realize an enhancement-mode device. A first P-type semiconductor layer with sidewall alignment, an aluminum film layer, and a gate contact layer are sequentially disposed above the barrier layer in the gate region. This can reduce gate leakage current and increase the breakdown voltage by increasing the Schottky barrier height between the gate contact layer and the first P-type semiconductor layer. Meanwhile, the sidewall alignment is achieved through a relatively simple metal self-alignment process.

[0065] It should be understood that the term "comprising" and its variations as used in this application are open-ended, meaning "including but not limited to". The term "one embodiment" means "at least one embodiment". Specific features, structures, materials, or characteristics described in this specification may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

Claims

1. A semiconductor structure, characterized by, The application relates to a semiconductor device. The semiconductor device comprises a substrate, a channel layer and a barrier layer which are sequentially stacked, and the channel layer and the barrier layer comprise a gate region and a source region and a drain region located on both sides of the gate region. The gate region comprises a first P-type semiconductor layer, an aluminum-containing film layer and a gate contact layer which are sequentially stacked on the side of the barrier layer away from the substrate, and the side walls of the first P-type semiconductor layer, the side walls of the aluminum-containing film layer and the side walls of the gate contact layer are aligned; wherein the material of the aluminum-containing film layer at least comprises any one of AlN, AlON and Al2O3. The source region comprises a source contact layer located on the side of the channel layer away from the substrate. The drain region comprises a drain contact layer located on the side of the channel layer away from the substrate.

2. The semiconductor structure of claim 1, wherein, The side walls of the first P-type semiconductor layer, the side walls of the aluminum-containing film layer and the side walls of the gate contact layer are all perpendicular to the plane where the substrate is located.

3. The semiconductor structure of claim 1, wherein, The thickness of the aluminum-containing film layer is 2-10nm.

4. The semiconductor structure of claim 1, wherein, The aluminum-containing film layer is a multilayer structure composed of any two or three of AlN, AlON and Al2O3.

5. The semiconductor structure of claim 4, wherein, In the aluminum-containing film layer, the film layer with a higher oxygen component is located on the side of the film layer with a lower oxygen component away from the substrate; and / or The film layer with a higher oxygen component forms the side walls of the film layer with a lower oxygen component.

6. The semiconductor structure of claim 1, wherein, The source region comprises a source N-type doped region located between the source contact layer and the channel layer. The drain region comprises a drain N-type doped region located between the drain contact layer and the channel layer.

7. The semiconductor structure of claim 6, wherein, The source N-type doped region and / or the drain N-type doped region comprises a superlattice structure.

8. The semiconductor structure of claim 6, wherein, The N-type doped concentration of the source N-type doped region and / or the drain N-type doped region gradually decreases along the direction away from the substrate.

9. The semiconductor structure of claim 6, wherein, The N-type doped concentration of the source N-type doped region and / or the drain N-type doped region first decreases and then increases along the direction away from the substrate.

10. The semiconductor structure of claim 1, wherein, The semiconductor device further comprises an insulating protective layer with an opening, and the insulating protective layer covers the gate contact layer, the source contact layer, the drain contact layer and the barrier layer and exposes the gate contact layer, the source contact layer and the drain contact layer at the opening.

11. The semiconductor structure of claim 1, wherein, The semiconductor device further comprises: A second P-type semiconductor layer located on the side of the barrier layer away from the substrate, and the second P-type semiconductor layer is located between the gate region and the drain region.

12. A method of fabricating a semiconductor structure, the method comprising: The semiconductor device comprises a substrate, a channel layer and a barrier layer which are sequentially stacked on the substrate, and the channel layer and the barrier layer comprise a gate region and a source region and a drain region located on both sides of the gate region, and a P-type semiconductor material layer is epitaxially prepared on the side of the barrier layer away from the substrate. An aluminum-containing material layer is deposited on the side of the P-type semiconductor material layer away from the substrate; wherein the material of the aluminum-containing material layer at least comprises any one of AlN, AlON and Al2O3. ​ etching the aluminum-containing material layer and the P-type semiconductor material layer to form a first P-type semiconductor layer and an aluminum-containing film layer in the gate region, so that the sidewall of the first P-type semiconductor layer, the sidewall of the aluminum-containing film layer and the sidewall of the gate contact layer are aligned. After depositing the aluminum-containing material layer on the side of the P-type semiconductor material layer away from the substrate, the manufacturing method further comprises: depositing a sacrificial layer above the aluminum-containing material layer; 13. The method of manufacturing according to claim 12, wherein, etching the sacrificial layer, the aluminum-containing material layer, the P-type semiconductor material layer, the barrier layer and at least part of the channel layer in the source region and the drain region to form a recess in the source region and the drain region; using the sacrificial layer as a mask, epitaxially manufacturing a source N-type doped region and a drain N-type doped region in the recess of the source region and the drain region, respectively; etching to remove the sacrificial layer; re-depositing the metal material layer. When etching the aluminum-containing material layer and the P-type semiconductor material layer, the etching direction is perpendicular to the plane in which the substrate is located, so that the sidewall of the first P-type semiconductor layer, the sidewall of the aluminum-containing film layer and the sidewall of the gate contact layer are all perpendicular to the plane in which the substrate is located. Further comprising:

14. The method of manufacturing according to claim 12, wherein, depositing an insulating protective layer, the insulating protective layer covering the gate contact layer, the source contact layer, the drain contact layer and the barrier layer; 15. The method of manufacturing of claim 12, wherein, etching the insulating protective layer to form an opening exposing the gate contact layer, the source contact layer and the drain contact layer, the opening being used for subsequent metal interconnection. ​ ​

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