Semiconductor device

Abstract

The embodiment of the invention relates to a semiconductor device. Provided is a wide bandgap semiconductor device having high robustness to a dislocation between a gate electrode (trench) and a punch-through stop layer. A technical concept is that a planar shape of a punch-through stop layer is configured by a pattern having periodicity in each of an X direction and a Y direction that establish a plane, on the premise that grooves extending in the Y direction among the X direction and the Y direction are arranged at predetermined intervals in the X direction.

Description

[0001] Cross Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2024-081209 filed on May 17, 2024 including the specification, drawings and abstract is incorporated herein by reference in its entirety. BACKGROUND

[0003] The present application relates to a semiconductor device, and more particularly to a technology effective when applied to a semiconductor device using a wide bandgap semiconductor material having a larger bandgap than silicon.

[0004] The technology disclosed is listed as follows.

[0005] [Patent Literature 1] Japanese Unexamined Patent Application Publication No. 2019-117859

[0006] Patent Literature 1 discloses a technology for forming a semiconductor region of a conductive type opposite to that of a drift layer in a drift layer deeper than a trench. SUMMARY

[0007] There is a semiconductor device that uses a wide bandgap semiconductor material having a larger bandgap than silicon in an epitaxial layer. In such a wide bandgap semiconductor device, even if the thickness of the epitaxial layer is reduced, the large bandgap allows a high breakdown voltage of the epitaxial layer. That is, the wide bandgap semiconductor device can achieve both a reduction in on-resistance and an increase in breakdown voltage, which are in a trade-off relationship with each other.

[0008] Therefore, the wide bandgap semiconductor device can achieve a higher operating voltage. However, for example, in a wide bandgap semiconductor device including a field effect transistor having a gate electrode filled into a trench formed in an epitaxial layer via a gate insulating film, the electric field intensity near the corner portion of the trench bottom increases as the operating voltage is increased. As a result, there is a risk of dielectric breakdown occurring in the gate insulating film formed in the trench.

[0009] For this reason, in a wide bandgap semiconductor device, it is necessary to suppress the electric field concentration near the trench bottom. Therefore, it has been considered to form a punch-through stopper layer of a conductive type opposite to that of the epitaxial layer in the epitaxial layer deeper than the trench.

[0010] In this regard, the present inventors have newly found that misalignment between the gate electrode formed in the trench and the punch-through stopper layer formed in the epitaxial layer is a factor causing a change in characteristics of the wide bandgap semiconductor device.

[0011] To this end, there is a demand for a semiconductor device having high robustness against misalignment between a gate electrode and a punchthrough stop layer.

[0012] Other objects and novel features will become apparent from the description and drawings.

[0013] According to one embodiment, a semiconductor device includes a punchthrough stop layer, wherein a planar shape of the punchthrough stop layer is configured by a pattern having periodicity in each of an X direction and a Y direction constituting a plane, with the proviso that trenches extending in the Y direction among the X direction and the Y direction constituting the plane are arranged at a predetermined interval in the X direction.

[0014] According to one embodiment, it is possible to provide a wide bandgap semiconductor device having high robustness against misalignment between a gate electrode (trench) and a punchthrough stop layer. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a diagram illustrating a configuration of a wide bandgap semiconductor device including a MOSFET having a trench gate structure.

[0016] Figure 2 is a diagram illustrating an example of forming a punchthrough stop layer.

[0017] Figure 3 is a diagram illustrating an example of forming a punchthrough stop layer.

[0018] Figure 4 is a diagram illustrating a planar positional relationship between a trench and a punchthrough stop layer in related art.

[0019] Figure 5 is a diagram illustrating one shot in photolithography for forming a trench and a punchthrough stop layer.

[0020] Figure 6 is a diagram for calculating δθ.

[0021] Figure 7 is a diagram illustrating a semiconductor chip in a first embodiment.

[0022] Figure 8 is an enlarged view of a unit block.

[0023] Figure 9 is a diagram illustrating an example in which a relative misalignment δY occurs in the Y direction between a trench and a punchthrough stop layer.

[0024] Figure 10 is a diagram illustrating an example in which a relative misalignment δX occurs in the X direction between a trench and a punchthrough stop layer.

[0025] Figure 11This is a diagram illustrating a first modification of the first embodiment.

[0026] Figure 12 This is a diagram illustrating a second modification of the first embodiment.

[0027] Figure 13 This is a diagram illustrating the region of interest in a cell block in the second embodiment.

[0028] Figure 14 This is a diagram showing the configuration of pattern A.

[0029] Figure 15 This is a diagram showing the configuration of pattern B.

[0030] Figure 16 This is a diagram used to illustrate the third embodiment.

[0031] Figure 17 This is a diagram illustrating the process for implementing configuration A of the third embodiment.

[0032] Figure 18 It shows the continuation Figure 17 The diagram shows the subsequent process.

[0033] Figure 19 It shows the continuation Figure 18 The diagram shows the subsequent process.

[0034] Figure 20 It shows the continuation Figure 19 The diagram shows the subsequent process.

[0035] Figure 21 This is a diagram illustrating the process for implementing configuration B of the third embodiment.

[0036] Figure 22 It shows the continuation Figure 21 The diagram shows the subsequent process.

[0037] Figure 23 This is a diagram illustrating the process for implementing configuration C of the third embodiment.

[0038] Figure 24 It shows the continuation Figure 23 The diagram shows the subsequent process.

[0039] Figure 25 It shows the continuation Figure 24 The diagram shows the subsequent process.

[0040] Figure 26 This is a diagram illustrating the process for implementing configuration D of the third embodiment.

[0041] Figure 27 It shows the continuation Figure 26 The diagram shows the subsequent process.

[0042] Figure 28 is a view showing a process subsequent to Figure 27

[0043] Figure 29 is a view showing a process subsequent to Figure 28 DETAILED DESCRIPTION

[0044] In all the drawings used to describe the embodiments, the same components are generally given the same reference numerals, and repeated explanation thereof will be omitted. In order to make the drawings clear, hatching can be applied even in plan views.

[0045] Semiconductor devices having an epitaxial layer made mainly of a wide bandgap semiconductor material having a bandgap larger than that of silicon (hereinafter referred to as wide bandgap semiconductor devices) have been attracting attention. This is because a large bandgap indicates a high dielectric breakdown strength, more easily promoting achievement of a high breakdown voltage.

[0046] Further, if the semiconductor material itself has a high dielectric breakdown strength, even if an epitaxial layer (also referred to as a drift layer) that maintains a breakdown voltage is thinned, the breakdown voltage can be ensured. Therefore, for example, by thinning the epitaxial layer and increasing the impurity concentration, the on-resistance of the wide bandgap semiconductor device can be reduced.

[0047] That is, the wide bandgap semiconductor device has the advantage that both the increase in the breakdown voltage and the reduction in the on-resistance, which are in a trade-off relationship with each other, can be achieved. Therefore, the wide bandgap semiconductor device is expected to be a promising semiconductor device that can achieve high performance.

[0048] Examples of the semiconductor material having a bandgap larger than that of silicon include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond, and the like. The following description focuses on silicon carbide.

[0049] <Considered Background>

[0050] <<Usefulness of Punch-Through Stopper Layer>>

[0051] For example, the wide bandgap semiconductor device includes a field effect transistor (hereinafter sometimes referred to as MOSFET) having a trench gate structure in which a gate electrode is filled into a trench formed in an epitaxial layer on a semiconductor substrate via a gate insulating film.

[0052] Figure 1 is a view showing a configuration of a wide bandgap semiconductor device 100 including a MOSFET having a trench gate structure. As shown in FIG. 1, the wide bandgap semiconductor device 100 includes a semiconductor substrate 101, a gate insulating film 102, a gate electrode 103, a trench 104, a drift layer 105, a punch-through stopper layer 106, and a source electrode 107. Figure 1 ​​As shown, the wide bandgap semiconductor device 100 includes a drain electrode DE, a semiconductor substrate SUB, an epitaxial layer EPI, a trench TR, a gate insulating film GOX, a gate electrode GE, a source region SR, a body contact region BC, a channel layer CH, an insulating layer IL, a source electrode SE, and a surface protective film PAS.

[0053] The semiconductor substrate SUB, the epitaxial layer EPI, and the source region SR are composed of an n-type semiconductor region. Further, the body contact region BC and the channel layer CH are composed of a p-type semiconductor region.

[0054] To turn on the MOSFET, a gate voltage equal to or higher than a threshold voltage is applied to the gate electrode GE. As a result, a channel composed of an inversion layer (n-type semiconductor region) is formed in the channel layer CH in contact with the side surface of the trench TR. Thus, a current flows along a path from the drain electrode DE, the semiconductor substrate SUB, the epitaxial layer EPI, the channel (inversion layer), the source region SR, to the source electrode SE. The MOSFET is turned on in this way.

[0055] To turn off the MOSFET, a gate voltage lower than the threshold voltage is applied to the gate electrode GE. As a result, the channel composed of the inversion layer formed in the channel layer CH in contact with the side surface of the trench TR disappears. Thus, the current path between the drain electrode DE and the source electrode SE is cut off. The MOSFET is turned off in this way.

[0056] When the MOSFET is in an off state, for example, "0 V" is applied to the source electrode SE, the source region SR, the body contact region BC, and the channel layer CH. On the other hand, a positive potential (hundreds of V to thousands of V) is applied to the drain electrode DE, the semiconductor substrate SUB, and the epitaxial layer EPI. As a result, a reverse bias is applied to a pn junction between the channel layer CH (p-type semiconductor region) and the epitaxial layer EPI (n-type semiconductor region). For this reason, a depletion layer extends from the pn junction to the channel layer CH, and from the pn junction to the epitaxial layer EPI. In the depletion layer, an electric field is generated in response to a source-drain voltage applied between the source electrode SE and the drain electrode DE. Specifically, in the wide bandgap semiconductor device 100, the source-drain voltage becomes high. This increases the electric field strength in the depletion layer. Thus, for example, in the depletion layer extending in the epitaxial layer EPI, the electric field strength increases near the bottom of the trench TR. This can cause dielectric breakdown of the gate insulating film GOX formed in the trench TR. Figure 1 In the depletion layer extending in the epitaxial layer EPI, near the bottom of the trench TR, the electric field strength increases. This can cause dielectric breakdown of the gate insulating film GOX formed in the trench TR.

[0057] Thus, to suppress the electric field concentration near the bottom of the trench TR, it has been considered to form a punchthrough stop layer (p-type semiconductor region) of a conductivity type opposite to that of the epitaxial layer EPI in the epitaxial layer EPI deeper than the trench TR.

[0058] In this case, in the region where the punch-through stopper layer is disposed, the voltage applied to the drain is mainly applied to the pn junction formed by the punch-through stopper layer and the epitaxial layer EPI, and thus, in the pn junction formed by the channel layer CH above and the epitaxial layer EPI, depletion is suppressed. Similarly, the electric field rise at the bottom of the trench TR is also suppressed. Thus, by forming the punch-through stopper layer in the epitaxial layer EPI, dielectric breakdown of the gate insulating film GOX formed in the trench TR is suppressed.

[0059] Figure 2 is a diagram showing an example of forming a punch-through stopper layer PTS1.

[0060] In Figure 2 , the punch-through stopper layer PTS1 is formed in the epitaxial layer EPI below the trench TR. In this case, the rise in the electric field intensity near the bottom of the trench TR can be effectively suppressed. On the other hand, if the punch-through stopper layer PTS1 is formed at the position shown in Figure 2 , the current path of the MOSFET is blocked. Thus, when the punch-through stopper layer PTS1 is formed in the epitaxial layer EPI below the trench TR, the electric field concentration near the bottom of the trench TR can be efficiently alleviated, while the on-resistance of the MOSFET increases.

[0061] Figure 3 is a diagram showing an example of forming a punch-through stopper layer PTS2.

[0062] In Figure 3 , the punch-through stopper layer PTS2 is formed in the epitaxial layer EPI away from below the trench TR. In other words, in a cross-sectional view, the punch-through stopper layer PTS2 is formed at a position that does not overlap the trench TR. In this case, since the punch-through stopper layer PTS2 is unlikely to block the current path of the MOSFET, the increase in the on-resistance of the MOSFET caused by providing the punch-through stopper layer PTS2 can be suppressed. On the other hand, the effect of suppressing the rise in the electric field intensity near the bottom of the trench TR is smaller than that of the punch-through stopper layer PTS1 shown in Figure 2 .

[0063] Thus, the following prior art regarding the punch-through stopper layer is under consideration.

[0064] <<Description of Related Art>>

[0065] In this specification, the term "related art" refers to a technology that has not been disclosed yet, but relates to a problem identified by the inventors, and serves as a premise for the present disclosure.

[0066] Figure 4is a view showing a planar positional relationship between a trench TR and a punchthrough stop layer in the related art. In Figure 4 In the related art, the punchthrough stop layer is configured by a punchthrough stop layer PTS1 shown in Figure 2 and a punchthrough stop layer PTS2 shown in Figure 3 . That is, an A-A cross section of Figure 4 corresponds to Figure 2 , and a B-B cross section of Figure 4 corresponds to Figure 3 . Thus, the related art includes the punchthrough stop layer PTS1 and the punchthrough stop layer PTS2. The punchthrough stop layer PTS1 is formed under the trench TR. Further, in a plan view, the punchthrough stop layer PTS2 is formed at a position not overlapping the trench TR.

[0067] According to the prior art, the configuration more reduces an on-resistance of the MOSFET than when the entire punchthrough stop layer is formed by the punchthrough stop layer PTS1. In addition, according to the prior art, the configuration more efficiently alleviates an electric field concentration near a bottom of the trench TR than when the entire punchthrough stop layer is formed by the punchthrough stop layer PTS2.

[0068] Thus, the prior art can achieve both alleviation of the electric field concentration near the bottom of the trench TR and reduction of the on-resistance of the MOSFET.

[0069] <<Considerations for improvement of the prior art>>

[0070] However, the inventors have newly found that a misalignment between a gate electrode formed in a trench and a punchthrough stop layer formed in an epitaxial layer is a factor that causes a change in characteristics of a wide bandgap semiconductor device.

[0071] For example, in Figure 4 , if formation positions of the punchthrough stop layer PTS1 and the punchthrough stop layer PTS2 are misaligned in an X direction, a relative positional relationship between the trench TR and the punchthrough stop layer PTS1 and a relative positional relationship between the trench TR and the punchthrough stop layer PTS2 change. As a result, a change in characteristics of the wide bandgap semiconductor device occurs. That is, the prior art has room for improvement in ensuring robustness to a misalignment between a gate electrode formed in a trench and a punchthrough stop layer formed in an epitaxial layer. Thus, there is a demand for a wide bandgap semiconductor device having high robustness to a misalignment between a gate electrode (trench) and a punchthrough stop layer. In other words, there is a demand for a technical concept for overcoming the room for improvement existing in the prior art.

[0072] <Components of the misalignment>

[0073] First, a description will be given of components of misregistration to be considered as misregistration between the trench and the punchthrough stopper layer before a technical concept is described.

[0074] For example, when the XY plane is considered, independent components of misregistration between the trench and the punchthrough stopper layer are misregistration δX in the X direction, misregistration δY in the Y direction, and misregistration δθ in the θ direction. Therefore, in order to realize a wide bandgap semiconductor device having high robustness against misregistration between the trench and the punchthrough stopper layer, it is essential to find a planar shape of the punchthrough stopper layer that can reduce changes in relative positional relationship between the trench and the punchthrough stopper layer caused by δX, δY, and δθ.

[0075] In this regard, a description will be given of δθ that can be ignored.

[0076] Figure 5 is a diagram showing one exposure ST in photolithography for forming a trench and a punchthrough stopper layer. In Figure 5 , the size of the exposure region, one exposure ST is, for example, 1000 μm x 1000 μm. The exposure region includes an alignment mark AM1 and an alignment mark AM2. The alignment mark AM1 and the alignment mark AM2 are used to align the trench and the punchthrough stopper layer. Misregistration between the alignment mark AM1 and the alignment mark AM2 generates δX, δY, and δθ. An estimate of δθ is provided below.

[0077] Figure 6 is a diagram used to calculate δθ. As Figure 6 indicated, the position coordinates of the alignment mark AM1 and the position coordinates of the alignment mark AM2 are defined. In this case, θ1 is represented by the following Equation 1. Further, θ2 is represented by the following Equation 2.

[0078] [Equation 1]

[0079]

[0080] [Equation 2]

[0081]

[0082] Here, δθ = θ2 - θ1. For example, assuming that the size of one exposure is 1000 μm x 1000 μm, δθ < 0.001° is obtained, indicating that δθ is a very small value. From this, δθ can be ignored.

[0083] As described above, in consideration of the XY plane, the independent components of the misalignment between the trench and the punchthrough stop layer that cannot be ignored are δX and δY. Accordingly, δθ can be ignored, and thus, in order to realize a wide bandgap semiconductor device that is highly robust against misalignment between the trench and the punchthrough stop layer, it is sufficient to find a planar shape of the punchthrough stop layer that reduces the change in the relative positional relationship between the trench and the punchthrough stop layer caused by δX and δY.

[0084] Therefore, in the following, a technical concept regarding the planar shape of the punchthrough stop layer will be described that is capable of reducing the change in the relative positional relationship between the trench and the punchthrough stop layer caused by δX and δY.

[0085] <Basic Concept>

[0086] The basic concept is that the planar shape of the punchthrough stop layer is configured from a pattern that has periodicity in each of the X direction and the Y direction of the established plane, on the premise that the trench extending in the Y direction of the established plane is arranged at a predetermined interval in the X direction. Therefore, even if relative misalignment occurs between the trench and the punchthrough stop layer, the change in the relative positional relationship between the trench and the punchthrough stop layer caused by the misalignment can be reduced from the entire chip. As a result, according to the basic concept, the change in the characteristics of the wide bandgap semiconductor device can be suppressed. That is, according to the basic concept, a wide bandgap semiconductor device that is highly robust against misalignment between the trench and the punchthrough stop layer can be provided.

[0087] For example, the punchthrough stop layer is divided into a plurality of portions in the plan view. Each of the plurality of portions is the same size as the other portions. There are portions that are adjacent to each other within the plurality of portions. The basic concept is that a first pattern is formed in each of the adjacent portions, where the planar shape of each of the adjacent portions is the same as each other. The first pattern is formed from one or more sub-patterns. Here, in the plan view, each of the one or more sub-patterns that form the first pattern partially overlaps any of the plurality of gate electrodes (the plurality of trenches).

[0088] Therefore, on the premise that the trench and the punchthrough stop layer have portions that overlap in the plan view, the planar shape of the punchthrough stop layer is configured from a pattern that has periodicity in each of the X direction and the Y direction of the established plane.

[0089] For example, the planar shape of the punchthrough stop layer forms a geometric pattern that includes the above-described first pattern as a repetition of a unit pattern.

[0090] In the present specification, the term "geometric pattern" is defined as a certain type of pattern, and specifically has the following meanings. Specifically, "geometric pattern" refers to a pattern created by combining and arranging simple figures as components, such as polygons (e.g., triangles, squares, and hexagons), circles, ellipses, and straight lines, which geometric components are subjected to operations such as translation, inversion, and rotation. "Geometric pattern" allows infinite pattern expansion through repetition of the same operation. In addition, "geometric pattern" can also be described as a figure generated by a geometric curve that can be expressed using a periodic function.

[0091] In view of the above, the first pattern is configured by one or more sub-patterns including any of a straight line, a rectangle, a circle, and a curve. Specifically, the first pattern is configured by a pattern capable of tessellating a plane. Here, the "pattern capable of tessellating a plane" mentioned in the present specification is a pattern using a finite number of plane figures in which adjacent plane figures do not overlap and adjacent plane figures can fill a plane without gaps. It should be noted that this does not exclude providing openings inside the plane figures.

[0092] For example, the first pattern is configured by a pattern capable of tessellating a plane. In this case, the first pattern is configured by a plurality of sub-patterns, and the plurality of sub-patterns is configured by a combination of a plurality of single figures. In this case, the single figure is a triangle, a square, or a hexagon. In addition, the first pattern can also be configured by a pattern capable of tessellating a plane using a combination of a plurality of types of figures, instead of the above-described combination of a plurality of single figures. Specifically, the first pattern is configured by a plurality of sub-patterns, and the plurality of sub-patterns is configured by a combination of a plurality of types of figures.

[0093] The basic concept is based on the premise that trenches extending in the Y direction among the X and Y directions that establish a plane are arranged at a predetermined interval in the X direction. In addition, the basic concept is based on the premise that the trenches and the penetration stop layer have portions that partially overlap each other in a plan view. As a specific example of the premise condition, the following configuration can be given. That is, each of the plurality of gate electrodes extends along a first direction (Y direction), and in a plan view, each of the one or more sub-patterns of the first pattern extends along a second direction (X direction) that intersects the first direction. This satisfies the premise condition.

[0094] In the penetration stop layer, each of the first and second portions of the penetration stop layer not only has the first pattern but also can have a second pattern having a ring shape that encloses the first pattern in a plan view. The first pattern is connected to the second pattern, for example. The second pattern is supplied with a ground potential. Thus, the configuration of the penetration stop layer in the basic concept includes an aspect in which a ground potential is supplied.

[0095] Hereinafter, a first embodiment will be described below as an example embodying the basic concept.

[0096] <First Embodiment>

[0097] <Configuration of Wide Bandgap Semiconductor Device>

[0098] Figure 7 is a view showing a semiconductor chip CHP in the first embodiment.

[0099] In Figure 7 , the semiconductor chip CHP includes an active region ACT, a floating ring FR1, and a floating ring FR2. The active region ACT is a region formed with semiconductor elements such as MOSFETs. The floating ring FR1 is formed so as to surround the active region ACT in a plan view. In addition, the floating ring FR2 is formed so as to surround the floating ring FR1 in a plan view. The floating ring FR1 and the floating ring FR2 are provided to secure an insulation breakdown voltage of the semiconductor chip CHP.

[0100] The active region ACT includes a plurality of trenches TR. Each of the plurality of trenches TR extends in the Y direction. The plurality of trenches TR is formed so as to be aligned at a predetermined interval in the X direction. In the first embodiment, the active region ACT has a plurality of cell blocks CB. For example, as shown in Figure 7 , the plurality of cell blocks CB includes a cell block CB1 and a cell block CB2 adjacent to each other. The cell block CB1 is a region formed with a first portion of a punchthrough stop layer. In addition, the cell block CB2 is a region formed with a second portion of the punchthrough stop layer.

[0101] The cell block CB1 and the cell block CB2 have the same size. The first pattern is formed in the cell block CB1 and the cell block CB2 adjacent to each other, the first pattern having the same planar shape. The configuration of the cell block CB formed with the first pattern will be described below.

[0102] Figure 8 is an enlarged view of the cell block CB. In Figure 8 , the cell block CB includes a trench TR, a pattern PTN1, and a pattern PTN2.

[0103] The trench TR extends in the Y direction and is arranged so as to be aligned at a predetermined interval in the X direction. Figure 8 Four trenches TR aligned at a predetermined interval in the X direction are shown.

[0104] The pattern PTN1 is configured by one or a plurality of sub-patterns. For example, in Figure 8 , the pattern PTN1 is configured by a sub-pattern SPN1, a sub-pattern SPN2, a sub-pattern SPN3, a sub-pattern SPN4, and a sub-pattern SPN5. That is,Figure 8 The pattern PTN1 shown is configured with five sub-patterns. Each of sub-patterns SPN1, SPN2, SPN3, SPN4, and SPN5 is a pattern of the pass-through blocking layer PTS. Therefore, pattern PTN1 configures a combination of patterns of the pass-through blocking layer PTS. For example, in Figure 8 In the pattern PTN1, five sub-patterns are configured, and each of these five sub-patterns is configured with a diagonal line.

[0105] Each of the sub-patterns SPN1, SPN2, SPN3, SPN4, and SPN5 of the configuration pattern PTN1 is associated with a plurality of trenches TR. Figure 8 Each of the four trenches (TR) partially overlaps. In other words, when considering the gate electrodes formed within the trenches TR, each of the sub-patterns SPN1, SPN2, SPN3, SPN4, and SPN5 overlaps with multiple gate electrodes ( Figure 8 Any of the four gate electrodes (in the middle) partially overlaps. Specifically, in Figure 8 In the diagram, each of the multiple trenches TR (multiple gate electrodes) extends along the Y direction, and in the plan view, each of the five sub-patterns of the configuration pattern PTN1 extends along the X direction, which intersects the Y direction.

[0106] Pattern PTN2 has an annulus surrounding pattern PTN1 in a planar view. That is, pattern PTN2 has an annulus surrounding five sub-patterns of pattern PTN1 in a planar view. Pattern PTN2 is connected to pattern PN1. In other words, the planar shape of the through-stop layer PTS is configured by a combination of pattern PTN1, which includes five sub-patterns, and pattern PTN2, which has an annulus surrounding pattern PTN1 in a planar view.

[0107] Figure 8 The cross-sectional view along line AA in the middle and Figure 2 They are basically the same. Also, Figure 8 The cross-sectional view along line BB in the middle and Figure 3 They are basically the same. It should be noted that... Figure 2 The punch-through blocking layer PTS1 in the middle corresponds to Figure 8 The through-hole blocking layer PTS is shown in the cross-sectional view along line AA. Additionally, Figure 3 The punch-through blocking layer PTS2 in the middle corresponds to Figure 8 The through-stop layer PTS in the cross-sectional view of BB along the line.

[0108] The wide-bandgap semiconductor device in the first embodiment includes a drain electrode DE, a semiconductor substrate SUB, an epitaxial layer EPI, a trench TR, a gate insulating film GOX, a gate electrode GE, a source region SR, a body contact region BC, a channel layer CH, a punchthrough stop layer PTS, an insulating layer IL, a source electrode SE, and a surface protective film PAS.

[0109] The semiconductor substrate SUB is made of, for example, silicon carbide doped with an n-type impurity (donor). The drain electrode DE is formed on a lower surface of the semiconductor substrate SUB. Further, the epitaxial layer EPI is formed on an upper surface of the semiconductor substrate SUB. The epitaxial layer EPI is an n-type semiconductor layer made of silicon carbide.

[0110] The channel layer CH is a p-type semiconductor layer formed in the epitaxial layer EPI. The trench TR is formed so as to penetrate the channel layer CH and reach an inside of the epitaxial layer EPI. The gate insulating film GOX is formed on an inner wall of the trench TR. The gate electrode GE is filled in the trench TR via the gate insulating film GOX.

[0111] The punchthrough stop layer PTS is formed in the epitaxial layer EPI. The punchthrough stop layer PTS is a p-type semiconductor layer formed at a position deeper than the trench TR. The source region SR is an n-type semiconductor region formed in the channel layer CH. The source region SR is in contact with the trench TR. In addition, the body contact region BC is a p-type semiconductor region formed in the channel layer CH. An impurity concentration of the body contact region BC is higher than an impurity concentration of the channel layer CH.

[0112] The source electrode SE is formed on the insulating layer IL and in a contact hole that penetrates the insulating layer IL. The source electrode SE is electrically connected to the source region SR and the body contact region BC. Thus, the source region SR and the body contact region BC are electrically connected to each other via the source electrode SE. The surface protective film PAS is formed on the source electrode SE. The wide-bandgap semiconductor device according to the first embodiment is configured as described above.

[0113] <<Features of the First Embodiment>>

[0114] Next, features of the first embodiment will be described.

[0115] The features of the first embodiment are based on a premise that, as shown in FIG. 7, for example, the plurality of cell blocks CB have the same size in a plan view. In addition, the features are based on a premise that the pattern PTN1 is formed in each of the plurality of cell blocks CB having the same planar shape. Under such premises, for example, as shown in FIG. 8, the pattern PTN1 is configured by a plurality of sub-patterns. In Figure 8 Figure 8 ​In the process, multiple sub-patterns include sub-patterns SPN1, SPN2, SPN3, SPN4, and SPN5. Furthermore, each of the multiple sub-patterns configuring pattern PTN1 partially overlaps with any trench in the multiple trenches TR in the planar view. Therefore, the characteristic is that the planar shape of the through-stop layer PTS is configured with pattern PTN1 having the above-described configuration.

[0116] As a result, according to the first embodiment, assuming that the trench TR and the punch-through stop layer PTS partially overlap in a planar view, the planar shape of the punch-through stop layer PTS can be configured by a pattern having periodicity in each of the X and Y directions of the established plane. As a result, according to the first embodiment, even if a relative misalignment (δX or δY) occurs between the trench TR and the punch-through stop layer PTS, the change in the relative positional relationship between the trench TR and the punch-through stop layer PTS caused by the misalignment can be reduced when viewed over the entire chip. As a result, based on these features, variations in the characteristics of the wide bandgap semiconductor device can be suppressed. That is, based on these features, a wide bandgap semiconductor device with high robustness to misalignment between the trench TR and the punch-through stop layer PTS can be provided.

[0117] Details will be described below.

[0118] exist Figure 8 In this case, there is no relative misalignment between the trench (TR) and the penetration-stop layer (PTS). Figure 8 In the unit block CB, there exists a section with section AA ( Figure 2 The portion corresponding to the positional relationship between the trench TR and the penetration barrier layer PTS shown in the figure. Figure 8 It also shows the BB section ( Figure 3 The portion corresponding to the positional relationship between the trench TR and the penetration barrier layer PTS shown in the figure.

[0119] Figure 9 This is a diagram illustrating an example of a relative misalignment δY in the Y direction between the trench TR and the through-stop layer PTS. Additionally, in Figure 9 In the unit block CB, there exists a section with section AA ( Figure 2 The portion corresponding to the positional relationship between the trench TR and the penetration barrier layer PTS shown in the figure. Figure 9 It also shows the BB section ( Figure 3 The portion corresponding to the positional relationship between the trench TR and the penetration barrier layer PTS shown in the figure.

[0120] Figure 10 This is a diagram illustrating an example where a relative misalignment δX occurs in the X direction between the trench TR and the through-stop layer PTS. Similarly, in Figure 10In the unit block CB, there exists a section with section AA ( Figure 2 The portion corresponding to the positional relationship between the trench TR and the penetration barrier layer PTS shown in the figure. Figure 10 It also shows the BB section ( Figure 3 The portion corresponding to the positional relationship between the trench TR and the penetration barrier layer PTS shown in the figure.

[0121] consider Figure 8 , Figure 9 and Figure 10 Even if a relative misalignment (δX or δY) occurs between the trench TR and the through-stop layer PTS, within the element block CB, there exists a cross section AA ( Figure 2 The position corresponding to the positional relationship between the trench TR and the penetration barrier layer PTS shown in the figure, and the position corresponding to the BB section ( Figure 3 The portion corresponding to the positional relationship between the trench TR and the punch-through stop layer PTS shown in the diagram. This means that, when viewed across the entire chip, changes in the relative positional relationship between the trench TR and the punch-through stop layer PTS caused by misalignment can be reduced. Therefore, according to the first embodiment, changes in the characteristics of the wide bandgap semiconductor device can be suppressed. That is, according to the first embodiment, a wide bandgap semiconductor device with high robustness to misalignment between the trench TR and the punch-through stop layer PTS can be provided.

[0122] <<First Modification of the First Embodiment>>

[0123] Figure 11 This is a diagram illustrating a first modification of the first embodiment.

[0124] exist Figure 11 In the first modification, the planar shape of the through-blocking layer PTS is configured with pattern PTN1. In the first modification, pattern PTN1 is configured with sub-patterns SPN1, SPN2, SPN3, SPN4, SPN5, SPN6, SPN7, SPN8, SPN9 and SPN10.

[0125] In the first modification configured in this way, based on the premise that the trench TR and the punch-through stop layer PTS partially overlap in a planar view, the planar shape of the punch-through stop layer PTS can be configured by a periodic pattern in each of the X and Y directions of the established plane. As a result, in the first modification, even if a relative misalignment (δX or δY) occurs between the trench TR and the punch-through stop layer PTS, the change in the relative positional relationship between the trench TR and the punch-through stop layer PTS caused by the misalignment can be reduced when viewed over the entire chip. Consequently, according to the first modification, changes in the characteristics of the wide bandgap semiconductor device can also be suppressed. That is, according to the first modification, a wide bandgap semiconductor device with high robustness to misalignment between the trench TR and the punch-through stop layer PTS can be provided.

[0126] <<Second Modification of the First Embodiment>>

[0127] Figure 12 This is a diagram illustrating a second modification of the first embodiment.

[0128] exist Figure 12 In the first modification, the first pattern PTN1 is configured with a planar shape of the through-blocking layer PTS. In the second modification, the first pattern PTN1 is configured with multiple sub-patterns SPN, and the multiple sub-patterns are configured as a combination of multiple single graphics. That is, the sub-patterns SPN have a hexagonal shape (single graphic), and the multiple sub-patterns SPN are configured as "patterns capable of tessell planarization".

[0129] In the second modification configured in this manner, assuming that the trench TR and the punch-through stop layer PTS partially overlap in a planar view, the planar shape of the punch-through stop layer PTS can be configured by a periodic pattern in each of the X and Y directions of the established plane. Therefore, in the second modification, even if a relative misalignment (δX or δY) occurs between the trench TR and the punch-through stop layer PTS, the change in the relative positional relationship between the trench TR and the punch-through stop layer PTS caused by the misalignment can be reduced from the perspective of the entire chip. As a result, according to the second modification, the variation in the characteristics of the wide bandgap semiconductor device can also be suppressed. In other words, according to the second modification, a wide bandgap semiconductor device with high robustness to misalignment between the trench TR and the punch-through stop layer PTS can be provided.

[0130] <Second Embodiment>

[0131] Figure 13 This is a diagram illustrating the region of interest RA in the outermost unit block CB of the second embodiment. In the second embodiment, the configuration of the pattern PTN2 in region RA will be described. The configuration of pattern PTN2 can be either configuration A or configuration B shown below.

[0132] Configuration A of the second embodiment

[0133] Figure 14 is a view showing Configuration A of the pattern PTN2. As shown in Figure 14 , in Configuration A, the offset OS is provided between the center line CL in the Y direction of the pattern PTN2 extending in the X direction and the trench TR. As a result, according to Configuration A, sufficient margin can be ensured against misalignment ±δY in the Y direction between the trench TR and the pattern PTN2 (punch-through stop layer).

[0134] Configuration B of the second embodiment

[0135] Figure 15 is a view showing Configuration B of the pattern PTN2. As shown in Figure 15 , in Configuration B, the offset OS is not provided between the center line CL in the Y direction of the pattern PTN2 extending in the X direction and the trench TR. This allows the chip size to be reduced.

[0136] Third embodiment

[0137] For example, in the related art shown in Figure 4 , the potential of the punch-through stop layer PTS1 and the potential of the punch-through stop layer PTS2 are set to floating potentials. In this case, when the MOSFET is repeatedly switched, a temporary potential shift occurs due to accumulation of holes, particularly, in the punch-through stop layer PTS1. As a result, the dynamic characteristics of the wide bandgap semiconductor device including the MOSFET are adversely affected.

[0138] To cope with this situation, it is conceivable to fix the potential of the punch-through stop layer to the ground potential (0 V). Therefore, the potential of the punch-through stop layer is fixed to the ground potential, so that even if the switching operation of the MOSFET is repeated, the potential shift of the punch-through stop layer can be suppressed. As a result, the influence on the dynamic characteristics of the wide bandgap semiconductor device including the MOSFET is reduced.

[0139] In this regard, for example, in Figure 8 showing the first embodiment, the planar shape of the punch-through stop layer PTS is configured by the pattern PTN1 including a plurality of sub-patterns SPN1 to SPN5 and the pattern PTN2 having a ring shape and surrounding the pattern PTN1. If a configuration in which the ground potential is supplied to the punch-through stop layer PTS configured in this way can be realized, the punch-through stop layer PTS can be fixed to the ground potential.

[0140] Examples of a configuration in which the ground potential is supplied to the punch-through stop layer PTS will be described below. The detailed description will be given with reference to a manufacturing process view of an A-A cross section in Figure 16 .

[0141] Configuration A of the third embodiment

[0142] First, as shown in FIG. 10A, an epitaxial layer EPI1 is formed on an n-type semiconductor substrate SUB by using epitaxial growth. Next, aluminum as a p-type impurity (acceptor) is introduced into the epitaxial layer EPI1 by using photolithography and ion implantation. Thus, a punchthrough stop layer PTS is formed in the epitaxial layer EPI1. Figure 17

[0143] Subsequently, as shown in FIG. 10B, an epitaxial layer EPI2 is formed by epitaxial growth on the epitaxial layer EPI1 on which the punchthrough stop layer PTS is formed. Thereafter, a p-type plug PLG is formed in the epitaxial layer EPI2 by using photolithography and ion implantation. The p-type plug PLG is connected to the punchthrough stop layer PTS. Figure 18

[0144] Subsequently, as shown in FIG. 10C, a p-type impurity is introduced into the epitaxial layer EPI2 by using photolithography and ion implantation to form a channel layer CH. Then, an n-type impurity is introduced into the channel layer CH by using photolithography and ion implantation to form a source region SR. Figure 19

[0145] Next, as shown in FIG. 10D, a trench TR is formed by using photolithography and etching. Then, after a gate insulating film GOX is formed on inner walls of the trench TR, a gate electrode GE is formed in the trench TR via the gate insulating film GOX. In this way, the epitaxial layer EPI1, the punchthrough stop layer PTS, the epitaxial layer EPI2, the p-type plug PLG, the channel layer CH, the source region SR, the trench TR, the gate insulating film GOX, and the gate electrode GE can be formed. Figure 20

[0146] Here, the source region SR and the channel layer CH are electrically connected to each other and supplied with a ground potential. That is, the ground potential is supplied to each of the source region SR and the channel layer CH. The punchthrough stop layer PTS is electrically connected to the channel layer CH supplied with the ground potential via the p-type plug PLG. Thus, the ground potential is supplied to the punchthrough stop layer PTS. In this way, a configuration in which the ground potential is supplied to the punchthrough stop layer PTS can be achieved.

[0147] An advantage of manufacturing such a structure A is that the p-type plug PLG can be formed by a single high-energy ion implantation. Thus, a manufacturing process can be simplified.

[0148] Structure B of the third embodiment

[0149] First, as shown in FIG. 11A, an epitaxial layer EPI1 is formed on an n-type semiconductor substrate SUB by using epitaxial growth. Next, aluminum as a p-type impurity (acceptor) is introduced into the epitaxial layer EPI1 by using photolithography and ion implantation. Thus, a punchthrough stop layer PTS is formed in the epitaxial layer EPI1. Figure 17 ​​​​As shown, the epitaxial layer EPI1 is formed by using epitaxial growth on the n-type semiconductor substrate SUB. Next, aluminum as a p-type impurity (acceptor) is introduced into the epitaxial layer EPI1 by using photolithography and ion implantation. Thus, the punchthrough stop layer PTS is formed in the epitaxial layer EPI1.

[0150] Subsequently, as shown in FIG. 2B, the lower epitaxial layer EPI2B in which the punchthrough stop layer PTS is formed is formed. The p-type plug PLG1 (lower plug) is formed in the lower epitaxial layer EPI2B by using photolithography and ion implantation. The p-type plug PLG1 is connected to the punchthrough stop layer PTS. Figure 21

[0151] Next, the middle epitaxial layer EPI2M is formed on the lower epitaxial layer EPI2B in which the p-type plug PLG1 is formed. The p-type plug PLG2 (middle plug) is formed in the middle epitaxial layer EPI2M by using photolithography and ion implantation. The p-type plug PLG2 is connected to the p-type plug PLG1. Next, the upper epitaxial layer EPI2U is formed on the middle epitaxial layer EPI2M in which the p-type plug PLG2 is formed. The lower epitaxial layer EPI2B, the middle epitaxial layer EPI2M, and the upper epitaxial layer EPI2U configure the epitaxial layer EPI2.

[0152] Thereafter, as shown in FIG. 2D, the p-type impurity is introduced into the upper epitaxial layer EPI2U by using photolithography and ion implantation to form a channel layer CH. Then, the n-type impurity is introduced into the channel layer CH by using photolithography and ion implantation to form a source region SR. Figure 22 Next, a trench TR is formed by using photolithography and etching. Then, after a gate insulating film GOX is formed on an inner wall of the trench TR, a gate electrode GE is formed in the trench TR via the gate insulating film GOX. In this way, the epitaxial layer EPI1, the punchthrough stop layer PTS, the lower epitaxial layer EPI2B, the middle epitaxial layer EPI2M, the upper epitaxial layer EPI2U, the p-type plug PLG1, the p-type plug PLG2, the channel layer CH, the source region SR, the trench TR, the gate insulating film GOX, and the gate electrode GE can be formed.

[0153] The source region SR and the channel layer CH are electrically connected to each other and are supplied with a ground potential. That is, the ground potential is supplied to each of the source region SR and the channel layer CH. The punchthrough stop layer PTS is electrically connected to the channel layer CH supplied with the ground potential via the p-type plug PLG1 and the p-type plug PLG2. Thus, the ground potential is supplied to the punchthrough stop layer PTS. In this way, a configuration in which the ground potential is supplied to the punchthrough stop layer PTS can be realized.

[0154]

[0155] ​​The advantage of manufacturing such a structure B is that p-type plugs PLG1 and PLG2 can be formed by low-energy ion implantation.

[0156] <<Configuration C of the Third Embodiment>>

[0157] First, such as Figure 17 As shown, the epitaxial layer EPI1 is formed on an n-type semiconductor substrate SUB using epitaxial growth. Next, aluminum, acting as a p-type impurity (acceptor), is introduced into the epitaxial layer EPI1 using photolithography and ion implantation. Therefore, a punch-through barrier layer PTS is formed in the epitaxial layer EPI1.

[0158] Subsequently, as Figure 23 As shown, the epitaxial layer EPI2 is formed by epitaxial growth on the epitaxial layer EPI1, on which a punch-through stop layer PTS is formed. Subsequently, as Figure 24 As shown, p-type impurities are introduced into the epitaxial layer EPI2 using photolithography and ion implantation to form the channel layer CH. Then, n-type impurities are introduced into the channel layer CH using photolithography and ion implantation to form the source region SR.

[0159] Next, as Figure 25 As shown, the trench TR is formed using photolithography and etching. Then, after forming a gate insulating film (GOX) on the inner wall of the trench TR, the gate electrode GE and a dummy electrode DMY (not serving as the gate electrode) are formed in the trench TR via the GOX. Subsequently, a p-type plug PLG containing the dummy electrode DMY is formed using photolithography and oblique ion implantation. The p-type plug PLG is connected to the punch-through stop layer (PTS). In this manner, the epitaxial layer EPI1, the punch-through stop layer PTS, the epitaxial layer EPI2, the p-type plug PLG, the channel layer CH, the source region SR, the trench TR, the gate insulating film GOX, the gate electrode GE, and the dummy electrode DMY can be formed.

[0160] The source region SR and the channel layer CH are electrically connected to each other and are supplied with ground potential. That is, ground potential is supplied to each of the source region SR and the channel layer CH. The punch-through blocking layer PTS is electrically connected to the channel layer CH, which is supplied with ground potential, via a p-type plug PLG. Therefore, ground potential is supplied to the punch-through blocking layer PTS. In this way, the configuration in which ground potential is supplied to the punch-through blocking layer PTS can be achieved.

[0161] The advantage of fabricating such a structure C is that, by using oblique ion implantation, the p-type plug PLG can be formed by low-energy ion implantation.

[0162] <<Configuration D of the Third Embodiment>>

[0163] First, such asFigure 26 As shown, the epitaxial layer EPI1 is formed on an n-type semiconductor substrate SUB using epitaxial growth. Next, aluminum, acting as a p-type impurity (acceptor), is introduced into the epitaxial layer EPI1 using photolithography and ion implantation. Therefore, a punch-through stop layer PTSB is formed in the epitaxial layer EPI1.

[0164] Subsequently, as Figure 27 As shown, the lower epitaxial layer EPI2B is formed on the epitaxial layer EPI1, on which the punch-through stop layer PTSB is formed. Next, aluminum, as a p-type impurity (acceptor), is introduced into the lower epitaxial layer EPI2B using photolithography and ion implantation. Therefore, the punch-through stop layer PTSU is formed in the lower epitaxial layer EPI2B. The punch-through stop layer PTSU is connected to the punch-through stop layer PTSB.

[0165] Subsequently, the intermediate epitaxial layer EPI2M is formed on the lower epitaxial layer EPI2B, on which the punch-through stop layer PTSU is formed. A p-type plug PLG is formed in the intermediate epitaxial layer EPI2M using photolithography and ion implantation. The p-type plug PLG is connected to the punch-through stop layer PTSU. The upper epitaxial layer EPI2U is formed on the intermediate epitaxial layer EPI2M, on which the p-type plug PLG is formed. The lower epitaxial layer EPI2B, the intermediate epitaxial layer EPI2M, and the upper epitaxial layer EPI2U are arranged to form the epitaxial layer EPI2.

[0166] After that, as Figure 28 As shown, p-type impurities are introduced into the upper epitaxial layer EPI2U using photolithography and ion implantation to form the channel layer CH. Then, n-type impurities are introduced into the channel layer CH using photolithography and ion implantation to form the source region SR.

[0167] Next, as Figure 29 As shown, the trench TR is formed using photolithography and etching. Then, after forming a gate insulating film GOX on the inner wall of the trench TR, the gate electrode GE is formed in the trench TR via the gate insulating film GOX. Therefore, the punch-through barrier layer PTSB is formed in the epitaxial layer EPI1.

[0168] The lower epitaxial layer EPI2B, the punch-through barrier layer PTSU, the intermediate epitaxial layer EPI2M, the p-type plug PLG, the upper epitaxial layer EPI2U, the channel layer CH, the source region SR, the trench TR, the gate insulating film GOX, and the gate electrode GE can be formed.

[0169] The punch-through blocking layer is configured by a punch-through blocking layer PTSB formed in the epitaxial layer EPI1 and a punch-through blocking layer PTSU formed in the lower epitaxial layer EPI2B.

[0170] The source region SR and the channel layer CH are electrically connected to each other, and are supplied with a ground potential. That is, the ground potential is supplied to each of the source region SR and the channel layer CH. The punchthrough stopper layer PTSU is electrically connected to the channel layer CH supplied with the ground potential via the p-type plug PLG. Therefore, the ground potential is supplied to the punchthrough stopper layer PTSU. The punchthrough stopper layer PTSB is connected to the punchthrough stopper layer PTSU. Therefore, the ground potential is also supplied to the punchthrough stopper layer PTSB. This makes it possible to achieve a configuration in which the ground potential is supplied to the punchthrough stopper layers PTSB and PTSU.

[0171] An advantage of manufacturing such a structure D is as follows. That is, the punchthrough stopper layer is configured by the punchthrough stopper layer PTSB formed in the epitaxial layer EPI1 and the punchthrough stopper layer PTSU formed in the lower epitaxial layer EPI2B. This improves the degree of freedom of the arrangement of the punchthrough stopper layer, thereby achieving both a shielding effect that alleviates the electric field concentration near the trench bottom efficiently and a reduction in the on-resistance of the current path for the MOSFET (improvement in the electrical characteristics of the MOSFET) by making it easier to ensure.

[0172] As described above, the invention made by the inventors of the present application has been specifically described on the basis of the embodiments. However, it goes without saying that the present invention is not limited to the foregoing embodiments, and various modifications and changes can be made within the scope of the present invention.

Claims

1. A semiconductor device, comprising: An epitaxial layer of a first conductivity type, the epitaxial layer being made of a wide bandgap semiconductor material having a bandgap larger than that of silicon; Multiple trenches are formed in the epitaxial layer; A plurality of gate electrodes, wherein the plurality of gate electrodes are formed in the plurality of trenches via a gate insulating film; as well as A punch-through barrier layer is formed in the epitaxial layer and is formed deeper than the plurality of trenches, and the punch-through barrier layer has a second conductivity type that is opposite to the first conductivity type. In the plan view, the penetration-blocking layer includes a first part and a second part, the first part and the second part being adjacent to each other. In the planar view, the first part and the second part each have a first pattern, and the first pattern has the same planar shape. The first pattern is configured with one or more sub-patterns, and In the plan view, each of the one or more sub-patterns that configure the first pattern partially overlaps with any of the plurality of gate electrodes.

2. The semiconductor device according to claim 1, The planar shape of the penetration barrier layer forms a geometric pattern, the geometric pattern comprising a repetition of the first pattern as a unit pattern.

3. The semiconductor device according to claim 1, The first pattern is configured by one or more sub-patterns, including any one of straight lines, rectangles, circles, and curves.

4. The semiconductor device according to claim 1, in, The first pattern is configured with patterns capable of tessellation of a plane. The pattern capable of tessellting a plane is a pattern using a finite number of planar graphics, wherein the planar graphics do not overlap and can fill the plane without gaps.

5. The semiconductor device according to claim 4, The first pattern is configured with one or more sub-patterns, and The multiple sub-patterns are configured by a combination of multiple single graphics.

6. The semiconductor device according to claim 4, The first pattern is configured with one or more sub-patterns, and The multiple sub-patterns are configured by a combination of various types of graphics.

7. The semiconductor device according to claim 1, Each of the plurality of gate electrodes extends in a first direction, and The one or more sub-patterns configured with the first pattern each extend in a second direction, which intersects the first direction.

8. The semiconductor device according to claim 1, The first part and the second part each have a second pattern, the second pattern having a ring surrounding the first pattern in a plan view.

9. The semiconductor device according to claim 8, The first pattern is connected to the second pattern.

10. The semiconductor device according to claim 9, The first pattern and the second pattern are supplied with ground potential.

11. The semiconductor device according to claim 10, The epitaxial layer comprises a first epitaxial layer of the first conductivity type and a second epitaxial layer of the first conductivity type, wherein the second epitaxial layer is formed on the first epitaxial layer. The semiconductor device includes: A punch-through barrier layer is formed in the first epitaxial layer. A plug, formed in the second epitaxial layer, connected to the punch-through barrier layer, and filled with a semiconductor material of the second conductivity type, A channel layer of the second conductivity type, the channel layer being formed in the second epitaxial layer and electrically connected to the plug, and The source region of the first conductivity type is formed in the second epitaxial layer and on the channel layer, and The source region is electrically connected to the channel layer.

12. The semiconductor device according to claim 11, The second epitaxial layer includes a second lower epitaxial layer of the first conductivity type, a second intermediate epitaxial layer of the first conductivity type, and a second upper epitaxial layer of the first conductivity type. The second intermediate epitaxial layer is formed on the second lower epitaxial layer, and the second upper epitaxial layer is formed on the second intermediate epitaxial layer. The plug is configured with a lower plug and an intermediate plug, the lower plug being formed in the second lower epitaxial layer, and the intermediate plug being formed in the second intermediate epitaxial layer and electrically connected to the lower plug. The channel layer is formed in the second upper epitaxial layer, and The source region is formed in the second upper epitaxial layer.

13. The semiconductor device according to claim 10, The epitaxial layer comprises a first epitaxial layer of the first conductivity type and a second epitaxial layer of the first conductivity type, wherein the second epitaxial layer is formed on the first epitaxial layer. The semiconductor device includes: A punch-through barrier layer is formed in the first epitaxial layer. A plug, formed in the second epitaxial layer, connected to the punch-through barrier layer, and filled with a semiconductor material of the second conductivity type, A dummy electrode, which is included in the plug and does not serve as a gate electrode. A channel layer of the second conductivity type, the channel layer being formed in the second epitaxial layer and electrically connected to the plug, and The source region of the first conductivity type is formed in the second epitaxial layer and on the channel layer, and The source region is electrically connected to the channel layer.

14. The semiconductor device according to claim 10, The epitaxial layer comprises a first epitaxial layer of the first conductivity type and a second epitaxial layer of the first conductivity type, wherein the second epitaxial layer is formed on the first epitaxial layer. The punch-through blocking layer is configured with a first punch-through blocking layer and a second punch-through blocking layer, wherein the first punch-through blocking layer is formed in the first epitaxial layer, the second punch-through blocking layer is formed in the second epitaxial layer, and is electrically connected to the first punch-through blocking layer.

15. The semiconductor device according to claim 1, The wide-bandgap semiconductor material mentioned above is silicon carbide.

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