Semiconductor device and manufacturing method thereof
By setting a field plate and dielectric layer in the trench below the gate of the VDMOS structure, the problem of balancing on-resistance and parasitic capacitance is solved, thereby reducing on-resistance and capacitance and improving switching losses and quality factor performance.
Patent Information
- Application Number
- CN202410588096.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-13
- Publication Date
- 2025-11-18
AI Technical Summary
Existing vertically diffused metal-oxide-semiconductor (VDMOS) structures present a challenge in balancing reducing on-resistance and various parasitic capacitances, which affects switching losses and quality factor.
A trench is formed below the gate of a vertically diffused metal-oxide-semiconductor (VDMOS) structure, and the charge accumulation and electron aggregation are controlled by the arrangement of field plates and dielectric layers in the trench, including laterally separated upper and lower field plates, which are surrounded by dielectric layers of different thicknesses.
It significantly reduces on-resistance and gate-to-drain capacitance, improves switching losses and quality factor, and enhances the electrical performance of semiconductor devices.
Smart Images
Figure CN120980935A_ABST
Abstract
Description
[Technical Field]
[0001] This disclosure relates to semiconductor technology, and in particular to semiconductor devices comprising a vertically diffused metal-oxide-semiconductor structure and methods for manufacturing the same. [Background Technology]
[0002] In power electronic systems, power transistors are commonly used as power components such as power switches and converters. Power transistors are transistors that operate under high voltage and high current conditions. The most common power transistor is the metal-oxide-semiconductor field-effect transistor (MOSFET), which includes horizontal structures, such as laterally-diffused MOS (LDMOS) FETs, and vertical structures, such as planar gate MOSFETs and trench gate MOSFETs. Planar gate MOSFETs, for example, are vertically-diffused MOS (VDMOS) structures, which have advantages such as fast switching speed and high voltage tolerance. However, the conventional VDMOS structure still has many areas for improvement, such as the inability to simultaneously reduce on-resistance (Ron) and various parasitic capacitances. [Summary of the Invention]
[0003] In view of this, this disclosure proposes a semiconductor device and its manufacturing method, in which a trench is formed under the gate of a vertically diffused metal-oxide-semiconductor (VDMOS) structure, and by means of the field plate and dielectric layer in the trench, various parasitic capacitances such as on-resistance (Ron) and gate-to-drain capacitance (Cgd) can be reduced simultaneously, thereby significantly improving the switching loss and figure of merit (FOM) of the semiconductor device.
[0004] According to one embodiment of this disclosure, a semiconductor device is provided, including a substrate, a trench, a first field plate, a second field plate, a first dielectric layer, a second dielectric layer, and a gate electrode. The trench is disposed in the substrate, and the first and second field plates are disposed within the trench. The second field plate is located below the first field plate and is laterally separated from it. The first and second dielectric layers are disposed on the sidewalls of the trench. The first dielectric layer surrounds the outer side surface of the first field plate and has a first thickness. The second dielectric layer surrounds the side surface and bottom surface of the second field plate and has a second thickness greater than the first thickness. The first field plate is located directly above the second dielectric layer. A gate electrode is disposed on the substrate and connected to the first field plate.
[0005] According to an embodiment of this disclosure, a method for manufacturing a semiconductor device is provided, comprising the following steps: providing a substrate; forming a trench in the substrate; forming a first field plate in the trench; forming a second field plate in the trench, located below the first field plate and laterally separated from the first field plate; forming a first dielectric layer on the sidewall of the trench, surrounding the outer side of the first field plate and having a first thickness; forming a second dielectric layer on the sidewall of the trench, surrounding the side and bottom surfaces of the second field plate and having a second thickness greater than the first thickness, wherein the first field plate is formed directly above the second dielectric layer; and forming a gate electrode on the substrate, connected to the first field plate.
[0006] To make the features of this disclosure clear and easy to understand, embodiments are provided below, along with detailed descriptions in conjunction with the accompanying drawings. [Attached Image Description]
[0007] To facilitate understanding, reference should be made to the accompanying drawings and detailed textual descriptions while reading this disclosure. Specific embodiments described herein, along with corresponding drawings, are used to explain the detailed implementation principles of these embodiments. Furthermore, for clarity, features in the drawings may not be drawn to scale; therefore, the dimensions of some features in certain drawings may be intentionally enlarged or reduced. Figure 1 This is a schematic cross-sectional view of a semiconductor device illustrated according to an embodiment of the present disclosure. Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 This is a cross-sectional schematic diagram illustrating some stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.
Detailed Implementation Methods
[0008] This disclosure provides several different embodiments that can be used to implement different features of this disclosure. For the sake of simplicity, examples of specific components and arrangements are also described. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, the following statement regarding "a first feature being formed on or above a second feature" may mean "the first feature and the second feature are in direct contact" or "there are other features between the first feature and the second feature," such that the first feature and the second feature are not in direct contact. Furthermore, various embodiments in this disclosure may use repeated reference numerals and / or textual annotations. The use of these repeated reference numerals and annotations is for the purpose of making the description more concise and clear, and is not intended to indicate any correlation between different embodiments and / or configurations.
[0009] Furthermore, for the spatially related descriptive terms mentioned in this disclosure, such as "below," "low," "under," "above," "above," "up," "top," "bottom," and similar terms, for ease of description, their use is to describe the relative relationship between one component or feature and another (or more) components or features in the diagram. In addition to the orientations shown in the diagram, these spatially related terms are also used to describe the possible orientations of the semiconductor device during use and operation. As the orientation of the semiconductor device varies (rotation 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should be interpreted in a similar manner.
[0010] Although this disclosure uses terms such as first, second, and third to describe various components, parts, regions, layers, and / or sections, it should be understood that such components, parts, regions, layers, and / or sections should not be limited by these terms. These terms are used only to distinguish one component, part, region, layer, and / or section from another, and do not in themselves imply or represent any prior ordinal number of the component, nor do they represent the order of arrangement of one component with another, or the order of manufacturing processes. Therefore, without departing from the scope of the specific embodiments of this disclosure, the first component, part, region, layer, or section discussed below may also be referred to as a second component, part, region, layer, or section.
[0011] The terms "about" or "substantially" as used in this disclosure generally mean within 20%, more preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the quantities provided in the specification are approximate quantities, meaning that the meaning of "about" or "substantially" may be implied even without specific specification.
[0012] The terms “coupled,” “coupled,” and “electrically connected” as used in this disclosure include any means of direct or indirect electrical connection. For example, if the text describes a first component coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other means of connection.
[0013] Although the invention disclosed herein is described below with reference to specific embodiments, the inventive principles of this disclosure can also be applied to other embodiments. Furthermore, in order to avoid obscuring the spirit of the invention, certain details have been omitted, and these omitted details fall within the scope of knowledge of those skilled in the art.
[0014] This disclosure relates to a semiconductor device comprising a vertically diffused metal-oxide-semiconductor (VDMOS) structure and a method for manufacturing the same. In embodiments of this disclosure, a laterally spaced upper field plate and a lower field plate are disposed in a trench below the gate electrode. The upper and lower field plates are surrounded by dielectric layers of different thicknesses, wherein the dielectric layer surrounding the upper field plate is significantly thinner than the dielectric layer surrounding the lower field plate. The upper field plate is connected to the gate electrode, and the lower field plate is electrically connected to the source electrode and grounded. The thinner dielectric layer located on the sidewall of the upper field plate helps charge accumulation in the junction field-effect transistor (JFET) region, which is beneficial for reducing the on-resistance (Ron). A thicker dielectric layer located on the sidewall of the lower field plate can prevent electron accumulation, thereby reducing the gate-to-drain capacitance (Cgd) and consequently the gate-to-drain charge (Qgd). This can significantly improve the switching loss and figure of merit (FOM) of semiconductor devices, where the figure of merit (FOM) is the product of the on-resistance (Ron) and the gate-to-drain charge (Qgd).
[0015] Figure 1 This is a schematic cross-sectional view of a semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 includes a substrate 101 having opposing first surfaces 101F (e.g., front side) and second surfaces 101B (e.g., back side). The substrate 101 includes a drain region 103 disposed on the second surface 110B of the substrate. The drain region 103 has a first conductivity type, such as an N-type heavily doped region (N... + The substrate 101 further includes an epitaxial layer 102 located on the drain region 103. The epitaxial layer 102 also has a first conductivity type, such as an N-type epitaxial layer, wherein the doping concentration of the drain region 103 is much higher than that of the epitaxial layer 102. In some embodiments, the drain region 103 is, for example, an N-type heavily doped silicon or silicon carbide substrate (N... +The epitaxial layer 102 is, for example, an N-type lightly doped silicon or silicon carbide epitaxial layer (N... - SiC epitaxial layer), but not limited to this.
[0016] like Figure 1 As shown, the semiconductor device 100 includes a gate electrode 115 disposed on a first surface 101F of a substrate 101, and spacers 117 disposed on the sidewalls of the gate electrode 115. In one embodiment, a metal silicide layer 119, composed of, for example, cobalt silicide (CoSix), may also be disposed on the top surface of the gate electrode 115. The metal silicide layer 119 helps to reduce the resistance of the gate electrode 115. In addition, a trench 105 is disposed in the epitaxial layer 102 of the substrate 101 and is located directly below the gate electrode 115. A first field plate 111 is disposed in the trench 105. The first field plate 111 includes a laterally separated first portion 111-1 and a second portion 111-2, and the first field plate 111 is connected to the gate electrode 115. The second field plate 112 is also disposed within the groove 105, located below the first field plate 111, and laterally separated from the first field plate 111. The first field plate 111 and the second field plate 112 do not overlap in the vertical projection direction, such as the Z-axis direction. Furthermore, the third field plate 113 is disposed within the groove 105, located directly above and connected to the second field plate 112. In a first direction perpendicular to the sidewall of the groove 105, such as the X-axis direction, the width of the third field plate 113 is smaller than the width of the second field plate 112. The third field plate 113 is also laterally separated from the first field plate 111, wherein the first portion 111-1 and the second portion 111-2 of the first field plate 111 are located on either side of the third field plate 113, and the first field plate 111 and the third field plate 113 do not overlap in the vertical projection direction, such as the Z-axis direction.
[0017] Additionally, a first dielectric layer 121 is disposed on the sidewall of the trench 105, surrounding the outer surface of the first field plate 111, and contacting the outer surface of the first portion 111-1 and the outer surface of the second portion 111-2. In a first direction, such as the X-axis, the first dielectric layer 121 has a first thickness T1, which in some embodiments is approximately 500 angstroms. Up to 600 Angers However, this is not the only limitation. A second dielectric layer 122 is also disposed on the sidewall of the trench 105, surrounding the side and bottom surfaces of the second field plate 112. In a first direction, such as the X-axis direction, the second dielectric layer 122 has a second thickness T2 greater than the first thickness T2; in some embodiments, the second thickness T2 is approximately 2000 angstroms. Up to 3000 However, this is not the only limitation. Furthermore, the first field plate 111 is located directly above the second dielectric layer 122. In some embodiments, the second thickness T2 of the second dielectric layer 122 may be greater than the widths of the first portion 111-1 and the second portion 111-2, respectively. Additionally, a third dielectric layer 123 is disposed within the trench 105, surrounding the side and top surfaces of the third field plate 113, and is located between the first field plate 111 and the third field plate 113, and between the gate electrode 115 and the third field plate 113. In a first direction, such as the X-axis direction, the third dielectric layer 123 has a third thickness T3 greater than the first thickness T1, and may be less than or slightly equal to the second thickness T2. In some embodiments, the third thickness T3 is approximately 2.5 to 4 times the first thickness T1. In addition, the gate dielectric layer 124 is disposed between the gate electrode 115 and the substrate 101, the gate dielectric layer 124 is connected to the first dielectric layer 121, and the gate dielectric layer 124 may have the same first thickness T1 as the first dielectric layer 121.
[0018] See also Figure 1 The semiconductor device 100 further includes a well region 106 disposed on a first surface 101F of a substrate 101. The well region 106 has a second conductivity type, such as a P-type well region, and is located on both sides of a trench 105. The well region 106 can serve as a substrate region (P-body), and the region between the well region 106 and the trench 105 is a junction field-effect transistor (JFET) region 160. A source region 108 is disposed on the first surface 101F of the substrate 101, located within the well region 106. The source region 108 has a first conductivity type, such as an N-type heavily doped region (N... + The source region 108 is laterally separated from the gate electrode 115. In one embodiment, the semiconductor device 100 may further include a lightly doped source region 107 disposed in the well region 106, adjacent to the side of the source region 108. The lightly doped source region 107 has a first conductivity type, such as an N-type lightly doped region (N... - The lightly doped source region 107 is located directly below the spacer 117 on the sidewall of the gate electrode 115. In a first direction, such as the X-axis direction, the lightly doped source region 107 is located between the source region 108 and the gate electrode 115. The lightly doped source region 107 can reduce the peak electric field intensity near the source region 108, thereby avoiding or reducing leakage current and improving the reliability of the semiconductor device 100.
[0019] Additionally, an interlayer dielectric layer (ILD) 130 is disposed on the first surface 101F of the substrate 101, covering the gate electrode 115, spacer 117, metal silicide layer 119, and source region 108. The source electrode 134 is disposed on the first surface 101F of the substrate 101, located on the interlayer dielectric layer 130, and electrically connected to the source region 108 via a source contact 132. The source contact 132 extends downwards into the well region 106 through the interlayer dielectric layer 130, the gate dielectric layer 124, and the source region 108. A doped region 109, having a second conductivity type, such as a P-type heavily doped region (P...), can also be disposed in the well region 106 directly below the bottom of the source contact 132. + The doped region 109 can serve as the base region (bulk) and is electrically connected to the source electrode 134 via the source contact 132. In addition, the drain electrode 136 is disposed below the second surface 101B of the substrate 101 and directly contacts the drain region 103.
[0020] The second field plate 112 and the third field plate 113 are electrically connected to the source electrode 134 via interconnect structures disposed in the interlayer dielectric layer 130 and vias passing through the third dielectric layer 123. The first field plate 111 is directly connected to the gate electrode 115. According to some embodiments of this disclosure, since the first thickness T1 of the first dielectric layer 121 surrounding the outer side of the first field plate 111 is thinner than the second thickness T2 of the second dielectric layer 121 surrounding the side of the second field plate 112, and the first field plate 111 is electrically connected to the gate electrode 115, this can help increase the charge accumulation in the junction field-effect transistor (JFET) region 160, thereby significantly reducing the on-resistance (Ron). Furthermore, since the second thickness T2 of the second dielectric layer 121 is much thicker than the first thickness T1 of the first dielectric layer 121, and the second field plate 112 is electrically connected to the source electrode 134 and grounded, electron accumulation can be avoided, effectively reducing the gate-to-drain capacitance (Cgd), thereby reducing the gate-to-drain charge (Qgd), and also reducing the gate-to-source capacitance (Cgd). Therefore, the embodiments of this disclosure can significantly improve switching losses and the factor of quality (FOM) to enhance the electrical performance of semiconductor devices.
[0021] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 This is a cross-sectional schematic diagram showing some stages of a method for manufacturing a semiconductor device 100 according to an embodiment of this disclosure. (See also...) Figure 2In step S101, a substrate 101 is first provided, which includes a drain region 103 and an epitaxial layer 102 epitaxially grown on the drain region 103. The substrate 101 has a first surface 101F and a second surface 101B opposite to each other. In one embodiment, the drain region 103 is, for example, an N-type heavily doped silicon carbide substrate, and the epitaxial layer 102 is, for example, an N-type lightly doped silicon carbide epitaxial layer. (Continue reading...) Figure 2 In step S103, a trench 105 is formed in the epitaxial layer 102 of the substrate 101. In one embodiment, a hard shielding layer is first deposited on the first surface 101F of the substrate 101. The hard shielding layer is patterned using photolithography and etching processes, and the epitaxial layer 102 is etched through the openings of the patterned hard shielding to form the trench 105. The patterned hard shielding is then removed, and a sacrificial oxide layer may be formed within the trench 105. This sacrificial oxide layer is then removed to eliminate defects caused by the etching process that formed the trench 105.
[0022] Next, refer to Figure 3 In step S105, a dielectric material layer 120, composed of, for example, silicon oxide, can be conventionally formed within the trench 105 and on the first surface 101F of the substrate 101 using a thermal oxidation or deposition process. In one embodiment, the deposition process in step S105 can be a sub-atmospheric undoped silicon glass (SAUSG) deposition process using tetraethoxysilane (TEOS) and ozone (O3) as reaction precursors. Then, a first semiconductor material layer 139 is deposited on the first surface 101F of the substrate 101 using a deposition process, and the trench 105 is filled. During the deposition process, a conductive dopant can be added to form a doped first semiconductor material layer, composed of, for example, doped polysilicon. Subsequently, a chemical mechanical planarization (CMP) process is used to remove the first semiconductor material layer located on the top surface of the dielectric material layer 120, so that the top surface of the remaining first semiconductor material layer 139 is flush with the top surface of the dielectric material layer 120. (Continue reading...) Figure 3 In step S107, a portion of the first semiconductor material layer 139 is removed using an etch-back process to form an initial field plate 140. The top surface of the initial field plate 140 is approximately at the same horizontal level as the first surface 101F of the substrate 101.
[0023] Then, refer to Figure 4In step S109, a dielectric material 125 is deposited on the initial field plate 140 using a deposition process. The surface of the dielectric material 125 is slightly recessed compared to the top surface of the dielectric material layer 120. The dielectric material 125 can protect the top surface of the initial field plate 140 during subsequent etching. In one embodiment, the dielectric material 125 is composed of, for example, silicon oxide, and the deposition process in step S109 can be a low-pressure chemical vapor deposition (LPCVD) process using tetraethoxysilane (TEOS) as a reaction precursor. (Continue reading...) Figure 4 In step S111, a portion of the dielectric material layer 120 can be removed using a wet etching process to form a second dielectric layer 122 within the trench 105, exposing the upper portion 140T of the initial field plate 140. The lower portion of the initial field plate 140 constitutes the second field plate 112, and the second dielectric layer 122 surrounds the sides and bottom of the second field plate 112. Furthermore, openings 141 are formed within the trench 105, located on both sides of the upper portion 140T of the initial field plate 140.
[0024] Next, refer to Figure 5 In step S113, a thermal oxidation process can be used to oxidize the exposed surfaces of both the epitaxial layer 102 of the substrate 101 and the upper portion 140T of the initial field plate 140. The upper portion 140T of the initial field plate 140 is oxidized to form the third dielectric layer 123, and the unoxidized remaining portion of the upper portion 140T of the initial field plate 140 forms the third field plate 113. The width of the third field plate 113 is smaller than the width of the second field plate 112, and the third field plate 113 is connected to the second field plate 112. The third dielectric layer 113 surrounds the side and top surfaces of the third field plate 113. Simultaneously, the surface of the epitaxial layer 102 adjacent to the sidewall of trench 105 and exposed by opening 141 is also oxidized to form a first dielectric layer 121, and the surface of the epitaxial layer 102 located on the first surface 101F of substrate 101 is also oxidized to form a gate dielectric layer 124, wherein the gate dielectric layer 124 and the first dielectric layer 121 are connected and have the same first thickness T1.
[0025] In some embodiments, the epitaxial layer 102 is composed of, for example, silicon carbide (SiC) or silicon (Si), and the initial field plate 140 is composed of, for example, polycrystalline silicon. Since the oxidation rate of polycrystalline silicon is about 3 to 4 times that of silicon carbide (SiC) and about 2.5 to 3 times that of silicon (Si), the oxidation rate of the initial field plate 140 is higher than that of the epitaxial layer 102, so that the third thickness T3 of the third dielectric layer 123 formed by oxidation is greater than the first thickness T1 of the first dielectric layer 121. The third thickness T3 may be about 2.5 to 4 times that of the first thickness T1 of the first dielectric layer 121.
[0026] See Figure 6In step S115, a deposition process is used to deposit a second semiconductor material layer 150 on the first surface 101F of the substrate 101, filling the opening 141 in the trench 105. During the deposition process, a conductive dopant may be added to form a doped second semiconductor material layer, such as doped polysilicon. The second semiconductor material layer 150 filling the opening 141 forms a first field plate 111, comprising a first portion 111-1 and a second portion 111-2 located on opposite sides of a third field plate 113. A third dielectric layer 123 is located between the first field plate 111 and the third field plate 113, and the third field plate 113 is laterally separated from the first field plate 111. Next, a chemical mechanical planarization (CMP) process can be used to planarize the top surface of the second semiconductor material layer 150. (Continue reading...) Figure 6 In step S117, a patterned photoresist 143 is first formed on the second semiconductor material layer 150 as a shield, and then an etching process is performed to pattern the second semiconductor material layer 150 to form the gate electrode 115.
[0027] See Figure 7 In step S119, the patterned photoresist 143 is removed, and an ion implantation process is performed on the first surface 101F of the substrate 101 to form a well region 106 in the epitaxial layer 102, which has a second conductivity type, such as a P-type well region. The well region 106 is located on both sides of the trench 105, and a portion of the well region 106 can extend laterally to the bottom of the gate electrode 115. Next, another ion implantation process is performed using the gate electrode 115 as a shield to form a lightly doped source region 107 in the well region 106, which has a first conductivity type, such as an N-type lightly doped region. (Continue reading...) Figure 7 In step S121, a rapid thermal annealing (RTA) process can be performed first to activate the dopants in the well region 106 and the lightly doped source region 107. Then, a spacer material layer is deposited on the sidewall and top surface of the gate electrode 115, and an anisotropic dry etching process is performed on the spacer material layer to remove the spacer material layer located on the top surface of the gate electrode 115, so as to form spacer 117 on the sidewall of the gate electrode 115.
[0028] See Figure 8In step S123, an ion implantation process is performed using spacer 117 as a shield to form a source region 108 in well region 106, which has a first conductivity type, such as an N-type heavily doped region, and is adjacent to the lightly doped source region 107. Subsequently, in one embodiment, a patterned resistive protection oxide layer (RPO) can be formed on the first surface 101F of substrate 101, covering the area other than gate electrode 115, as a self-aligned silicide barrier layer. Then, a metal layer, such as cobalt, is deposited on the top surface of gate electrode 115, and thermally treated to react the metal with the silicon in gate electrode 115 to form a metal silicide layer 119 on the top surface of gate electrode 115. The composition of metal silicide layer 119 is, for example, cobalt silicide (CoSix), which helps to reduce the resistance of gate electrode 115.
[0029] Then, refer to Figure 9 In step S125, using a deposition process and a chemical mechanical planarization (CMP) process, an interlayer dielectric layer 130 is formed comprehensively on the first surface 101F of the substrate 101, covering the gate electrode 115, spacer 117, metal silicide layer 119, gate dielectric layer 124, and source region 108. (Continue reading...) Figure 9 In step S127, a source contact hole 131 is formed using patterned photoresist and etching processes. The hole passes through the interlayer dielectric layer 130, the gate dielectric layer 124 and the source region 108, and extends downward into the well region 106. The bottom surface of the source contact hole 131 exposes the well region 106, and the sidewalls of the source contact hole 131 expose the source region 108.
[0030] Next, refer to Figure 10 In step S129, an ion implantation process is performed via the source contact hole 131, forming a doped region 109 in the well region 106 directly below the source contact hole 131. The doped region 109 can serve as a base region (bulk). The doped region 109 has the same conductivity type as the well region 106, but the doping concentration of the doped region 109 is higher than that of the well region 106. The doped region 109 is, for example, a heavily p-type doped region (P... + (Continue reading) Figure 10In step S131, a conductive material, such as tungsten (W), copper (Cu), or other suitable metal, is filled into the source contact hole 131 to form a source contact 132. Furthermore, before filling with the conductive material, a diffusion barrier layer can be formed oriented on the sidewalls and bottom surface of the source contact hole 131 to prevent the metal of the source contact 132 from diffusing outwards. The composition of the diffusion barrier layer is, for example, titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), zirconium nitride (ZrN), or other suitable diffusion barrier materials. Then, using deposition, photolithography, and etching processes, a source electrode 134 is formed on the interlayer dielectric layer 130 and the source contact 132. Its composition is, for example, aluminum copper (AlCu), or other suitable metal materials. The source electrode 134 is electrically connected to the source region 108 and the doped region 109 via the source contact 132. Furthermore, the second field plate 112 and the third field plate 113 can be electrically connected to the source electrode 134 via other vias and conductive layers. Subsequently, using a deposition process, a drain electrode 136 is formed under the second surface 101B of the substrate 101 to directly contact the drain region 103, thereby completing the process. Figure 1 Semiconductor device 100.
[0031] According to some embodiments of this disclosure, a second dielectric layer with the largest thickness and a first dielectric layer with the smallest thickness can be formed in a trench below the gate electrode. The first dielectric layer surrounds the outer side of a first field plate within the trench, and the first field plate is electrically connected to the gate electrode. This helps to accumulate charge in the junction field-effect transistor (JFET) region, thereby significantly reducing the on-resistance (Ron). Furthermore, a second dielectric layer surrounds a second field plate within the trench, and the second field plate is electrically connected to the source electrode and grounded. This prevents electron accumulation, effectively reducing the gate-to-drain capacitance (Cgd), and consequently reducing the gate-to-drain charge (Qgd). Therefore, embodiments of this disclosure can significantly improve switching losses and the factor of quality (FOM), thereby enhancing the electrical performance of semiconductor devices. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included within the scope of the present invention. [Symbol Explanation]
[0032] 100… Semiconductor devices 101…base 101F…First Surface 101B…Second Surface 102… epitaxial layer 103…Drain region 105… trench 106… well area 107…source extremely light doped region 108…Source Region 109…doped region 111…First game board 111-1… Part One 111-2… Part Two 112…Second game board 113… Third game board 115…Gate electrode 117…spacers 119…metal silicide layer 120…Dielectric material layer 121…First dielectric layer 122…Second dielectric layer 123…Third dielectric layer 124… Gate Dielectric Layer 125… Dielectric material 130… interlayer dielectric layer 131…Source contact hole 132…Source Contact 134…Source Electrode 136…Drain electrode 139…First semiconductor material layer 140…Initial Field Plate 140T… Upper part 141…Opening 143… Patterned photoresist 150…Second semiconductor material layer 160… Junction Field-Effect Transistor (JFET) Region T1…First Thickness T2…Second thickness T3…Third Thickness Steps S101, S103, S105, S107, S109, S111, S113, S115, S117, S119, S121, S123, S125, S127, S129, S131…
Claims
1. A semiconductor device, comprising: One base; A trench is provided in the substrate; A first field plate is set inside the trench; A second field plate is disposed in the trench, located below the first field plate, and laterally separated from the first field plate; A first dielectric layer is disposed on one side wall of the trench, surrounding the outer side surface of the first field plate, and has a first thickness; A second dielectric layer is disposed on the sidewall of the trench, surrounding the side and bottom surfaces of the second field plate, and has a second thickness greater than the first thickness, wherein the first field plate is located directly above the second dielectric layer; and A gate electrode is disposed on the substrate and connected to the first field plate.
2. The semiconductor device of claim 1, further comprising: A third field plate is disposed in the trench, connected to the second field plate, and laterally separated from the first field plate; as well as A third dielectric layer is disposed within the trench, between the first field plate and the third field plate.
3. The semiconductor device of claim 2, wherein the third field plate has a third thickness greater than the first thickness and less than the second thickness.
4. The semiconductor device of claim 2, wherein the first field plate includes a first portion and a second portion that are laterally separated and located on both sides of the third field plate, respectively.
5. The semiconductor device of claim 2, wherein the third dielectric layer surrounds the side and top surfaces of the third field plate, and the third dielectric layer is disposed between the gate electrode and the third field plate.
6. The semiconductor device of claim 2, wherein the third field plate is located directly above the second field plate, and the width of the third field plate is smaller than the width of the second field plate.
7. The semiconductor device of claim 1, wherein the first field plate and the second field plate do not overlap in the vertical projection direction.
8. The semiconductor device of claim 1, further comprising: A source region is disposed on a first surface of the substrate and is laterally spaced from the gate electrode; A drain region is disposed on a second surface of the substrate; A source electrode is disposed on the first surface of the substrate and electrically connected to the source region; and A drain electrode is disposed below the second surface of the substrate and in direct contact with the drain region, wherein the second field plate is electrically connected to the source electrode.
9. The semiconductor device of claim 1 further includes a metal silicide layer disposed on the top surface of the gate electrode.
10. The semiconductor device of claim 1, further comprising a gate dielectric layer disposed between the gate electrode and the substrate, the gate dielectric layer being connected to the first dielectric layer and having the first thickness.
11. A method for manufacturing a semiconductor device, comprising: Provide a base; A trench is formed in the substrate; A first field plate is formed within the trench; A second field plate is formed in the trench, located below the first field plate, and laterally separated from the first field plate; A first dielectric layer is formed on one side wall of the trench, surrounding the outer side of the first field plate, and has a first thickness; A second dielectric layer is formed on the sidewall of the trench, surrounding the side and bottom surfaces of the second field plate, and has a second thickness greater than the first thickness, wherein the first field plate is formed directly above the second dielectric layer; as well as A gate electrode is formed on the substrate and connected to the first field plate.
12. The method for manufacturing a semiconductor device as described in claim 11, further comprising: A third field plate is formed in the trench, connected to the second field plate, and laterally separated from the first field plate; as well as A third dielectric layer is formed in the trench, between the first field plate and the third field plate.
13. The method of manufacturing a semiconductor device as claimed in claim 12, wherein forming the second field plate and the second dielectric layer comprises: A dielectric material layer is formed in the trench in a oriented manner; A first semiconductor material layer is deposited to fill the trench to form an initial field plate; as well as A portion of the dielectric material layer is removed to form the second dielectric layer, exposing an upper portion of the initial field plate, wherein the lower portion of the initial field plate forms the second field plate and is surrounded by the second dielectric layer.
14. The method of manufacturing a semiconductor device as claimed in claim 13, wherein forming the first dielectric layer, the third field plate, and the third dielectric layer comprises: The substrate and the upper portion of the initial field plate are subjected to an oxidation process, wherein the upper portion of the initial field plate is oxidized to form the third dielectric layer, a remaining portion of the upper portion of the initial field plate forms the third field plate, the width of the third field plate is smaller than the width of the second field plate, the third dielectric layer surrounds the third field plate, and a portion of the substrate adjacent to the trench is oxidized to form the first dielectric layer.
15. The method of manufacturing a semiconductor device as claimed in claim 14, wherein the surface of the substrate is oxidized to form a gate dielectric layer, the gate dielectric layer being connected to the first dielectric layer and having the first thickness.
16. The method of manufacturing a semiconductor device as claimed in claim 14, wherein the oxidation rate of the initial field plate is higher than the oxidation rate of the substrate, and the third dielectric layer has a third thickness greater than the first thickness.
17. The method of manufacturing a semiconductor device as claimed in claim 14, wherein forming the first field plate and the gate electrode comprises: A second semiconductor material layer is deposited on the substrate and fills the trench, wherein the second semiconductor material layer in the trench forms the first field plate, and the first field plate includes a first portion and a second portion, which are respectively located on both sides of the third field plate; as well as The second semiconductor material layer on the substrate is patterned to form the gate electrode.
18. The method of manufacturing a semiconductor device as claimed in claim 11, further comprising forming a metal silicide layer on the top surface of the gate electrode.
19. The method for manufacturing a semiconductor device as claimed in claim 11, further comprising: A source region is formed on a first surface of the substrate, and the source region is laterally spaced from the gate electrode; A drain region is formed on a second surface of the substrate; A source electrode is formed on the first surface of the substrate and electrically connected to the source region; and A drain electrode is formed below the second surface of the substrate and in direct contact with the drain region, wherein the second field plate is electrically connected to the source electrode.
20. The method for manufacturing a semiconductor device as claimed in claim 19, further comprising: A well region is formed on the first surface of the substrate, the well region having a conductivity type opposite to that of the source region; Using the gate electrode as a shield, a lightly doped source region is formed within the well region; A spacer is formed on the sidewall of the gate electrode; Using this spacer as a shield, the source electrode region is formed within the well region; A dielectric layer is formed to cover the gate electrode; A source contact hole is formed, which passes through the interlayer dielectric layer and the source region, and extends downward into the well region; A doped region with the same conductivity as the well region is formed directly below the source contact hole. as well as A conductive material is filled into the source contact hole to form a source contact that electrically connects the source electrode and the source region.