Pseudo gate forming method and semiconductor device forming method

Abstract

The invention discloses a dummy gate forming method and a semiconductor device forming method, and the dummy gate forming method comprises the steps: providing a substrate, the surface of the substrate is provided with a recessed region, and a stacked structure which is used for forming a dummy gate and has a boundary located in the recessed region is formed on the substrate; a protection layer is formed on the substrate, the protection layer covers the side wall of the laminated structure and the surface of the substrate, and the protection layer forms a groove above the concave area; spin-coating a compensation material on the protection layer and etching the spin-coated compensation material until the protection layer outside the groove is exposed and the compensation material in the groove is reserved; and etching the protection layer and the compensation material in the groove so as to form a pseudo grid side wall by the protection layer covering the side wall of the laminated structure after the protection layer on the surface of the substrate is removed. According to the invention, the dummy gate side wall can also form a footing in the recessed area of the surface of the substrate, thereby effectively protecting the bottom layer structure of the dummy gate.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a dummy gate forming method and a semiconductor device forming method. BACKGROUND

[0002] The feature size of semiconductor devices is continuously reduced according to Moore's Law, and the gate of a semiconductor device usually adopts a high dielectric metal gate (HKMG) when entering a process node below 28 nm. The high dielectric metal gate is formed by a gate replacement process, and a "high-K first" method is one of the gate replacement processes, which forms a high-K dielectric layer on a gate formation region on the surface of a substrate and then forms a dummy gate.

[0003] Figure 1a and Figure 1b Fig. 1 shows a schematic diagram of a semiconductor device in the prior art. As shown in Fig. 1, the semiconductor device includes a substrate 110, a high-K dielectric layer 121, a layer stack 130, a protective layer 140, and a gate 150. The substrate 110 includes a doped region 111 and an isolation structure 112. The high-K dielectric layer 121 is formed on the surface of the substrate 110. The layer stack 130 is formed on the high-K dielectric layer 121 and includes a polysilicon layer 131, a silicon nitride layer 132, and a silicon oxide layer 133. The protective layer 140 is formed on the surface of the substrate 110 and covers the high-K dielectric layer 121 and the sidewalls of the layer stack 130 as well as the top of the layer stack 130. The gate 150 is formed on the layer stack 130 and includes a gate electrode 151 and a gate sidewall 152. Figure 1a As shown in Fig. 2, the dummy gate forming process includes forming the layer stack 130 on the high-K dielectric layer 121 for constituting the dummy gate. The layer stack 130 can include the polysilicon layer 131, the silicon nitride layer 132, and the silicon oxide layer 133 as shown in Fig. 3. Figure 1a In order to protect the layer stack 130 from being damaged, the dummy gate forming process further includes depositing the protective layer 140 on the substrate 110 as shown in Fig. 4. The protective layer 140 covers the high-K dielectric layer 121 and the sidewalls of the layer stack 130 as well as the top of the layer stack 130. The protective layer 140 also covers the surface of the substrate 110. Figure 1a As shown in Fig. 5, the dummy gate forming process further includes etching away the portion of the protective layer 140 covering the surface of the substrate 110. The portion of the protective layer 140 covering the top of the layer stack 130 is also etched away in this process, thereby forming the dummy gate sidewall 152 as shown in Fig. 6. The dummy gate sidewall 152 protects the layer stack 130 from the side as a part of the dummy gate. Figure 1b Figure 1b However, in some semiconductor devices, the gate formation region spans the doped region 111 and the isolation structure 112 included in the substrate 110. The isolation structure 112 is recessed at the edge adjacent to the doped region 111, and the boundary of the dummy gate is located in the recessed region of the isolation structure 112. Thus, the protective layer 140 has a trench above the recessed region as indicated by the arrow in Fig. 7, and the dummy gate sidewall 152 formed after etching cannot form a footing within the dashed circle as shown in Fig. 8. The high-K dielectric layer 121 will be exposed as shown in Fig. 9.

[0004] Figure 1a Figure 1b Figure 2 ​​​​The exposed part is indicated by the arrow. The reaction between the sulfuric acid in the subsequent cleaning process and the exposed high-K dielectric layer 121 can cause the high-K dielectric layer 121 to be hollowed out. SUMMARY

[0005] In view of the above problems, the present application provides a dummy gate forming method and a semiconductor device forming method, aiming to improve the process so that the dummy gate side wall can also form a footing in the recessed area of the substrate surface, thereby effectively protecting the bottom structure of the dummy gate.

[0006] According to a first aspect of the present application, a dummy gate forming method is provided, comprising:

[0007] providing a substrate, wherein a recessed area exists on the surface of the substrate and a layer structure for constituting a dummy gate is formed on the substrate, and the boundary of the layer structure is located in the recessed area;

[0008] forming a protection layer on the substrate, wherein the protection layer covers the sidewall of the layer structure and the surface of the substrate, and the protection layer forms a trench above the recessed area;

[0009] spinning a compensation material on the protection layer and etching the spun compensation material until the protection layer outside the trench is exposed and the compensation material in the trench is reserved;

[0010] etching the protection layer and the compensation material in the trench to form a dummy gate side wall by the protection layer covering the sidewall of the layer structure after removing the protection layer on the surface of the substrate.

[0011] Optionally, the compensation material is a liquid material for forming a bottom anti-reflective coating.

[0012] Optionally, the material of the protection layer is different from the compensation material, and etching the spun compensation material comprises: etching the spun compensation material by a first etching process, wherein the etching rate of the compensation material is greater than the etching rate of the protection layer in the first etching process.

[0013] Optionally, the first etching process is a dry etching process using plasma gas, and the compensation material in the trench is reserved by adjusting the etching bias and the pressure of the plasma gas in the etching chamber.

[0014] Optionally, etching the protection layer and the compensation material in the trench comprises: etching the protection layer and the compensation material in the trench by a second etching process, wherein the etching rate of the compensation material is equal to the etching rate of the protection layer in the second etching process.

[0015] Optionally, a high-K dielectric layer is formed on the substrate and borders the recessed region, and the high-K dielectric layer is between the substrate surface and the stack structure.

[0016] Optionally, a barrier layer is formed on the substrate and borders the recessed region, and the barrier layer is between the high-K dielectric layer and the stack structure.

[0017] Optionally, the barrier layer is made of titanium nitride.

[0018] Optionally, the substrate includes an adjacent isolation structure and an active region, and the recessed region is located at an edge surface of the isolation structure adjacent to the active region.

[0019] According to a second aspect of the present application, a method for forming a semiconductor device is provided, comprising:

[0020] forming a dummy gate by any of the methods for forming a dummy gate according to the first aspect;

[0021] forming a source region and a drain region in the substrate on both sides of the dummy gate by an ion implantation process;

[0022] forming an interlayer dielectric layer on the substrate on both sides of the dummy gate, and the top of the interlayer dielectric layer is flush with the dummy gate;

[0023] removing the dummy gate to form a recess in the interlayer dielectric layer, and forming a metal gate in the recess to replace the dummy gate.

[0024] The present application has the following unexpected technical effects:

[0025] The method for forming a dummy gate provided by the present application, after forming a stack structure and a protective layer covering the sidewall of the stack structure and the substrate surface on the substrate and bordering a recessed region, the protective layer is filled with a compensation material in the trench above the recessed region by spin-coating the compensation material on the protective layer, and the protective layer outside the trench is exposed and the compensation material in the trench is reserved by etching the spin-coated compensation material, so that in the process of etching the protective layer to form a dummy gate sidewall, since the trench has been filled with the compensation material, the dummy gate sidewall can also form a footing in the recessed region of the substrate surface, thereby effectively protecting the bottom structure of the dummy gate.

[0026] Further, the compensation material is a liquid material for forming a bottom anti-reflective coating, so that the compensation material can be smoothly filled in the trench above the recessed region of the protective layer in the process of spin-coating the compensation material on the protective layer, and a bottom anti-reflective coating filled in the trench in a solid state is formed on the protective layer after the spin-coating process, thereby ensuring that the trench of the protective layer is stably filled.

[0027] Further, the spin-on compensation material can be etched by a first etching process which is a dry etching process using plasma gas, and the etching bias and the pressure of the plasma gas in the etching chamber are adjusted so that the plasma gas does not react with the compensation material in the trench by rapidly impacting on the trench without exposing the protection layer outside the trench, thereby facilitating to ensure that the compensation material in the trench is reserved.

[0028] Further, the protection layer and the compensation material in the trench can be etched by a second etching process, and the etching rate of the compensation material is equal to the etching rate of the protection layer in the second etching process, so that the protection layer and the compensation material in the trench are etched at the same etching rate during the second etching process, and the protection layer under the trench is no longer etched rapidly due to the existence of the trench, thereby facilitating to ensure that the pseudo gate side wall forms a footing in the recessed area on the substrate surface. BRIEF DESCRIPTION OF DRAWINGS

[0029] The above and other objects, features and advantages of the present application will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1a shows a schematic cross-sectional view of the protection layer after being formed in a pseudo gate forming process according to the prior art;

[0031] Figure 1b shows a schematic cross-sectional view of the pseudo gate side wall after being formed in a pseudo gate forming process according to the prior art;

[0032] Figure 2 shows a schematic view of a structure of a pseudo gate formed according to the prior art;

[0033] Figure 3 shows a schematic cross-sectional view of a semiconductor device;

[0034] Figure 4 shows a flow chart of a pseudo gate forming method according to an embodiment of the present application;

[0035] Figure 5a shows a schematic cross-sectional view of the compensation layer after being formed in a pseudo gate forming process according to an embodiment of the present application;

[0036] Figure 5b shows a schematic cross-sectional view of the protection layer outside the trench after being exposed in a pseudo gate forming process according to an embodiment of the present application;

[0037] Figure 5c shows a schematic cross-sectional view of the pseudo gate side wall after being formed in a pseudo gate forming process according to an embodiment of the present application;

[0038] Figure 6A structure diagram of a dummy gate formed according to an embodiment of the present application is shown.

[0039] Figure 7 A flow chart of a method for forming a semiconductor device according to another embodiment of the present application is shown.

[0040] Reference Signs List: 110-substrate; 111-active region; 112-isolation structure; 113-source region; 114-drain region; 120-high dielectric metal gate; 121-high K dielectric layer; 122-barrier layer; 123-metal gate; 130-laminated structure; 131-polysilicon layer; 132-silicon nitride layer; 133-silicon oxide layer; 140-protection layer; 150-dummy gate sidewall; 160-compensation material; 170-improved dummy gate sidewall; 180-interlayer dielectric layer. DETAILED DESCRIPTION

[0041] The present application will be described in more detail with reference to the drawings. Like elements in the various figures are denoted by like reference numerals. Each figure is not drawn to scale for the sake of clarity. Furthermore, some known elements can not be shown.

[0042] The present application can take various forms, some of which will now be described.

[0043] In the rapid development of semiconductor manufacturing technology, MOS (Metal Oxide Semiconductor) devices are continuously shrinking, and the thickness of the gate oxide layer in the MOS devices is continuously reduced. The thickness of the gate oxide layer is too small to cause a significant carrier tunneling effect, and a high dielectric metal gate is used to solve this problem. The high dielectric metal gate replaces the conventional silicon oxide material as the gate dielectric layer of the MOS device by using a high dielectric constant dielectric material, thereby avoiding the occurrence of the carrier tunneling effect caused by the reduction of the thickness of the gate dielectric layer. At the same time, since there is a Fermi level pinning effect between the high dielectric constant dielectric material and the semiconductor substrate, a metal material is needed to replace the conventional polysilicon material as the gate electrode layer of the MOS device. The gate dielectric layer formed by the high dielectric constant dielectric material in the present application is also called a high K dielectric layer, and the gate electrode layer formed by the metal material is also called a metal gate. The high dielectric constant dielectric material forming the gate dielectric layer is, for example, hafnium dioxide, and the metal material forming the gate electrode layer is, for example, aluminum.

[0044] Figure 3 A schematic cross-sectional view of a semiconductor device, such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but not limited thereto, is shown.

[0045] AsFigure 3 As shown, the semiconductor device includes a substrate 110. For an N-type MOSFET, the substrate 110 is P-type doped, and for a P-type MOSFET, the substrate 110 is N-type doped. The semiconductor device also includes a source region 113 and a drain region 114 located in the substrate 110. The source region 113 and drain region 114 are formed by implanting ions into the substrate 110. For an N-type MOSFET, the source region 113 and drain region 114 are N-type doped, and for a P-type MOSFET, the source region 113 and drain region 114 are P-type doped. The channel of the semiconductor device is formed between the source region 113 and drain region 114. The semiconductor device also includes an interlayer dielectric layer 180 located on the substrate 110 and a high-dielectric metal gate 120 located on the channel within the interlayer dielectric layer 180.

[0046] The high-k dielectric metal gate 120 is typically formed using a gate replacement process. In the "high-k first" method, which is a gate replacement process, a high-k dielectric layer 121 is first formed on the gate formation region of the substrate 110, followed by the formation of a dummy gate. After the dummy gate is formed, source regions 113 and drain regions 114 are formed in the substrate 110 on both sides of the dummy gate using an ion implantation process. An interlayer dielectric layer 180, with its top flush with the dummy gate, is then formed on the substrate 110 on both sides of the dummy gate. The dummy gate is then removed, forming a trench in the interlayer dielectric layer 180. The trench is then filled with a metal material to form a metal gate 123 replacing the dummy gate. In some examples, to prevent the metal material forming the metal gate 123 from diffusing into the high-k dielectric layer 121, a barrier layer 122 is formed on the high-k dielectric layer 121 after its formation. The dummy gate is formed after the barrier layer 122 is formed. The barrier layer 122 may be made of materials such as titanium nitride.

[0047] Pseudo-gates typically include, for example: Figure 1b The layered structure 130 and the pseudo-gate sidewall 150 are shown. The pseudo-gate sidewall 150 is composed of... Figure 1a The protective layer 140 shown is obtained after etching away a portion of the surface of the substrate 110. Therefore, the dummy gate sidewall 150 covers not only the sidewalls of the stacked structure 130, but also the sidewalls of various structures on the surface of the substrate 110 that lie beneath the stacked structure 130. When a recessed region exists on the surface of the substrate 110 and the boundaries of the stacked structure 130 and its various underlying structures are located within this recessed region, the protective layer 140, formed on the substrate 110 by depositing a material such as silicon nitride, will... Figure 1a As shown, a groove appears above the recessed area, as indicated by the arrow. Etching the protective layer 140 then causes the formed pseudo-gate sidewall 150 to appear as... Figure 1b As shown, a base cannot be formed within the dashed circle.

[0048] The surface of substrate 110 has recessed areas, for example, as shown in the figure. Figure 1aThe isolation structure 112 shown is recessed at the edge surface adjacent to the active region 111, because the isolation structure 112 is formed by etching a groove in the substrate 110, filling the etched groove with a material such as silicon oxide, and grinding the filled material, but the area adjacent to the active region 111 cannot be ground flat due to technical reasons and the like during the grinding process, resulting in a recessed area.

[0049] Figure 1a The middle layer stack structure 130 has a right side boundary located in the recessed area of the substrate 110 surface, so the protection layer 140 only appears in the groove on the right side of the layer stack structure 130, and thus Figure 1b The pseudo gate sidewall 150 on the right side of the layer stack structure 130 does not form a footing. In this application, the pseudo gate sidewall 150 forms a footing means that the bottom of the pseudo gate sidewall 150 extends outward, and the pseudo gate sidewall 150 does not form a footing means that the bottom of the pseudo gate sidewall 150 does not extend outward. Referring to Figure 1b , the bottom of the pseudo gate sidewall 150 on the right side of the layer stack structure 130 does not extend outward, and the structure of the bottom layer of the layer stack structure 130 is exposed when thinned to a certain thickness. Figure 2 The structure of the bottom layer of the layer stack structure 130 includes the high-K dielectric layer 121 as shown in Figure 1b , and in some examples also includes the barrier layer 122 as shown in Figure 3 . Taking the materials used in the high-K dielectric layer 121 as hafnium oxide and the materials used in the barrier layer 122 as titanium nitride as an example, sulfuric acid used in subsequent cleaning processes can react with hafnium oxide and titanium nitride, so the exposed structure of the bottom layer of the layer stack structure 130 will be hollowed out due to the reaction with sulfuric acid in the cleaning process, resulting in the final manufactured semiconductor device not having a high-dielectric metal gate 120 that meets the requirements, and the product yield is greatly reduced.

[0050] In view of the above reasons, the embodiments of the present application provide a pseudo gate forming method, which improves the process so that the pseudo gate sidewall can also form a footing in the recessed area of the substrate surface, thereby effectively protecting the pseudo gate bottom layer structure. Figure 4 The flowchart of the pseudo gate forming method provided by the embodiments of the present application is shown in Figure 4 , and the pseudo gate forming method comprises:

[0051] Step S110, providing a substrate, the substrate surface has a recessed area and the substrate has a layer stack structure for constituting a pseudo gate with a boundary located in the recessed area;

[0052] Step S120, forming a protection layer on the substrate, the protection layer covers the sidewall of the layer stack structure and the surface of the substrate, and the protection layer forms a groove above the recessed area;

[0053] Step S130, spin-coating compensation material on the protection layer and etching the spin-coated compensation material until the protection layer outside the trench is exposed and the compensation material inside the trench is reserved;

[0054] Step S140, etching the protection layer and the compensation material inside the trench to form a pseudo gate side wall by the protection layer covering the side wall of the layer structure after removing the protection layer on the surface of the substrate.

[0055] It should be noted that the spin-coating process is a coating process relying on the centrifugal force and gravity generated when the workpiece rotates to flow the coating liquid droplets falling on the workpiece on the surface of the workpiece, so that the above spin-coating compensation material on the protection layer can flow the compensation material in the trench of the protection layer to fill the trench, and the surface of the spin-coated compensation material on the protection layer can be relatively flat, so that a relatively flat surface can be formed in the process of etching the spin-coated compensation material until the protection layer outside the trench is exposed and the compensation material inside the trench is reserved.

[0056] In the embodiment of the present application, the compensation material is etched to expose the protection layer outside the trench and reserve the compensation material inside the trench, so that in the process of etching the protection layer to form a pseudo gate side wall, since the trench has been filled with compensation material, the pseudo gate side wall can also form a footing in the recessed area of the substrate surface, thereby effectively protecting the pseudo gate bottom structure.

[0057] The following will be described in detail Figure 5a to Figure 5c the pseudo gate forming method provided by the embodiment of the present application, Figure 5a to Figure 5c the same as the structure shown in Figure 3 will not be described again in the following description if necessary.

[0058] As Figure 5a shown, in some examples, the substrate 110 can include adjacent active regions 111 and isolation structures 112, and the recessed area described in step S110 can be an area formed by the surface recessing at the edge of the isolation structure 112 adjacent to the active region 111, so that the pseudo gate bottom structure can be effectively protected for the semiconductor device with the gate forming area across the active region 111 and the isolation structure 112.

[0059] The above-mentioned substrate 110 can also form a high-K dielectric layer 121 with a boundary located in the recessed area as Figure 5a shown, the high-K dielectric layer 121 is located between the surface of the substrate 110 and the layer structure 130, so that the high-K dielectric layer 121 can be effectively protected as the pseudo gate bottom structure. Further, the substrate 110 can also form a barrier layer (not shown in Figure 5a ) with a boundary located in the recessed area, the barrier layer is located between the surface of the substrate 110 and the layer structure 130, so that the barrier layer can be effectively protected as the pseudo gate bottom structure. Figure 5aThe high-K dielectric layer 121 and the barrier layer are both effectively protected as a pseudo gate bottom layer structure. The barrier layer is used to prevent the diffusion of metal material on the high-K dielectric layer 121, and the material used can be titanium nitride.

[0060] After the trench-protected layer 140 is formed on the substrate 110, Figure 5a The compensation material 160 spun on the trench-protected layer 140 can be a liquid material for forming a bottom anti-reflection coating (BARC), so that the compensation material 160 can smoothly fill the trench above the recessed area of the trench-protected layer 140 during the process of spinning the compensation material 160 on the trench-protected layer 140, and a bottom anti-reflection coating filled with the trench in a solid state is formed on the trench-protected layer 140 after the spin coating process, thereby ensuring that the trench of the trench-protected layer 140 is stably filled.

[0061] The material used in the trench-protected layer 140 is different from the compensation material 160, and the etching of the spun compensation material in step S130 can be etching the spun compensation material 160 by a first etching process. In the first etching process, the etching rate of the compensation material 160 is greater than the etching rate of the trench-protected layer 140, so that the compensation material 160 is etched by the first etching process of selective etching, but the trench-protected layer 140 is basically not etched. In practice, an etchant with a large etching selectivity can be selected as much as possible in the first etching process, which is conducive to ensuring that the trench-protected layer 140 is not etched during the execution of step S130.

[0062] Further, the first etching process is a dry etching process using plasma gas. Dry etching is an anisotropic etching, and its etching direction is as follows Figure 5aThe first etching process is performed vertically downward, and the etching size is easier to control compared to the wet etching process. Thus, when the first etching process is performed to etch the trench surface of the protection layer 140, the etching is controlled not to etch the compensation material 160 in the trench of the protection layer 140. In addition, the etching bias voltage increases the speed of the plasma gas moving downward during the etching process. The greater the etching bias voltage and the greater the pressure of the plasma gas in the etching chamber, the faster the etching and the easier the plasma gas enters the trench of the protection layer 140 to react with the compensation material 160 in the trench when the trench surface of the protection layer 140 is etched. Thus, the two process parameters, the etching bias voltage and the pressure of the plasma gas in the etching chamber, can be adjusted to make the compensation material 160 in the trench of the protection layer 140 not easy to be removed when the trench surface of the protection layer 140 is etched, so that the compensation material 160 in the trench is retained after the compensation material 160 outside the trench is removed. The pressure of the plasma gas in the etching chamber can be adjusted by pumping the plasma gas out of the etching chamber.

[0063] After the compensation material 160 is etched to the position as shown in FIG. 4, the second etching process is performed to etch the protection layer 140 and the compensation material 160 in the trench. In the second etching process, the etching rate of the compensation material 160 is equal to the etching rate of the protection layer 140. Thus, the protection layer 140 and the compensation material 160 in the trench are etched at the same etching rate during the second etching process. The compensation material 160 in the trench plays a protective role at the beginning of the etching, and the protection layer 140 under the trench is no longer etched quickly due to the existence of the trench. Thus, the improved pseudo gate side wall 170 as shown in FIG. 5 can be formed after the second etching process is performed. Figure 5b After the compensation material 160 is etched to the position as shown in FIG. 4, the second etching process is performed to etch the protection layer 140 and the compensation material 160 in the trench. In the second etching process, the etching rate of the compensation material 160 is equal to the etching rate of the protection layer 140. Thus, the protection layer 140 and the compensation material 160 in the trench are etched at the same etching rate during the second etching process. The compensation material 160 in the trench plays a protective role at the beginning of the etching, and the protection layer 140 under the trench is no longer etched quickly due to the existence of the trench. Thus, the improved pseudo gate side wall 170 as shown in FIG. 5 can be formed after the second etching process is performed. Figure 5c The improved pseudo gate side wall 170 has a footing in the dashed circle as shown in FIG. 5, so that the pseudo gate bottom structure is effectively protected. Figure 5c The improved pseudo gate side wall 170 has a footing in the dashed circle as shown in FIG. 5, so that the pseudo gate bottom structure is effectively protected.

[0064] In practice, when the compensation material 160 is a liquid material for forming a bottom anti-reflective coating and the material of the protection layer 140 is silicon nitride, a hydrogen-doped fluorocarbon gas can be selected as the etchant in the second etching process. In this case, the greater the proportion of hydrogen in the fluorocarbon gas, the faster the protection layer 140 is etched and the slower the compensation material 160 is etched. Thus, the proportion of hydrogen in the fluorocarbon gas can be adjusted to make the etching rate of the compensation material 160 equal to the etching rate of the protection layer 140.

[0065] Figure 6Fig. 1 shows a structure diagram of a dummy gate according to an embodiment of the present application. The white line frame in the figure shows a section of the dummy gate sidewall abutting the substrate surface, wherein the upper white solid line is 4.5 nm long, the lower white solid line is 3.1 nm long, the left white dotted line and the right white dotted line show that the bottom of the dummy gate sidewall extends outward, i.e., the dummy gate sidewall in the recessed area forms a footing.

[0066] According to the dummy gate forming method provided in the above embodiment, another embodiment of the present application further provides a semiconductor device forming method. Figure 7 Fig. 2 shows a flow chart of an exemplary semiconductor device forming method according to an embodiment of the present application. As shown in the figure, the semiconductor device forming method comprises the following steps. Figure 7 As shown in the figure, the semiconductor device forming method comprises the following steps.

[0067] The dummy gate is formed through steps S110 to S140;

[0068] In step S150, source and drain regions are formed in the substrate on both sides of the dummy gate through an ion implantation process;

[0069] In step S160, an interlayer dielectric layer is formed on the substrate on both sides of the dummy gate, and the top of the interlayer dielectric layer is flush with the dummy gate;

[0070] In step S170, the dummy gate is removed to form a recess in the interlayer dielectric layer, and a metal gate is formed in the recess to replace the dummy gate.

[0071] The semiconductor device formed through the above steps S110 to S170 is, for example, Figure 3 the semiconductor device shown in Fig. 1, but Figure 3 the semiconductor device shown in Fig. 1 does not represent a limitation on the semiconductor device formed according to the embodiments of the present application. For detailed descriptions of steps S110 to S170, refer to the related descriptions of the dummy gate forming method above, which will not be described here.

[0072] The semiconductor device forming method provided in the embodiments of the present application can effectively protect the bottom structure of the dummy gate without adjusting the trench depth of the front process isolation structure and the thickness of the dummy gate sidewall, because the dummy gate sidewall in the dummy gate formed through steps S110 to S140 can form a footing in the recessed area of the substrate surface.

[0073] In the drawings and specification, there have been disclosed typical embodiments of the application and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the application being set forth in the following claims.

Claims

1. A dummy gate forming method, comprising: providing a substrate having a recessed region on a surface thereof and a stack structure for forming a dummy gate formed on the substrate and having a boundary located in the recessed region; forming a protection layer on the substrate, the protection layer covering sidewalls of the stack structure and the surface of the substrate, and the protection layer forming a trench over the recessed region; spinning a compensation material on the protection layer and etching the spun compensation material until the protection layer outside the trench is exposed and the compensation material in the trench is reserved; etching the protection layer and the compensation material in the trench to form a dummy gate spacer from the protection layer covering the sidewalls of the stack structure after removing the protection layer on the surface of the substrate.

2. The dummy gate formation method according to claim 1, wherein The compensation material is a liquid material forming a bottom anti-reflective coating.

3. The dummy gate formation method of claim 1, wherein, The material of the protection layer is different from the compensation material, and etching the spun compensation material comprises etching the spun compensation material by a first etching process in which an etching rate of the compensation material is greater than an etching rate of the protection layer.

4. The dummy gate formation method according to claim 3, wherein The first etching process is a dry etching process using plasma gas, and the compensation material in the trench is reserved by adjusting an etching bias and a pressure of the plasma gas in an etching chamber.

5. The dummy gate formation method of claim 3, wherein, Etching the protection layer and the compensation material in the trench comprises etching the protection layer and the compensation material in the trench by a second etching process in which an etching rate of the compensation material is equal to an etching rate of the protection layer.

6. The dummy gate formation method of claim 1, wherein, The substrate further has a high-K dielectric layer formed on the substrate and having a boundary located in the recessed region, the high-K dielectric layer being located between the surface of the substrate and the stack structure.

7. The dummy gate formation method of claim 6, wherein, The substrate further has a barrier layer formed on the substrate and having a boundary located in the recessed region, the barrier layer being located between the high-K dielectric layer and the stack structure.

8. The dummy gate formation method of claim 7, wherein, The barrier layer is made of titanium nitride.

9. The dummy gate formation method of claim 1, wherein, The substrate includes adjacent isolation structures and active regions, and the recessed region is formed by recessing a surface of an edge of the isolation structure adjacent to the active region. 10.A semiconductor device forming method, comprising: forming a dummy gate by the dummy gate forming method of any one of claims 1-9; forming source and drain regions in the substrate on both sides of the dummy gate by an ion implantation process; forming an interlayer dielectric layer on the substrate on both sides of the dummy gate, the interlayer dielectric layer having a top surface flush with the dummy gate; removing the dummy gate to form a recess in the interlayer dielectric layer, and forming a metal gate in the recess to replace the dummy gate.

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