Pseudo-gate forming method and semiconductor device forming method

Abstract

The application discloses a dummy gate forming method and a semiconductor device forming method. The dummy gate forming method comprises the following steps: providing a substrate, the substrate surface has a recessed area, and a layer structure for constituting a dummy gate is formed on the substrate, and the boundary of the layer structure is located in the recessed area; forming a protection layer on the substrate, the protection layer covers the sidewall of the layer structure and the surface of the substrate, and the protection layer forms a groove above the recessed area; spin-coating a compensation material on the protection layer and etching the spin-coated compensation material until the protection layer outside the groove is exposed and the compensation material in the groove is reserved; etching the protection layer and the compensation material in the groove to form a dummy gate sidewall by the protection layer covering the sidewall of the layer structure after removing the protection layer on the surface of the substrate. The application can form a footing in the recessed area on the surface of the substrate, so as to effectively protect the bottom structure of the dummy gate.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a dummy gate and a method for forming a semiconductor device. Background Technology

[0002] As the feature size of semiconductor devices continues to decrease according to Moore's Law, when the process node is below 28nm, the gate of semiconductor devices is usually made of high-k metal (HKMG). The HKMG is formed by a gate replacement process. One type of gate replacement process is the "high-k first" method, which involves forming a high-k dielectric layer in the gate formation region on the substrate surface before forming the dummy gate.

[0003] Figure 1a and Figure 1b The diagram shown illustrates the result of some steps in the pseudo-gate formation process in the prior art. Figure 1a As shown, the pseudo-gate formation process includes: forming a stacked structure 130 for constituting the pseudo-gate on a high-k dielectric layer 121, wherein the stacked structure 130 can be formed as follows: Figure 1a The structure shown includes a polysilicon layer 131, a silicon nitride layer 132, and a silicon oxide layer 133. To protect the stacked structure 130 from damage, the dummy gate formation process is as follows: Figure 1a The process includes: depositing a protective layer 140 on a substrate 110, the protective layer 140 covering the high-k dielectric layer 121, the sidewalls of the stacked structure 130, and the top of the stacked structure 130, and the protective layer 140 also covering the surface of the substrate 110. Since the source and drain regions are formed in the substrate 110 on both sides of the dummy gate through an ion implantation process after the dummy gate is formed, the dummy gate formation process is as follows: Figure 1b The process also includes etching away the portion of the protective layer 140 covering the surface of the substrate 110, and simultaneously etching away the portion of the protective layer 140 covering the top of the stacked structure 130, thereby forming a structure as shown. Figure 1b The pseudo-gate sidewall 150 shown is part of the pseudo-gate and protects the stacked structure 130 from the side.

[0004] However, in some semiconductor devices, the gate formation region spans the substrate 110, including the active region 111 and the isolation structure 112. The isolation structure 112 has a surface recess at the edge adjacent to the active region 111, and the dummy gate boundary is located in the recessed region of the isolation structure 112. Thus, the protective layer 140 is affected by the presence of... Figure 1a The trench indicated by the middle arrow, located above the recessed area, forms a pseudo-gate sidewall 150 after etching. Figure 1b As shown, footing cannot be formed within the dashed coil, and the high-K dielectric layer 121 will... Figure 2As shown by the arrow, the exposed high-K dielectric layer 121 will be hollowed out due to the reaction between sulfuric acid and the exposed high-K dielectric layer 121 during the subsequent cleaning process. Summary of the Invention

[0005] In view of the above problems, this application provides a method for forming a dummy gate and a method for forming a semiconductor device, which aims to improve the process so that the dummy gate sidewall can also form a base in the recessed area on the substrate surface, thereby effectively protecting the underlying structure of the dummy gate.

[0006] According to a first aspect of the present invention, a method for forming a pseudo-gate is provided, comprising:

[0007] A substrate is provided, wherein a recessed region is present on the surface of the substrate and a stacked structure for constituting a pseudo gate is formed on the substrate with the boundary located in the recessed region;

[0008] A protective layer is formed on the substrate, the protective layer covering the sidewalls of the laminated structure and the surface of the substrate, and the protective layer forms a trench above the recessed area;

[0009] A compensating material is spin-coated onto the protective layer and etched until the protective layer outside the trench is exposed and the compensating material inside the trench is retained.

[0010] The protective layer and the compensation material within the trench are etched to form a pseudo gate sidewall by the protective layer covering the sidewalls of the stacked structure after the protective layer on the substrate surface is removed.

[0011] Optionally, the compensation material is a liquid material that forms the bottom anti-reflective coating.

[0012] Optionally, the protective layer uses a material different from the compensation material. The etched spin-coated compensation material includes: etching the spin-coated compensation material through a first etching process, wherein the etching rate of the compensation material in the first etching process is greater than the etching rate of the protective layer.

[0013] Optionally, the first etching process is a dry etching process using plasma gas, and the compensation material in the trench is retained by adjusting the etching bias voltage and the pressure of the plasma gas in the etching chamber.

[0014] Optionally, etching the protective layer and the compensation material in the trench includes: etching the protective layer and the compensation material in the trench using a second etching process, wherein the etching rate of the compensation material in the second etching process is equal to the etching rate of the protective layer.

[0015] Optionally, a high-K dielectric layer with its boundary located in the recessed region is further formed on the substrate, the high-K dielectric layer being located between the substrate surface and the stacked structure.

[0016] Optionally, a barrier layer with its boundary located in the recessed region is also formed on the substrate, the barrier layer being located between the high-k dielectric layer and the stacked structure.

[0017] Optionally, the barrier layer is made of titanium nitride.

[0018] Optionally, the substrate includes adjacent isolation structures and an active region, the recessed region being located on the edge surface of the isolation structure adjacent to the active region.

[0019] According to a second aspect of the present invention, a method for forming a semiconductor device is provided, comprising:

[0020] A pseudo-gate is formed by any of the pseudo-gate forming methods described in the first aspect;

[0021] Source and drain regions are formed in the substrates on both sides of the dummy gate using an ion implantation process.

[0022] An interlayer dielectric layer with its top flush with the dummy gate is formed on the substrates on both sides of the dummy gate;

[0023] The dummy gate is removed to form a groove in the interlayer dielectric layer, and a metal gate replacing the dummy gate is formed in the groove.

[0024] The unexpected technical effect of this application is:

[0025] The dummy gate formation method provided in this application involves forming a stacked structure with its boundary located in a recessed region on a substrate, and a protective layer covering the sidewalls of the stacked structure and the substrate surface. Then, a compensation material is spin-coated onto the protective layer to fully fill the trench above the recessed region. The spin-coated compensation material is etched to expose the protective layer outside the trench while retaining the compensation material inside the trench. Thus, during the subsequent etching of the protective layer to form the dummy gate sidewall, since the trench has been filled with compensation material, the dummy gate sidewall can also form a base in the recessed region on the substrate surface, thereby effectively protecting the underlying structure of the dummy gate.

[0026] Furthermore, the compensation material is a liquid material that forms the bottom anti-reflective coating. Therefore, during the spin coating process on the protective layer, the compensation material can smoothly fill the grooves above the recessed area of ​​the protective layer. After the spin coating process is completed, a bottom anti-reflective coating that fills the grooves is formed on the protective layer in a solid form, thereby ensuring that the grooves of the protective layer are stably filled.

[0027] Furthermore, the spin-coated compensation material can be etched using a first etching process with selective etching. The first etching process is a dry etching process using plasma gas. By adjusting the etching bias and the pressure of the plasma gas in the etching chamber, the plasma gas will not rapidly impact the trench and react with the compensation material in the trench when the protective layer outside the trench is exposed. This helps to ensure that the compensation material in the trench is retained.

[0028] Furthermore, the protective layer and the compensation material in the trench can be etched by a second etching process. In the second etching process, the etching rate of the compensation material is equal to the etching rate of the protective layer. In this way, the protective layer and the compensation material in the trench are etched at the same etching rate during the second etching process. The protective layer below the trench is no longer etched quickly due to the existence of the trench, which helps to ensure that the pseudo gate sidewall forms a foot in the recessed area on the substrate surface. Attached Figure Description

[0029] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0030] Figure 1a A schematic cross-sectional view of the protective layer after its formation during the pseudo-gate formation process according to the prior art is shown.

[0031] Figure 1b A schematic cross-sectional view of the pseudo-gate sidewalls after their formation is shown during the pseudo-gate formation process according to the prior art;

[0032] Figure 2 A schematic diagram of a pseudo-gate formed according to the prior art is shown;

[0033] Figure 3 A schematic cross-sectional view of a semiconductor device is shown;

[0034] Figure 4 This document shows a flowchart illustrating a pseudo-gate formation method according to an embodiment of this application.

[0035] Figure 5a A schematic cross-sectional view is shown after the compensation layer is formed during the formation of the dummy gate according to an embodiment of this application;

[0036] Figure 5b A schematic cross-sectional view is shown after the outer protective layer of the trench is exposed during the formation of the dummy gate according to an embodiment of this application;

[0037] Figure 5c A schematic cross-sectional view is shown after the formation of the dummy gate sidewalls during the dummy gate formation process according to an embodiment of this application;

[0038] Figure 6This diagram illustrates the structure of a pseudo-gate formed according to an embodiment of this application.

[0039] Figure 7 A flowchart illustrating a method for forming a semiconductor device according to another embodiment of this application is shown.

[0040] Figure reference numerals: 110-Substrate; 111-Active region; 112-Isolation structure; 113-Source region; 114-Drain region; 120-High-dielectric metal gate; 121-High-K dielectric layer; 122-Barrier layer; 123-Metal gate; 130-Layered structure; 131-Polysilicon layer; 132-Silicon nitride layer; 133-Silicon oxide layer; 140-Protective layer; 150-Dummy gate sidewall; 160-Compensation material; 170-Improved dummy gate sidewall; 180-Interlayer dielectric layer. Detailed Implementation

[0041] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0042] This application may be presented in various forms, some of which will be described below.

[0043] In the rapid development of semiconductor manufacturing technology, MOS (Metal Oxide Semiconductor) devices are constantly shrinking, and the thickness of the gate oxide layer in MOS devices is also continuously decreasing. Excessively thin gate oxide layers can cause significant carrier tunneling effects, which are addressed by high-dielectric metal gates. High-dielectric metal gates use a high-dielectric-constant dielectric material instead of conventional silicon oxide as the gate dielectric layer of MOS devices, thus avoiding the carrier tunneling effect caused by the reduced gate dielectric layer thickness. Simultaneously, due to the Fermi level pinning effect between the high-dielectric-constant dielectric material and the semiconductor substrate, a metal material is needed instead of conventional polysilicon as the gate electrode layer of MOS devices. In this application, the gate dielectric layer formed by the high-dielectric-constant dielectric material is also called a high-k dielectric layer, and the gate electrode layer formed by the metal material is also called a metal gate. Examples of high-dielectric-constant dielectric materials forming the gate dielectric layer include hafnium dioxide, and examples of metal materials forming the gate electrode layer include aluminum.

[0044] Figure 3 A schematic cross-sectional view of a semiconductor device is shown, such as a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor), but not limited thereto.

[0045] like Figure 3 As shown, the semiconductor device includes a substrate 110. For an N-type MOSFET, the substrate 110 is P-type doped, and for a P-type MOSFET, the substrate 110 is N-type doped. The semiconductor device also includes a source region 113 and a drain region 114 located in the substrate 110. The source region 113 and drain region 114 are formed by implanting ions into the substrate 110. For an N-type MOSFET, the source region 113 and drain region 114 are N-type doped, and for a P-type MOSFET, the source region 113 and drain region 114 are P-type doped. The channel of the semiconductor device is formed between the source region 113 and drain region 114. The semiconductor device also includes an interlayer dielectric layer 180 located on the substrate 110 and a high-dielectric metal gate 120 located on the channel within the interlayer dielectric layer 180.

[0046] The high-k dielectric metal gate 120 is typically formed using a gate replacement process. In the "high-k first" method, which is a gate replacement process, a high-k dielectric layer 121 is first formed on the gate formation region of the substrate 110, followed by the formation of a dummy gate. After the dummy gate is formed, source regions 113 and drain regions 114 are formed in the substrate 110 on both sides of the dummy gate using an ion implantation process. An interlayer dielectric layer 180, with its top flush with the dummy gate, is then formed on the substrate 110 on both sides of the dummy gate. The dummy gate is then removed, forming a trench in the interlayer dielectric layer 180. The trench is then filled with a metal material to form a metal gate 123 replacing the dummy gate. In some examples, to prevent the metal material forming the metal gate 123 from diffusing into the high-k dielectric layer 121, a barrier layer 122 is formed on the high-k dielectric layer 121 after its formation. The dummy gate is formed after the barrier layer 122 is formed. The barrier layer 122 may be made of materials such as titanium nitride.

[0047] Pseudo-gates typically include, for example: Figure 1b The layered structure 130 and the pseudo-gate sidewall 150 are shown. The pseudo-gate sidewall 150 is composed of... Figure 1a The protective layer 140 shown is obtained after etching away a portion of the surface of the substrate 110. Therefore, the dummy gate sidewall 150 covers not only the sidewalls of the stacked structure 130, but also the sidewalls of various structures on the surface of the substrate 110 that lie beneath the stacked structure 130. When a recessed region exists on the surface of the substrate 110 and the boundaries of the stacked structure 130 and its various underlying structures are located within this recessed region, the protective layer 140, formed on the substrate 110 by depositing a material such as silicon nitride, will... Figure 1a As shown, a groove appears above the recessed area, as indicated by the arrow. Etching the protective layer 140 then causes the formed pseudo-gate sidewall 150 to appear as... Figure 1b As shown, a base cannot be formed within the dashed circle.

[0048] The surface of substrate 110 has recessed areas, for example, as shown in the figure. Figure 1aThe isolation structure 112 shown has a recess on the edge surface adjacent to the active region 111. This is because it is necessary to first etch a groove in the substrate 110, then fill the etched groove with a material such as silicon oxide, and grind the filling material to form the isolation structure 112. However, due to technical reasons during the grinding process, the area adjacent to the active region 111 cannot be ground flat and a recessed area exists.

[0049] Figure 1a The middle stacked structure 130 has its right boundary located in a recessed region on the surface of the substrate 110. Therefore, the protective layer 140 only has trenches on the right side of the stacked structure 130, thus... Figure 1b Only the pseudo-gate sidewall 150 located on the right side of the stacked structure 130 failed to form a base. In this application, "forming a base" for the pseudo-gate sidewall 150 means that the bottom of the pseudo-gate sidewall 150 extends outward; "not forming a base" means that the bottom of the pseudo-gate sidewall 150 does not extend outward. (See reference...) Figure 1b The bottom of the pseudo-gate sidewall 150 on the right side of the stacked structure 130 does not extend outward. When thinned to a certain thickness, the structure of the bottom layer of the stacked structure 130 will be as follows: Figure 2 The exposed layer of the stacked structure 130 includes the following structure: Figure 1b The high-k dielectric layer 121 shown in the figure, in some examples also includes, for example, Figure 3 The barrier layer 122 is shown. Taking the high-k dielectric layer 121 made of hafnium dioxide and the barrier layer 122 made of titanium nitride as an example, the sulfuric acid used in the subsequent cleaning process can react with hafnium dioxide and titanium nitride. Therefore, the exposed structure at the bottom of the stacked structure 130 will be hollowed out during the cleaning process due to the reaction with sulfuric acid. As a result, the semiconductor device manufactured in the end cannot have a high-dielectric metal gate 120 that meets the requirements, and the product yield is greatly reduced.

[0050] In view of the above reasons, this application provides a method for forming a pseudo gate, which improves the process so that the pseudo gate sidewalls can also form feet in the recessed area on the substrate surface, thereby effectively protecting the pseudo gate underlying structure. Figure 4 The diagram shown is a flowchart of a pseudo-gate formation method provided in an embodiment of this application. Figure 4 As shown, the method for forming a pseudo-gate includes:

[0051] Step S110: A substrate is provided, the substrate surface has a recessed region and a stacked structure for forming a pseudo gate is formed on the substrate with the boundary located in the recessed region.

[0052] Step S120: A protective layer is formed on the substrate. The protective layer covers the sidewalls of the stacked structure and the surface of the substrate, and a trench is formed in the protective layer above the recessed area.

[0053] Step S130: Spin-coat compensation material onto the protective layer and etch the spin-coated compensation material until the protective layer outside the trench is exposed and the compensation material inside the trench is retained.

[0054] Step S140: Etch the protective layer and the compensation material in the trench to form a pseudo gate sidewall by the protective layer covering the sidewalls of the stacked structure after the protective layer on the substrate surface is removed.

[0055] It should be noted that spin coating is a coating process that relies on the centrifugal force and gravity generated when the workpiece rotates to spread the paint droplets falling on the workpiece to the workpiece surface. Therefore, the above-mentioned spin coating of compensation material on the protective layer can make the compensation material flow into the grooves of the protective layer to fill the grooves. Moreover, the surface of the compensation material spin coated on the protective layer can also be relatively flat. In this way, a relatively flat surface can be formed during the subsequent etching process of the spin coated compensation material until the protective layer outside the grooves is etched and the compensation material in the grooves is retained.

[0056] In this embodiment, the protective layer outside the trench is exposed by etching the spin-coated compensation material while the compensation material inside the trench is retained. In this way, during the subsequent etching of the protective layer to form the pseudo gate sidewall, since the trench has been filled by the compensation material, the pseudo gate sidewall can also form a foot in the recessed area on the substrate surface, thereby effectively protecting the pseudo gate bottom layer structure.

[0057] The following is combined Figures 5a to 5c The pseudo-gate formation method provided in the embodiments of this application will be described in detail. Figures 5a to 5c Zhongyu Figure 3 The parts with the same structure as shown will not be repeated in the following description unless necessary.

[0058] like Figure 5a As shown, in some examples, the substrate 110 may include adjacent active regions 111 and isolation structures 112. The recessed region mentioned in step S110 may be the region formed by the surface recess at the edge of the isolation structure 112 adjacent to the active region 111, so that the pseudo-gate underlying structure can be effectively protected for semiconductor devices in which the gate formation region spans the active region 111 and the isolation structure 112.

[0059] The substrate 110 may also be formed with such as Figure 5a The high-K dielectric layer 121, with its boundary located in the recessed region, is situated between the surface of the substrate 110 and the stacked structure 130, thus effectively protecting the high-K dielectric layer 121 as the dummy gate bottom layer structure. Furthermore, a barrier layer with its boundary located in the recessed region can also be formed on the substrate 110. Figure 5a (not shown in the image), the barrier layer is located in Figure 5aThe high-k dielectric layer 121 and the stacked structure 130 described herein are positioned between each other, thus effectively protecting both the high-k dielectric layer 121 and the barrier layer, which serve as the bottom layer of the pseudo-gate structure. The barrier layer is used to prevent the diffusion of metallic materials onto it into the high-k dielectric layer 121, and the material used can be titanium nitride.

[0060] After forming the protective layer 140 with trenches on the substrate 110, Figure 5a The compensation material 160 spin-coated on the protective layer 140 can be a liquid material that forms a bottom anti-reflection coating (BARC). Therefore, during the spin-coating process of the compensation material 160 on the protective layer 140, the compensation material 160 can smoothly fill the grooves of the protective layer 140 above the recessed area. After the spin-coating process is completed, a bottom anti-reflection coating that fills the grooves is formed on the protective layer 140 in a solid form, thereby ensuring that the grooves of the protective layer 140 are stably filled.

[0061] The protective layer 140 uses a different material than the compensation material 160. In step S130, the compensation material being etched by spin-coating can be etched using a first etching process. In this first etching process, the etching rate of the compensation material 160 is greater than the etching rate of the protective layer 140. This allows for selective etching of the compensation material 160, while the protective layer 140 remains largely untouched. In practice, an etchant with a high selectivity can be selected in the first etching process to ensure that the protective layer 140 is not etched during step S130.

[0062] Furthermore, the first etching process is a dry etching process using plasma gas. Dry etching is anisotropic etching, and its etching direction is as follows: Figure 5aThe diagram shows a vertical downward etching process. Compared to wet etching, the etching size is easier to control. This allows for better control during the first etching process, preventing further etching of the compensation material 160 within the trenches of the protective layer 140 when the material reaches the surface of the trenches. Furthermore, the etching bias increases the downward velocity of the plasma gas. A higher etching bias and higher plasma gas pressure within the etching chamber result in faster etching and easier entry of the plasma gas into the trenches of the protective layer 140, where it reacts with the compensation material 160. Therefore, by adjusting the etching bias and plasma gas pressure within the etching chamber just before reaching the trench surface, the compensation material 160 within the trenches can be prevented from being easily removed. This ensures that the compensation material 160 within the trenches is retained even after the material outside the trenches is removed. The pressure of the plasma gas within the etching chamber can be adjusted by drawing plasma gas out of the chamber.

[0063] In the etching compensation material 160 to such Figure 5b With the protective layer 140 exposed outside the trench and the compensation material 160 inside the trench retained, a second etching process is performed to etch both the protective layer 140 and the compensation material 160 inside the trench. In this second etching process, the etching rate of the compensation material 160 is equal to the etching rate of the protective layer 140. Thus, during the second etching process, the protective layer 140 and the compensation material 160 inside the trench are etched at indiscriminate etching rates. Initially, the compensation material 160 inside the trench provides protection, and the protective layer 140 below the trench is no longer rapidly etched due to the presence of the trench. Therefore, after the second etching process is completed, a layer is formed as shown... Figure 5c The improved pseudo-gate sidewall 170 is shown. The improved pseudo-gate sidewall 170 is as follows: Figure 5c As shown, the base is located within the dashed circle, thus effectively protecting the pseudo-gate underlying structure.

[0064] In practice, when the compensation material 160 is a liquid material forming the bottom anti-reflective coating and the protective layer 140 is made of silicon nitride, a hydrogen-doped fluorocarbon gas can be used as an etchant in the second etching process. Since the higher the proportion of hydrogen in the fluorocarbon gas, the faster the protective layer 140 is etched and the slower the compensation material 160 is etched, the etching rate of the compensation material 160 can be made equal to the etching rate of the protective layer 140 by adjusting the proportion of hydrogen in the fluorocarbon gas.

[0065] Figure 6The diagram shows a schematic of a pseudo gate structure formed according to an embodiment of this application. The area enclosed by the white frame in the diagram is a section of the pseudo gate sidewall adjacent to the substrate surface. The upper white solid line is 4.5 nm long, the lower white solid line is 3.1 nm long, and the left and right white dashed lines indicate that the bottom of the pseudo gate sidewall extends outward, which means that the pseudo gate sidewall located in the recessed area forms a foot.

[0066] Corresponding to the pseudo-gate formation method provided in the above embodiments, another embodiment of this application also provides a method for forming a semiconductor device. Figure 7 The diagram shown is a flowchart of an exemplary method for forming a semiconductor device according to an embodiment of this application. Figure 7 As shown, the method for forming the semiconductor device includes:

[0067] A pseudo-gate is formed through steps S110 to S140;

[0068] Step S150: Source and drain regions are formed in the substrate on both sides of the dummy gate by ion implantation.

[0069] Step S160: An interlayer dielectric layer with its top flush with the dummy gate is formed on the substrates on both sides of the dummy gate.

[0070] Step S170: Remove the dummy gate and form a groove in the interlayer dielectric layer, and form a metal gate in the groove to replace the dummy gate.

[0071] The semiconductor device formed through steps S110 to S170 is, for example, Figure 3 The semiconductor device shown, but Figure 3 The semiconductor device shown is not intended to limit the semiconductor device formed in the embodiments of this application. For a detailed description of steps S110 to S170, please refer to the above description of the dummy gate formation method; it will not be repeated here.

[0072] The semiconductor device formation method provided in this application embodiment can effectively protect the pseudo-gate underlying structure without adjusting the trench depth of the previous process isolation structure and the thickness of the pseudo-gate sidewall in the recessed area on the substrate surface of the pseudo-gate formed by steps S110 to S140.

[0073] As described above, these embodiments of this application do not exhaustively cover all details, nor do they limit the application to merely the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A method for forming a pseudo-gate, comprising: A substrate is provided, wherein a recessed region is present on the surface of the substrate and a stacked structure for constituting a pseudo gate is formed on the substrate with the boundary located in the recessed region; A protective layer is formed on the substrate, the protective layer covering the sidewalls of the laminated structure and the surface of the substrate, and the protective layer forms a trench above the recessed area; A compensating material is spin-coated onto the protective layer and etched until the protective layer outside the trench is exposed and the compensating material inside the trench is retained. The protective layer and the compensation material within the trench are etched to form a pseudo gate sidewall by the protective layer covering the sidewalls of the stacked structure after the protective layer on the substrate surface is removed.

2. The method for forming a pseudo-gate according to claim 1, wherein, The compensation material is a liquid material that forms the bottom anti-reflective coating.

3. The method for forming a pseudo-gate according to claim 1, wherein, The protective layer uses a different material than the compensation material. The etched spin-coated compensation material includes etching the spin-coated compensation material through a first etching process, wherein the etching rate of the compensation material in the first etching process is greater than the etching rate of the protective layer.

4. The method for forming a pseudo-gate according to claim 3, wherein, The first etching process is a dry etching process using plasma gas, and the compensation material in the trench is retained by adjusting the etching bias voltage and the pressure of the plasma gas in the etching chamber.

5. The method for forming a pseudo-gate according to claim 3, wherein, Etching the protective layer and the compensation material in the trench includes: etching the protective layer and the compensation material in the trench through a second etching process, wherein the etching rate of the compensation material in the second etching process is equal to the etching rate of the protective layer.

6. The method for forming a pseudo-gate according to claim 1, wherein, A high-K dielectric layer with its boundary located in the recessed region is also formed on the substrate, and the high-K dielectric layer is located between the substrate surface and the stacked structure.

7. The method for forming a pseudo-gate according to claim 6, wherein, A barrier layer with its boundary located in the recessed region is also formed on the substrate, the barrier layer being located between the high-k dielectric layer and the stacked structure.

8. The method for forming a pseudo-gate according to claim 7, wherein, The barrier layer is made of titanium nitride.

9. The method for forming a pseudo-gate according to claim 1, wherein, The substrate includes adjacent isolation structures and active regions, and the recessed region is the area formed by the surface recess at the edge of the isolation structure adjacent to the active region.

10. A method for forming a semiconductor device, comprising: A pseudo-gate is formed by the pseudo-gate forming method according to any one of claims 1-9; Source and drain regions are formed in the substrates on both sides of the dummy gate using an ion implantation process. An interlayer dielectric layer with its top flush with the dummy gate is formed on the substrates on both sides of the dummy gate; The dummy gate is removed to form a groove in the interlayer dielectric layer, and a metal gate replacing the dummy gate is formed in the groove.

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