Semiconductor element with anti-ferroelectric spacer layer and manufacturing method thereof

Abstract

The invention discloses a semiconductor element and a manufacturing method of the semiconductor element. The semiconductor device includes: a substrate; a gate structure on the substrate; an internal spacer layer on the substrate and covering the gate structure; and a plurality of antiferroelectric spacer layers on both sides of the inner spacer layer and on the substrate, where the gate structure is located between the two sides of the inner spacer layer.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 662,012 (i.e., priority date "May 13, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device having an antiferroelectric spacer layer and a method for manufacturing the same. Background Technology

[0003] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components continues to shrink to meet the ever-increasing demands for computing power. However, this shrinkage process also introduces many problems, and these problems are constantly increasing. Therefore, challenges remain in improving quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The discussion in the preceding technical paragraphs is provided for background information only. The statements in the discussion in the preceding technical paragraphs are not an admission that the content disclosed in this paragraph constitutes prior art of this disclosure, and nothing in the discussion in the preceding technical paragraphs shall be construed as an admission that any part of this application, including the parts discussed in the preceding technical paragraphs, constitutes prior art of this disclosure. Summary of the Invention

[0005] One aspect of this disclosure provides a semiconductor device, comprising: a substrate; a gate structure located on the substrate; an inner spacer layer located on the substrate and covering the gate structure; and a plurality of antiferroelectric spacers located on two sides of the inner spacers and on the substrate, wherein the gate structure is located between the two sides of the inner spacers.

[0006] Another aspect of this disclosure provides a semiconductor device comprising: a substrate including a bottom semiconductor layer, a buried insulating layer on the bottom semiconductor layer, and a top semiconductor layer on the buried insulating layer; a gate structure on the top semiconductor layer; an inner spacer layer on the top semiconductor layer and covering the gate structure; and a plurality of antiferroelectric spacers on two sides of the inner spacers and on the top semiconductor layer, wherein the gate structure is located between the two sides of the inner spacers.

[0007] Another aspect of this disclosure provides a method for manufacturing a semiconductor device, comprising: providing a substrate; forming a gate structure on the substrate and forming an internal spacer layer covering the gate structure; and forming a plurality of antiferroelectric spacers on two sides of the gate structure.

[0008] Due to the design of the semiconductor device disclosed herein, the channel resistance during the off-state and the channel current during the on-state can be increased by employing multiple antiferroelectric spacers. Furthermore, by employing multiple lightly doped portions formed through epitaxial growth with designed dopant concentrations and substrate recessing, drain-induced barrier lowering (DIBL) can be reduced. This mitigation can lead to an enhanced on / off ratio and reduced random dopant variation, thereby enhancing the performance of the semiconductor device.

[0009] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0010] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the drawings that combine the embodiments and claims. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features can be arbitrarily increased or decreased.

[0011] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0012] Figures 2 to 14 This is a cross-sectional view illustrating the manufacturing process of a semiconductor device according to an embodiment of the present disclosure;

[0013] Figures 15 to 18 This is a cross-sectional view illustrating a semiconductor element subjected to an applied electric field according to some embodiments of the present disclosure;

[0014] Figures 19 to 20 This is a cross-sectional view illustrating semiconductor elements according to some embodiments of the present disclosure;

[0015] Figures 21 to 33 This is a cross-sectional view illustrating the manufacturing process of a semiconductor device according to an embodiment of the present disclosure; and

[0016] Figure 34 This is a cross-sectional view illustrating a semiconductor element according to another embodiment of the present disclosure.

[0017] The reference numerals in the attached figures are explained as follows:

[0018] 1A: Semiconductor components

[0019] 1B: Semiconductor components

[0020] 1C: Semiconductor components

[0021] 1D: Semiconductor components

[0022] 1E: Semiconductor components

[0023] 10: Method

[0024] 100: Substrate

[0025] 100BS: Bottom surface

[0026] 100TS: Top surface

[0027] 101: Bottom semiconductor layer

[0028] 103: Embedded insulation layer

[0029] 105: Top semiconductor layer

[0030] 107: Passage Area

[0031] 109: Isolation Layer

[0032] 111: Contact

[0033] 113: First insulating layer

[0034] 115: Well Area

[0035] 200: Gate structure

[0036] 201: Gate dielectric layer

[0037] 201BS: Bottom surface

[0038] 203: Bottom conductive layer of the gate

[0039] 205: Top conductive layer of the gate

[0040] 207: Gate capping layer

[0041] 301: Impurity Zone

[0042] 301-1: Lightly doped portion

[0043] 301-3: Main doped portion

[0044] 301T1: Top surface

[0045] 301T2: Top surface

[0046] 303: Precursor Layer

[0047] 305: Halo Intersection

[0048] 401: Internal spacer layer

[0049] 401S: Side View

[0050] 403: Antiferroelectric spacer

[0051] 405: External spacer layer

[0052] 501: First insulating material

[0053] 503: First conductive material

[0054] 505: Second conductive material

[0055] 507: Second Insulation Material

[0056] 509: Epitaxial layer

[0057] 511: Pre-impurity region

[0058] 601: First mask layer

[0059] AA: Active Zone

[0060] D1: Maximum Depth

[0061] R1: Groove

[0062] S11: Steps

[0063] S13: Steps

[0064] S15: Steps

[0065] T1: Thickness

[0066] T2: Thickness

[0067] W1: Width

[0068] W2: Width

[0069] W3: Width Detailed Implementation

[0070] This disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations described below are provided to simplify this disclosure. Of course, these are merely illustrative and not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature can include embodiments in which the first and second features are formed in direct contact, or embodiments in which an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, element symbols and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and is not in itself a limitation on the relationship between the various embodiments and / or configurations discussed.

[0071] Furthermore, for ease of description, spatially related terms such as "below," "under," "lower part," "above," "upper part," or other similar terms may be used herein to describe the relative relationship between one element or feature depicted in the diagram and another. In addition to the orientations shown in the diagrams, spatially related terms are intended to cover different orientations of the element during use or operation. The element may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptors used herein can be interpreted accordingly.

[0072] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it may be directly connected to or coupled to the other component or layer, or there may be intermediate components or intermediate layers.

[0073] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise stated, these terms are used only to distinguish one component from another. Thus, for example, the first component, first member, or first part discussed below may be referred to as the second component, second member, or second part without departing from the teachings of this disclosure.

[0074] Unless the context otherwise indicates, terms such as “identical,” “equal,” “plane,” or “coplanar” as used herein do not necessarily mean exactly identical orientations, layouts, locations, shapes, dimensions, quantities, or other measures of reference, but are intended to cover substantially identical orientations, layouts, locations, shapes, dimensions, quantities, or other measures of reference within an acceptable range of possible variations (e.g., due to manufacturing processes). The term “substantially” may be used herein to reflect this meaning. For example, articles described as “substantially identical,” “substantially equal,” or “substantially coplanar” may be exactly identical, equal, or coplanar, or may be substantially identical, equal, or coplanar within an acceptable range of possible variations (e.g., due to manufacturing processes).

[0075] In this disclosure, semiconductor element generally refers to an element that can operate using semiconductor properties, and electro-optic elements, light-emitting display elements, semiconductor circuits and electronic components are all included in the category of semiconductor element.

[0076] It should be noted that, in the description of this disclosure, "above" (or "up") corresponds to the direction of the arrow in the Z direction, and "below" (or "down") corresponds to the opposite direction of the arrow in the Z direction.

[0077] Figure 1 This is a flowchart illustrating a method 10 for manufacturing a semiconductor element 1A according to an embodiment of the present disclosure. Figures 2 to 14 This is a cross-sectional view illustrating the manufacturing process of a semiconductor element 1A according to an embodiment of the present disclosure.

[0078] See Figures 1 to 6 In step S11, a substrate 100 may be provided, an isolation layer 109 may be formed in the substrate 100 to define the active region AA, and a gate structure 200 may be formed on the active region AA and an internal spacer layer 401 may be formed to cover the gate structure 200.

[0079] See Figure 2 The substrate 100 may be a host semiconductor substrate composed entirely of at least one semiconductor material; this host semiconductor substrate does not contain any dielectric material, insulating layer, or conductive features. The host semiconductor substrate may be formed of materials such as: elemental semiconductors, such as silicon or germanium; compound semiconductors, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, other group III-V compound semiconductors or group II-VI compound semiconductors; or combinations thereof.

[0080] See Figure 2An isolation layer 109 can be formed in the substrate 100. A series of deposition processes can be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) on the substrate 100. Photolithography processes and subsequent etching processes, such as anisotropic dry etching processes, can be performed to form trenches that penetrate the pad oxide layer, the pad nitride layer and extend into the substrate 100. An insulating material can be deposited into these trenches, followed by planarization processes, such as chemical mechanical polishing, until the top surface of the substrate 100 is exposed to remove excess filler material and provide a substantially flat surface for subsequent process steps, while simultaneously forming the isolation layer 109. The insulating material can be, for example, silicon oxide or other suitable insulating materials. The isolation layer 109 can define an active region AA in the substrate 100.

[0081] It should be noted that, in the description of this disclosure, the surface of the element (or feature) at its highest vertical height along the Z-axis is referred to as the top surface of this element (or feature). The surface of the element (or feature) at its lowest vertical height along the Z-axis is referred to as the bottom surface of this element (or feature).

[0082] It should be noted that the active region AA may include a portion of the substrate 100 and the space above this portion of the substrate 100. Describing a component as disposed on the active region AA means that the component is disposed on the top surface 100TS of this portion of the substrate 100. Describing a component as disposed in (or within) the active region AA means that the component is disposed within the substrate 100; however, the top surface of the component may be flush with or coplanar with the top surface 100TS of this portion of the substrate 100. Describing a component as disposed above the active region AA means that the component is disposed above the top surface 100TS of this portion of the substrate 100.

[0083] See Figure 3 A first insulating material 501 can be formed on the substrate 100 and cover the active region AA. In some embodiments, the first insulating material 501 may include, for example, a high-k material, silicon oxide, or a combination thereof. In some embodiments, this first insulating material 501 may be formed by, for example, chemical vapor deposition, atomic layer deposition, or other suitable deposition processes.

[0084] In some embodiments, the high dielectric constant material may include a hafnium-containing material. The hafnium-containing material may be, for example, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In some embodiments, the high dielectric constant material may be, for example, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof.

[0085] See Figure 3A first conductive material 503 can be formed on this first insulating material 501. In some embodiments, the first conductive material 503 may include, for example, doped polycrystalline silicon, doped polycrystalline germanium, doped polycrystalline silicon-germanium, or a combination thereof. In some embodiments, this first conductive material 503 may be doped with a p-type dopant or an n-type dopant. n-type dopant may include, for example, antimony, arsenic, and phosphorus. p-type dopant may include, for example, boron, aluminum, gallium, and indium. In some embodiments, this first conductive material 503 may be formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0086] See Figure 3 A second conductive material 505 can be formed on the first conductive material 503. In some embodiments, the second conductive material 505 may include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., magnesium tantalum carbide), transition metal aluminum compounds, or combinations thereof. In some embodiments, the second conductive material 505 may be formed by, for example, physical vapor deposition, sputtering, electroplating, electroless plating, chemical vapor deposition, atomic layer deposition, or other suitable deposition processes.

[0087] See Figure 3 A second insulating material 507 can be formed on this second conductive material 505. In some embodiments, the second insulating material 507 may include, for example, an oxide, a nitride, or an oxide oxynitride. In some embodiments, the second insulating material 507 may include silicon nitride or silicon oxide. In some embodiments, this second insulating material 507 may be formed by, for example, chemical vapor deposition or other suitable deposition processes.

[0088] See Figure 3 A first mask layer 601 may be formed on this second insulating material 507. In some embodiments, the first mask layer 601 may be a photoresist layer. In some embodiments, the first mask layer 601 may include a pattern of the gate structure 200.

[0089] See Figure 4An etching process can be performed using a first mask layer 601 as a mask to remove portions of the second insulating material 507, the second conductive material 505, and the first conductive material 503. In some embodiments, the etching process can be an anisotropic dry etching process. The remaining first conductive material 503 can be referred to as the gate bottom conductive layer 203. The gate bottom conductive layer 203 can be disposed on this first insulating material 501. The remaining second conductive material 505 can be referred to as the gate top conductive layer 205. The gate top conductive layer 205 can be disposed on the gate bottom conductive layer 203. The remaining second insulating material 507 can be referred to as the gate capping layer 207. The capping layer 207 can be disposed on the gate top conductive layer 205. In some embodiments, the width of the gate capping layer 207, the width of the gate top conductive layer 205, and the width of the gate bottom conductive layer 203 can be substantially the same.

[0090] See Figure 5 An internal spacer layer 401 can be compliantly formed to cover the stack of the gate bottom conductive layer 203, the gate top conductive layer 205, and the gate capping layer 207. The internal spacer layer 401 may also cover a portion of this first insulating material 501. In other words, the internal spacer layer 401 can be formed on this first insulating material 501 and surround the stack of the gate bottom conductive layer 203, the gate top conductive layer 205, and the gate capping layer 207. In some embodiments, the internal spacer layer 401 may be formed of the same material as the gate capping layer 207. In some embodiments, the internal spacer layer 401 may include, for example, a nitride or an oxide nitride. In some embodiments, the internal spacer layer 401 may include silicon nitride, silicon oxynitride, or silicon nitride oxide. In some embodiments, the internal spacer layer 401 may be formed by, for example, chemical vapor deposition or other suitable deposition processes and subsequent anisotropic etching processes.

[0091] It should be noted that silicon oxynitride in this disclosure refers to a substance containing silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance containing silicon, oxygen, and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0092] See Figure 6An etching process can be performed using the internal spacer layer 401 as a mask to remove a portion of the first insulating material 501. In some embodiments, the etching process can be an anisotropic dry etching process. The active region AA can be exposed after the etching process. The remaining first insulating material 501 can be referred to as the gate dielectric layer 201. In some embodiments, the width W1 of the gate dielectric layer 201 can be greater than the width W2 of the bottom conductive layer 203. The gate dielectric layer 201, the bottom conductive layer 203, the top conductive layer 205, and the gate capping layer 207 together constitute the gate structure 200. In some embodiments, the thickness T1 of the gate structure 200 can be between approximately 70 nm and approximately 55 nm.

[0093] See Figure 1 and Figures 7 to 9 In step S13, multiple grooves R1 can be formed in the active region AA, multiple epitaxial layers 509 can be formed in the multiple grooves R1, multiple antiferroelectric spacers 403 can be formed on the side 401S of the inner spacer layer 401 and partially shield the multiple epitaxial layers 509, and multiple epitaxial layers 509 can be partially removed to form multiple precursor layers 303.

[0094] See Figure 7 An etching process can be performed to recess the active region AA to form a plurality of grooves R1. In some embodiments, the etching process can be an isotropic etching process. In some embodiments, the etching process can be a wet etching process. During the etching process, a portion of the active region AA located below the gate dielectric layer 201 can also be etched laterally, exposing a portion of the bottom surface 201BS of the gate dielectric layer 201 by means of the plurality of grooves R1. In some embodiments, the plurality of grooves R1 can be formed from the top surface 100TS of the substrate 100 toward the bottom surface 100BS of the substrate 100, separated from each other, and defining a channel region 107. The channel region 107 can be disposed between the plurality of grooves R1 and located directly below the gate dielectric layer 201. The width W3 of the channel region 107 can be smaller than the width W1 of the gate dielectric layer 201.

[0095] In some embodiments, the etching process can be a wet etching process comprising a mixture of nitric acid and hydrofluoric acid. The wet etching process can be initiated by nitric acid, which forms a layer of silicon dioxide on silicon (i.e., the active region AA), and the hydrofluoric acid dissolves and removes the silicon dioxide. In some embodiments, water can be used to dilute the etchant, and acetic acid can be used as a buffer.

[0096] In some embodiments, a pre-cleaning process may be performed before recessing the plurality of grooves R1. The pre-cleaning process may include exposing the active area AA to a solution comprising fluoride components, oxidants, and inorganic acids.

[0097] See Figure 8 Multiple epitaxial layers 509 can be compliantly formed on the active region AA and within multiple recesses R1. In some embodiments, the multiple epitaxial layers 509 may include, for example, silicon, germanium, or silicon-germanium. In some embodiments, the multiple epitaxial layers 509 may be doped with n-type or p-type dopants. In some embodiments, the dopant concentration of the multiple epitaxial layers 509 may be between about 2E20 atoms / cm³. 3 With approximately 4E20 atoms / cm 3 Between, or approximately 3E20 atoms / cm 3 In some embodiments, the electrical type of the plurality of epitaxial layers 509 may be n-type or p-type, depending on the dopants doped during the formation of the plurality of epitaxial layers 509.

[0098] In some embodiments, multiple epitaxial layers 509 can be grown by exposing the active region AA to a radio frequency plasma originating from an etching gas flow. In some embodiments, the etching gas may include a halogen. In some embodiments, the etching gas may include a tetrafluorosilane. In some embodiments, the flow rate of the gas flow is between about 30 standard cubic centimeters per minute (sccm) and about 40 sccm. In some embodiments, the radio frequency power of the radio frequency plasma may be between about 300 W and about 450 W. In some embodiments, the exposure time to the radio frequency plasma may be between about 1 second and about 2 minutes.

[0099] In some embodiments, a plurality of epitaxial layers 509 may be formed by a deposition process including exposing the active region AA to a deposition gas comprising at least a silicon source and a carrier gas. The deposition gas may also include a dopant source.

[0100] In detail, the deposition process can be achieved by using materials containing... Figure 7 The process chamber for the intermediate semiconductor device shown is adjusted to a predetermined temperature and pressure to begin. The temperature can be designed according to the specific process being performed. In some embodiments, the process chamber can be maintained at a temperature in the range of about 250°C to about 1000°C, about 500°C to about 800°C, or about 550°C to about 750°C. The appropriate temperature for performing the deposition process can depend on the specific precursor used to deposit the multiple epitaxial layers 509. In some embodiments, the process chamber can typically be maintained at a pressure of about 0.1 Torr to about 200 Torr, or about 1 Torr to about 50 Torr. The pressure may vary during the deposition process, but is generally kept constant.

[0101] After adjusting the process chamber to the appropriate temperature and pressure, such as Figure 7The intermediate semiconductor element shown can be exposed to a deposition gas containing a silicon source and a carrier gas to form multiple epitaxial layers 509. In some embodiments, the active region AA can be exposed to the deposition gas for a time interval ranging from about 0.5 seconds to about 30 seconds, from about 1 second to about 20 seconds, or from about 5 seconds to about 10 seconds. The specific exposure time of the deposition process can depend on the specific precursors, temperature, and pressure used in the deposition process.

[0102] In some embodiments, the deposition gas used to deposit the plurality of epitaxial layers 509 may include at least a silicon source and a carrier gas. In some embodiments, the deposition gas may also include a dopant compound to provide a dopant source, such as boron, arsenic, phosphorus, gallium, and / or aluminum.

[0103] In some embodiments, the silicon source can typically be supplied to the process chamber at a rate ranging from about 5 sccm to about 500 sccm, from about 10 sccm to about 300 sccm, or from about 50 sccm to about 200 sccm. For example, the silicon source can be supplied to the process chamber at a rate of about 100 sccm.

[0104] In some embodiments, the silicon source may include silanes, halogenated silanes, and / or organosilanes.

[0105] In some embodiments, the silane may include silane (SiH4) and silane having the experimental formula Si x H (2x+2) Higher silanes, such as silane (Si₂H₆), propane (Si₃H₈), and butane (Si₄H₂O), are also mentioned. 10 ) and other silanes.

[0106] In some embodiments, silane halide may include those having the experimental formula X' y Si x H (2x+2-y) Compounds in which X' is fluorine (F), chlorine (Cl), bromine (Br) or iodine (I), for example, hexachlorosilane (Si2Cl6), tetrachlorosilane (SiCl4), dichlorosilane (Cl2SiH2) and trichlorosilane (Cl3SiH).

[0107] In some embodiments, organosilanes may include those having the experimental formula R y Si x H (2x+2-y) The compound wherein R is methyl, ethyl, propyl or butyl, for example methylsilane ((CH3)SiH3), dimethylsilane ((CH3)2SiH2), ethylsilane ((CH3CH2)SiH3), methylsilane ((CH3)Si2H5), dimethylsilane ((CH3)2Si2H4) and hexamethylsilane ((CH3)6Si2).

[0108] In this embodiment, the silicon source may include silane, dichlorosilane, and ethylsilane.

[0109] The silicon source can be provided into the process chamber along with a carrier gas. In some embodiments, the carrier gas may have a flow rate in the range of about 1 slm (standard liters per minute) to about 100 slm, about 5 slm to about 75 slm, or about 10 slm to about 50 slm. In this embodiment, the flow rate of the carrier gas may be, for example, about 25 slm.

[0110] The carrier gas can be selected based on the precursor used (e.g., silicon source) and / or the process temperature during the deposition process. Typically, the carrier gas can be the same throughout the deposition process. However, some embodiments may use different carrier gases during the deposition process.

[0111] In some embodiments, the carrier gas may include nitrogen, hydrogen, argon, helium, or combinations thereof. In some embodiments, an inert carrier gas may be preferred, and may include nitrogen, argon, helium, or combinations thereof.

[0112] In some embodiments, particularly those characterized by low-temperature (e.g., <800°C) processes, nitrogen can be used as the carrier gas. Nitrogen remains inert during the low-temperature deposition process. Therefore, nitrogen is not integrated into the multiple epitaxial layers 509 during the low-temperature deposition process. Furthermore, the nitrogen carrier gas does not form a hydrogen-terminated surface as a hydrogen carrier gas would. Hydrogen-terminated surfaces formed by the adsorption of hydrogen carrier gas on the surface inhibit the growth rate of the multiple epitaxial layers 509. Finally, because nitrogen is significantly cheaper than hydrogen, argon, or helium, this low-temperature process using nitrogen as the carrier gas offers economic advantages.

[0113] See Figure 9 Multiple antiferroelectric spacer layers 403 can be formed and cover the sides 401S of the inner spacer layer 401. The multiple antiferroelectric spacer layers 403 may also partially cover the multiple epitaxial layers 509. In some embodiments, the antiferroelectric spacer layers 403 may be in a crystalline state. In some embodiments, the antiferroelectric spacer layers 403 may be tetragonal, and a phase transition may occur between the tetragonal and orthorhombic phases when an electric field is applied.

[0114] In some embodiments, the antiferroelectric spacer layer 403 may include hafnium and oxygen or zirconium and oxygen. In some embodiments, the antiferroelectric spacer layer 403 may include hafnium oxide. In some embodiments, the antiferroelectric spacer layer 403 may include zirconium oxide. In some embodiments, the antiferroelectric spacer layer 403 may include at least one of hafnium and zirconium, and may include one or more additional dopants, such as silicon, aluminum, germanium, magnesium, calcium, strontium, barium, titanium, yttrium, lanthanum, cerium, or rare earth elements. This additional dopant may be incorporated into the hafnium-containing material to induce an antiferroelectric phase and / or adjust the voltage position of the local capacitance / polarization / k-value boost. In some embodiments, the concentration of the dopant may be between about 0.2 mol% and about 30 mol%, or between about 0.5 mol% and about 20 mol%. In some embodiments, the antiferroelectric spacer layer 403 may be composed of Hf a X b O2 material, where X represents one of zirconium (Zr), silicon (Si), and aluminum (Al). In one example, X may represent zirconium and a < 0.5, b > 0.5, for example, a < 0.7, b > 0.3. In another example, X may represent silicon and 0.05 < b < 0.2, 0.88 < a < 0.95. In another example, b may also be in the range of 0.05 < b < 0.12. In another example, X may represent aluminum and 0.05 < b < 0.12, 0.88 < a < 0.95.

[0115] In some embodiments, a layer of antiferroelectric material (not shown) may be conformally formed over the substrate 100 to cover the isolation layer 109, the plurality of epitaxial layers 509, and the internal spacer layer 401. In some embodiments, this layer of antiferroelectric material may be formed by, for example, atomic layer deposition, chemical vapor deposition, or other suitable deposition processes. In some embodiments, atomic layer deposition may utilize alkylamide precursors bis(ethylmethylamino)hafnium and bis(ethylmethylamino)zirconium. Subsequently, an anisotropic etching process may be performed to remove a portion of the antiferroelectric material layer. The remaining antiferroelectric material may be referred to as the plurality of antiferroelectric spacer layers 403.

[0116] In some embodiments, after the etching process, the antiferroelectric spacer layer 403 may be amorphous. A heat treatment may be performed to induce crystallization of the antiferroelectric spacer layer 403. In some embodiments, the temperature of the heat treatment is between about 250 °C and about 1200 °C, between about 250 °C and about 800 °C, or between about 500 °C and about 1100 °C. In some embodiments, the heat treatment may be rapid thermal annealing, laser spike annealing, or flash lamp annealing. In some embodiments, the heat treatment may be performed after forming the plurality of impurity regions 301, which will be described below.

[0117] See Figure 10Multiple antiferroelectric spacers 403 can be used as masks for an etching process to remove portions of the multiple epitaxial layers 509. During the etching process, the multiple epitaxial layers 509 can be exposed to etching gas for a time interval ranging from about 10 seconds to about 90 seconds, from about 20 seconds to about 60 seconds, or from about 30 seconds to about 45 seconds. After the etching process, the remaining epitaxial layers 509 can be referred to as multiple precursor layers 303. The multiple precursor layers 303 can have the same electrical type as the multiple epitaxial layers 509.

[0118] In some embodiments, the etching gas may include at least one etchant and a carrier gas. The etchant may be supplied to the process chamber at a rate in the range of about 10 sccm to about 700 sccm, about 50 sccm to about 500 sccm, or about 100 sccm to about 400 sccm. For example, the etchant flow rate may be about 200 sccm.

[0119] The etchants used in the etching gas may include chlorine, hydrogen chloride, boron trichloride, carbon tetrachloride, chlorine trifluoride, or combinations thereof.

[0120] The etchant is typically supplied to the process chamber along with a carrier gas. The carrier gas may have a flow rate in the range of about 1 slm to about 100 slm, about 5 slm to about 75 slm, or about 10 slm to about 50 slm. For example, the flow rate of the carrier gas may be about 25 slm. In some embodiments, the carrier gas may include nitrogen, hydrogen, argon, helium, or combinations thereof.

[0121] In some embodiments, an inert carrier gas is preferred and may include nitrogen, argon, helium, and combinations thereof. The carrier gas may be selected based on the specific precursors and / or temperatures used during the deposition of the multiple epitaxial layers 509. The same carrier gas can typically be used during the deposition of the multiple epitaxial layers 509 and subsequent etching processes. However, in some embodiments, different carrier gases may be applied during the deposition of the multiple epitaxial layers 509 and subsequent etching processes.

[0122] In some embodiments, a preferred etchant may be chlorine gas, particularly when the deposition process of the plurality of epitaxial layers 509 is performed at low temperatures (e.g., <800°C). For example, an etching process using an etching gas containing chlorine as an etchant and nitrogen as a carrier gas can be performed at temperatures ranging from about 500°C to about 750°C. In another example, an etching process using an etching gas containing both chlorine and nitrogen can be performed at temperatures ranging from about 250°C to about 500°C.

[0123] See Figure 1 and Figures 11 to 14In step S15, multiple pre-impurity regions 511 can be formed in the active region AA, and heat treatment can be performed to transform multiple precursor layers 303 into multiple lightly doped portions 301-1, and multiple pre-impurity regions 511 into multiple main doped portions 301-3. An external spacer layer 405 can be formed to cover the active region AA, and multiple contacts 111 can be formed on the multiple main doped portions 301-3.

[0124] See Figure 11 A value-laying process can be performed to form a plurality of pre-impurity regions 511 in the active region AA. In some embodiments, the plurality of pre-impurity regions 511 may include n-type dopants or p-type dopants. In some embodiments, the electrical type of the plurality of pre-impurity regions 511 may have the same electrical type as the plurality of precursor layers 303. The plurality of pre-impurity regions 511 may be disposed adjacent to the plurality of precursor layers 303 respectively and correspondingly.

[0125] See Figure 12 Heat treatment can be performed to activate multiple precursor layers 303 and multiple pre-impurity regions 511. In some embodiments, the heat treatment temperature can be between about 800°C and about 1250°C. In some embodiments, the heat treatment can have a process duration between about 1 millisecond and about 500 milliseconds. In some embodiments, the heat treatment can include, for example, rapid thermal annealing, laser-spike annealing, or flash annealing. In some embodiments, the heat treatment can also induce the crystallization of multiple antiferroelectric spacer layers 403.

[0126] After heat treatment, the plurality of precursor layers 303 can be transformed into a plurality of lightly doped portions 301-1, and the plurality of pre-impurity regions 511 can be transformed into a plurality of main doped portions 301-3. The plurality of lightly doped portions 301-1 and the plurality of main doped portions 301-3 together constitute a plurality of impurity regions 301. In some embodiments, during heat treatment, the boundaries between the precursor layers 303 and the pre-impurity regions 511 may merge and fuse together due to diffusion to form impurity regions 301. In some embodiments, the dopant concentration of the plurality of lightly doped portions 301-1 may be less than the dopant concentration of the plurality of main doped portions 301-3.

[0127] In some embodiments, a plurality of lightly doped portions 301-1 may be disposed in the active region AA and located below the plurality of antiferroelectric spacer layers 403 and the gate dielectric layer 201. A channel region 107 may be disposed between the plurality of lightly doped portions 301-1 and located below the gate dielectric layer 201. In some embodiments, the thickness T2 of the plurality of lightly doped portions 301-1 may be between about 20 nm and about 25 nm. In some embodiments, the ratio of the thickness T1 of the gate structure 200 to the maximum depth D1 between the top surface 100TS of the substrate 100 and the top surface 301T1 of the plurality of lightly doped portions 301-1 may be between about 7.00 and about 3.60, between about 7.00 and about 4.60, or between about 5.50 and about 3.60. In some embodiments, the ratio of the thickness T1 of the gate structure 200 to the thickness T2 of the plurality of lightly doped portions 301-1 may be between about 3.50 and about 2.20, between about 3.50 and about 2.80, or between about 2.80 and about 2.75. In some embodiments, the plurality of main doped portions 301-3 may be disposed in the active region AA and respectively and correspondingly connected to the plurality of main doped portions 301-3. The plurality of main doped portions 301-3 may be exposed through the plurality of recesses R1. The top surface 301T1 of the plurality of lightly doped portions 301-1 and the top surface 301T2 of the plurality of main doped portions 301-3 may be coplanar with the plurality of recesses R1.

[0128] In some embodiments, heat treatment may be integrated into the fabrication process used to form a plurality of pre-impurity regions 511.

[0129] In some alternative embodiments, the lightly doped portion 301-1 can be formed by directly performing one (or more) value-layout processes on the substrate 100.

[0130] See Figure 13 An outer spacer layer 405 can be compliantly formed to cover a plurality of antiferroelectric spacer layers 403, an inner spacer layer 401, and a plurality of host doped portions 301-3. In other words, the outer spacer layer 405 can be formed on the plurality of host doped portions 301-3 and surround the plurality of antiferroelectric spacer layers 403 and the inner spacer layer 401. In some embodiments, the outer spacer layer 405 can be formed of the same material as the inner spacer layer 401. In some embodiments, the outer spacer layer 405 can include, for example, nitrides or oxides of nitride. In some embodiments, the outer spacer layer 405 can include silicon nitride, silicon oxynitride, or silicon nitride oxide. In some embodiments, the outer spacer layer 405 can be formed by, for example, chemical vapor deposition or other suitable deposition processes and a subsequent anisotropic etching process.

[0131] See Figure 14A first insulating layer 113 can be formed on the substrate 100 to cover the outer spacer layer 405 and the isolation layer 109. A planarization process, such as chemical mechanical polishing, can be performed to remove excess material and provide a substantially flat surface for subsequent process steps. In some embodiments, the first insulating layer 113 can be formed of materials such as silicon oxide, borosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, or combinations thereof. Low-k dielectric materials can have a dielectric constant less than 3.0 or even less than 2.5. In some embodiments, undoped silicate glass can be represented as SiO₂. x x can be between 1.4 and 2.1. In some embodiments, the first insulating layer 113 can be formed by, for example, chemical vapor deposition or other suitable deposition processes.

[0132] See Figure 14 Multiple contacts 111 can be formed along the first insulating layer 113 and the outer spacer layer 405, and are respectively and correspondingly formed on multiple body doped portions 301-3. In some embodiments, the multiple contacts 111 can be formed of materials such as doped polycrystalline silicon, doped polycrystalline germanium, doped polycrystalline silicon germanium, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, or magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof.

[0133] By employing multiple lightly doped portions 301-1 formed through epitaxial growth with designed dopant concentrations, and by recessing the substrate 100, drain-induced barrier lowering (DIBL) can be reduced. This mitigation can lead to an enhanced on / off ratio and reduced random dopant variation, thereby enhancing the performance of the semiconductor device 1A.

[0134] Figures 15 to 18 This is a cross-sectional view illustrating a semiconductor element subjected to an electric field according to some embodiments of the present disclosure.

[0135] See Figure 15The plurality of impurity regions 301 can be n-type. One of the plurality of impurity regions 301 on the left can be referred to as the source, and one of the plurality of impurity regions 301 on the right can be referred to as the drain. During the off-state of the semiconductor device 1A, a positive voltage (or positive electric field) is applied to the drain through the right-side contact 111, while the source and gate structure 200 are grounded (or zero voltage is applied). Since there is no electric field between the gate structure 200 and the source, the left-side antiferroelectric spacer layer 403 can remain non-polar. Conversely, a dipole (indicated by plus and minus signs) is formed in the right-side antiferroelectric spacer layer 403. This dipole can repel charges (e.g., electrons) near the drain in the channel region 107, thereby increasing the channel resistance during the off-state.

[0136] See Figure 16 The plurality of impurity regions 301 can be n-type. One of the plurality of impurity regions 301 on the left can be referred to as the source, and one of the plurality of impurity regions 301 on the right can be referred to as the drain. During the conduction state of the semiconductor device 1A, a positive voltage (or positive electric field) is applied to the drain through the right-side contact 111 and to the gate structure 200, while the source is grounded (or zero voltage is applied). Since there is no electric field between the gate structure 200 and the drain, the right-side antiferroelectric spacer layer 403 can remain non-polar. Conversely, a dipole (indicated by plus and minus signs) is formed in the left-side antiferroelectric spacer layer 403. This dipole can attract charges (e.g., electrons) in the channel region 107 near the source, thereby increasing the channel current during the conduction state.

[0137] See Figure 17 The plurality of impurity regions 301 can be p-type. One of the plurality of impurity regions 301 on the left can be referred to as the source, and one of the plurality of impurity regions 301 on the right can be referred to as the drain. During the off-state of the semiconductor device 1A, a negative voltage (or negative electric field) is applied to the drain through the right-side contact 111, while the source and gate structure 200 are grounded (or zero voltage is applied). Since there is no electric field between the gate structure 200 and the source, the left-side antiferroelectric spacer layer 403 can remain non-polar. Conversely, a dipole (indicated by plus and minus signs) is formed in the right-side antiferroelectric spacer layer 403. This dipole can repel charges (e.g., holes) near the drain in the channel region 107, thereby increasing the channel resistance during the off-state.

[0138] See Figure 18The plurality of impurity regions 301 can be p-type. One of the plurality of impurity regions 301 on the left can be referred to as the source, and one of the plurality of impurity regions 301 on the right can be referred to as the drain. During the conduction state of the semiconductor device 1A, a negative voltage (or negative electric field) is applied to the drain through the right-side contact 111 and to the gate structure 200, while the source is grounded (or zero voltage is applied). Since there is no electric field between the gate structure 200 and the drain, the right-side antiferroelectric spacer layer 403 can remain non-polar. Conversely, a dipole is formed in the left-side antiferroelectric spacer layer 403. This dipole can attract charges (e.g., holes) in the channel region 107 near the source, thereby increasing the channel current during the conduction state.

[0139] Figures 19 to 20 This is a cross-sectional view illustrating semiconductor element 1B and semiconductor element 1C according to some embodiments of the present disclosure.

[0140] See Figure 19 Semiconductor element 1B can have similar characteristics to Figure 14 The structure shown. In Figure 19 The same or similar Figure 14 The components are already marked with similar component symbols, and repeated descriptions are omitted.

[0141] Semiconductor device 1B may include a well region 115. The well region 115 may be disposed in the active region AA. A plurality of impurity regions 301 and a channel region 107 may be disposed in the well region 115. In some embodiments, the well region 115 may have an electrical type opposite to that of the plurality of impurity regions 301 (n-type or p-type).

[0142] See Figure 20 Semiconductor element 1C can have similar characteristics to Figure 14 The structure shown. In Figure 20 The same or similar Figure 14 The components are already marked with similar component symbols, and repeated descriptions are omitted.

[0143] Semiconductor device 1C may include multiple halo junctions 305. The halo junctions 305 may be disposed between the lightly doped portion 301-1 and the bulk-doped portion 301-3. The halo junctions 305 may have the same electrical type as the lightly doped portion 301-1 and the bulk-doped portion 301-3. The resistance of the channel region 107 can be further adjusted via the halo junctions 305.

[0144] Figures 21 to 33 This is a cross-sectional view illustrating the manufacturing process of a semiconductor device 1D according to another embodiment of the present disclosure.

[0145] See Figure 21The substrate 100 may include a semiconductor-on-insulator structure, which consists of a bottom semiconductor layer 101, a buried insulating layer 103, and a top semiconductor layer 105 from bottom to top. The bottom semiconductor layer 101 and the top semiconductor layer 105 may be made of... Figure 2 The substrate 100 shown is formed of the same material. The buried insulating layer 103 can be a crystalline or amorphous dielectric material, such as an oxide and / or a nitride. For example, the buried insulating layer 103 can be a dielectric oxide, such as silicon oxide. As another example, the buried insulating layer 103 can be a dielectric nitride, such as silicon nitride or boron nitride. Yet another example, the buried insulating layer 103 can comprise a stack of dielectric oxides and dielectric nitrides in any order, which is a stack of silicon oxide and either silicon nitride or boron nitride. In some embodiments, the buried insulating layer 103 can have a thickness between about 10 nm and 200 nm.

[0146] See Figure 21 It can utilize similar Figure 2 The process shown forms an isolation layer 109 in the top semiconductor layer 105 and defines an active region AA, which will not be described again here.

[0147] See Figure 22 It can utilize similar Figure 3 The process shown involves sequentially forming a first insulating material 501, a first conductive material 503, a second conductive material 505, a second insulating material 507, and a first mask layer 601 on the top semiconductor layer 105, which will not be described again here.

[0148] See Figure 23 It can utilize similar Figure 4 The process shown forms a bottom conductive layer 203, a top conductive layer 205, and a gate capping layer 207, which will not be described again here.

[0149] See Figure 24 It can utilize similar Figure 5 The process shown forms an internal spacer layer 401 to cover the stack of the bottom gate conductive layer 203, the top gate conductive layer 205, and the gate capping layer 207, which will not be described again here.

[0150] See Figures 5 to 27 It can utilize similar Figures 6 to 8 The process shown forms a gate dielectric layer 201, multiple grooves R1, and multiple epitaxial layers 509, which will not be described again here.

[0151] See Figures 28 to 30 It can utilize similar Figures 9 to 11The process shown forms multiple antiferroelectric spacer layers 403, multiple precursor layers 303, and multiple pre-impurity regions 511, which will not be described again here.

[0152] See Figures 31 to 33 It can utilize similar Figures 12 to 14 The process shown forms multiple impurity regions 301, an outer spacer layer 405, a first insulating layer 113, and multiple contacts 111, which will not be described again here.

[0153] Figure 34 This is a cross-sectional view illustrating a semiconductor element according to another embodiment of the present disclosure.

[0154] See Figure 34 Semiconductor element 1E can have with Figure 29 The structure shown is similar to the one described. Figure 34 The same or similar Figure 29 The components are already marked with similar component symbols, and repeated descriptions are omitted.

[0155] Semiconductor device 1E may include multiple halo junctions 305. The halo junctions 305 may be disposed between the lightly doped portion 301-1 and the bulk-doped portion 301-3. The halo junctions 305 may have the same electrical type as the lightly doped portion 301-1 and the bulk-doped portion 301-3. The resistance of the channel region 107 can be further adjusted via the halo junctions 305.

[0156] One aspect of this disclosure provides a semiconductor device, comprising: a substrate; a gate structure located on the substrate; an inner spacer layer located on the substrate and covering the gate structure; and a plurality of antiferroelectric spacers located on two sides of the inner spacers and on the substrate, wherein the gate structure is located between the two sides of the inner spacers.

[0157] Another aspect of this disclosure provides a semiconductor device comprising: a substrate including a bottom semiconductor layer, a buried insulating layer on the bottom semiconductor layer, and a top semiconductor layer on the buried insulating layer; a gate structure on the top semiconductor layer; an inner spacer layer on the top semiconductor layer and covering the gate structure; and a plurality of antiferroelectric spacers on two sides of the inner spacers and on the top semiconductor layer, wherein the gate structure is located between the two sides of the inner spacers.

[0158] Another aspect of this disclosure provides a method for manufacturing a semiconductor device, comprising: providing a substrate; forming a gate structure on the substrate and forming an internal spacer layer covering the gate structure; and forming a plurality of antiferroelectric spacers on two sides of the gate structure.

[0159] Due to the design of the semiconductor device disclosed herein, the channel resistance during the off-state and the channel current during the on-state can be increased by employing multiple antiferroelectric spacer layers 403. Furthermore, by employing multiple lightly doped portions 301-1 formed through epitaxial growth with designed dopant concentrations and the recessing of the substrate 100, drain-induced barrier lowering (DIBL) can be reduced. This mitigation can lead to an enhanced on / off ratio and reduced random dopant variation, thereby enhancing the performance of the semiconductor device 1A.

[0160] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0161] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: One substrate; A gate structure is located on the substrate; An internal spacer layer is located on the substrate and covers the gate structure; as well as Multiple antiferroelectric spacers are located on two sides of the inner spacer and on the substrate, wherein the gate structure is located between the two sides of the inner spacer.

2. The semiconductor device of claim 1, wherein the plurality of antiferroelectric spacers comprise hafnium and oxygen or comprise zirconium and oxygen.

3. The semiconductor device of claim 1, wherein the plurality of antiferroelectric spacer layers are in a crystalline state.

4. The semiconductor device of claim 1, wherein the plurality of antiferroelectric spacer layers are tetragonal phase.

5. The semiconductor device of claim 1, wherein the plurality of antiferroelectric spacer layers comprise a plurality of dopants.

6. The semiconductor device of claim 5, wherein the plurality of dopants includes silicon, aluminum, germanium, magnesium, calcium, strontium, barium, or titanium.

7. The semiconductor device of claim 1, further comprising: Multiple grooves are recessed from a top surface of the substrate, adjacent to the gate structure, and define a channel region, wherein the channel region is located between the multiple grooves and below the gate structure.

8. The semiconductor device of claim 7, further comprising a plurality of impurity regions, wherein the plurality of impurity regions includes: Multiple lightly doped portions are located within the substrate and spaced apart from each other, wherein the channel region is located between the multiple lightly doped portions; as well as Multiple main doped portions are located within the substrate and are respectively connected to the multiple lightly doped portions.

9. The semiconductor device of claim 8, wherein the ratio of a thickness of the gate structure to a maximum depth between the top surface of the substrate and a top surface of the plurality of lightly doped portions is between about 7.00 and about 3.

60.

10. The semiconductor device of claim 8, wherein the ratio of a thickness of the gate structure to a thickness of the plurality of lightly doped portions is between about 3.50 and about 2.20.

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