Package structure

Abstract

A package structure according to the present disclosure includes a package substrate, an interposer disposed over the package substrate, a photonic die disposed over the interposer, a memory structure disposed over the interposer and including a controller die, a system die disposed over the interposer and partially overlapping the photonic die and the controller die; and a cap covering the system die, the memory structure, and the photonic die. The system die includes micro-bumps extending from a bottom surface of the system die to a top surface of the controller die.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a package structure. BACKGROUND

[0002] Three-dimensional integrated circuit (3DIC) technology improves the performance and efficiency of chips by bringing peripheral chips closer to a central system on a chip (SoC) and enabling edge-to-edge 3D connections, while also improving the stability and reliability of systems. 3DIC technology also provides increased chip density, improved area utilization efficiency, and provides higher performance and efficiency. In addition, integrating different types of chips (e.g., such as CPUs, GPUs, and memories) can provide more efficient data processing and storage, thereby improving the overall performance and efficiency of systems. On the other hand, by integrating optical chips with electronic chips, optical integration can achieve more efficient data transmission and communication, reduce transmission loss and thermal effects, and achieve higher bandwidth and lower power consumption by taking advantage of the high speed and low latency characteristics of optical transmission. SUMMARY

[0003] Embodiments of the present disclosure provide a package structure, including: a package substrate; a interposer disposed above the package substrate; a photonic die disposed above the interposer; a memory structure disposed above the interposer and including a controller die; a system die disposed above the interposer and partially overlapping the photonic die and the controller die; and a cap covering the system die, the memory structure, and the photonic die, wherein the system die includes micro-bumps extending from a bottom surface of the system die to a top surface of the controller die.

[0004] Another embodiment of the present disclosure provides a package structure, including: a package substrate; a interposer disposed above the package substrate; a first photonic die and a second photonic die disposed above the interposer and spaced apart from each other along a first direction; a first memory structure and a second memory structure disposed above the interposer and spaced apart from each other along a second direction perpendicular to the first direction, the first memory structure including a first controller die and the second memory structure including a second controller die; a system die disposed above the interposer and partially overlapping the first controller die, the second controller die, the first photonic die, and the second photonic die; and a cap covering the system die, the first memory structure, the second memory structure, the first photonic die, and the second photonic die, wherein the system die includes micro-bumps extending from a bottom surface of the system die to top surfaces of the first controller die and the second controller die.

[0005] Yet another embodiment of the present disclosure provides a package structure, comprising: a package substrate; a interposer disposed above the package substrate; a system die disposed above the interposer; a first photonic die and a second photonic die disposed above the system die and overhanging the system die; a first memory structure and a second memory structure disposed above the interposer, the first memory structure comprising a first controller die and a first memory stack bonded to the first controller die, and the second memory structure comprising a second controller die and a second memory stack bonded to the second controller die; and a cap covering the system die, the first memory structure, the second memory structure, the first photonic die, and the second photonic die, wherein portions of the first controller die and the second controller die span a top surface of the system die.

[0006] Embodiments of the present disclosure provide 3D integrated circuit devices and related methods. BRIEF DESCRIPTION OF DRAWINGS

[0007] The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized, however, that various modifications, additions and substitutions are also possible within the scope of the disclosure, in accordance with the standard practice in the art. For example, the

[0008] Figure 1 is a top perspective view of a package structure in accordance with various aspects of the present disclosure.

[0009] Figure 2 is a top perspective view of a package structure in accordance with various aspects of the present disclosure. Figure 1 is a cross-sectional view of a package structure in

[0010] Figure 3 is a cross-sectional view of a package structure in Figure 1

[0011] Figure 4 is an enlarged partial cross-sectional view of an overlap region between a system die and a photonic die in accordance with various aspects of the present disclosure.

[0012] Figure 5 is an enlarged partial cross-sectional view of an overlap region between a system die and a photonic die in accordance with various aspects of the present disclosure.

[0013] Figure 6 is an enlarged partial cross-sectional view of an overlap region between a system die and a photonic die in accordance with various aspects of the present disclosure.

[0014] Figure 7 is a flowchart illustrating a method for forming a package structure in accordance with various aspects of the present disclosure.​

[0015] Figures 8 to 18 Cross-sectional or top views of precursor structures undergoing various steps of the methods in Figure 7 are shown in accordance with various aspects of the present disclosure.

[0016] Figures 19 to 28 Alternative embodiments in accordance with various aspects of the present disclosure are shown. DETAILED DESCRIPTION

[0017] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the disclosure in any way. For example, in the following description, a first component forming over or on a second component can include embodiments where the first component and the second component are in direct contact, and can also include embodiments where additional components can be formed between the first component and the second component such that the first component and the second component can not be in direct contact. Furthermore, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the embodiments and / or configurations discussed.

[0018] To facilitate description, spatially relative terms such as "beneath", "below", "lower", "above", "upper" and the like can be used herein for describing elements and / or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0019] In addition, when describing a numerical value or a range of numerical values with "about", "approximately", or the like, the term is intended to encompass numerical values within a reasonable range, taking into account variations that occur inherently during manufacture as understood by one of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing a component having a feature associated with the numerical value, the numerical value or range of numerical values encompasses a reasonable range including the described numerical value, such as within + / - 10% of the described numerical value. For example, a material layer having a thickness of "about 5 nm" can encompass a range of sizes from 4.25 nm to 5.75 nm, where a manufacturing tolerance of + / - 15% associated with depositing the material layer is known to one of skill in the art.

[0020] Semiconductor packaging technology was once considered a back-end process that facilitated the connection of chips to external circuits. This is no longer the case. Computing workloads have changed dramatically, bringing packaging technology to the forefront of innovation. Modern packaging integrates multiple chips or dies into a single semiconductor device. The integration of chips is typically in two forms—two-dimensional (2D) architecture and three-dimensional (3D) architecture. In 2D architecture, the dies are packaged separately and mounted on a circuit board, and conductive traces in the circuit board interconnect the separately packaged dies. An integrated circuit (IC) with 3D architecture includes more than one die stacked vertically. This 3DIC technology improves the performance and efficiency of chips and also improves the stability and reliability of systems by bringing peripheral chips closer to a central system-on-a-chip (SoC) and enabling edge-to-edge 3D connections. 3DIC technology also results in increased chip density, improved area utilization efficiency, higher performance, and higher efficiency. Additionally, integrating different types of chips (e.g., such as central processing units (CPUs), graphics processing units (GPUs), and memories) can provide more efficient data processing and storage, thereby improving the overall performance and efficiency of systems. Optical chips can be integrated with electronic chips to take advantage of the high speed and low latency characteristics of optical transmission to increase communication speed and efficiency, reduce transmission loss and thermal effects, and achieve higher bandwidth and lower power consumption.

[0021] The present disclosure provides packaging structures that minimize the distance between peripheral dies and a central system die, reduce optical interference, and improve heat dissipation efficiency. In some examples, an interposer is bonded to a packaging substrate. A photonic die and a memory structure are bonded to the interposer. A system die is disposed over the photonic die, the memory structure, and the interposer such that the system die partially and vertically overlaps portions of the photonic die and the memory structure. The packaging structure also includes an electronic die bonded to a top surface of the photonic die. In some cases, the electronic die can be integrated into the system die. An optional packaging structure includes an interposer bonded to the packaging structure and a system die bonded to the interposer. A photonic die is bonded to the system die and overhangs the system die. The memory structure includes a controller die and a memory stack. In an optional packaging structure, the controller die is bonded to a top surface of the system die. The packaging structures of the present disclosure include a heat spreader attached to the packaging substrate. The heat spreader helps dissipate heat from the system die, the electronic die, the controller die, and the photonic die. In some cases, the photonic die includes an optical coupler coupled to an array of optical fibers.

[0022] Reference is first made to Figure 1 , Figure 1A top perspective view of the package structure 100 is shown. The package structure 100 includes a package substrate 102, an interposer 106 bonded to the package substrate 102. In the depicted embodiment, the package structure 100 includes four photonic dies and four memory structures bonded to a top surface of the interposer 106. Other arrangements are possible, which can include more or fewer photonic dies or memory structures. As Figure 1 shown, the four photonic dies include a first photonic die 110-1, a second photonic die 110-2, a third photonic die 110-3, and a fourth photonic die 110-4. The four memory structures include a first memory structure 112-1, a second memory structure 112-2, a third memory structure 112-3, and a fourth memory structure 112-4. The package structure 100 also includes a first electronic die 114-1 partially overlapping the first photonic die 110-1 and the second photonic die 110-2, and a second electronic die 114-2 partially overlapping the third photonic die 110-3 and the fourth photonic die 110-4. The package structure 100 also includes a system die 108 partially overlapping the memory structures and the photonic dies. The system die 108, the first photonic die 110-1, the second photonic die 110-2, the third photonic die 110-3, the fourth photonic die 110-4, the first memory structure 112-1, the second memory structure 112-2, the third memory structure 112-3, and the fourth memory structure 112-4 are covered by a heat spreader 104 attached to a top surface of the package substrate 102. Figure 1 A top perspective view of the package structure 100 in FIG. 1 is shown with a cross-section of a sidewall of the heat spreader 104, which will be further described below.

[0023] In some embodiments, the package substrate 102 can include a printed circuit board (PCB) or the like, which can include fiberglass-reinforced epoxy (FR-4), polytetrafluoroethylene (PTFE), and metal traces. The system die 108 can include a graphics processing unit (GPU), a central processing unit (CPU), a neural processing unit (NPU), or a combination thereof, to perform various applications. In some cases, the system die 108 can also be referred to as a system on a chip (SoC) die 108. Each of the photonic dies 110-1, 110-2, 110-3, and 110-4 refers to a die that includes two or more photonic components and detects, generates, transmits, and processes optical signals. The photonic die can also be referred to as a P-die or a photonic integrated circuit (PIC). Each of the electronic dies 114-1 and 114-2 can be referred to as an E-die or an electronic integrated circuit (EIC). In some embodiments, the photonic die can convert optical signals to electrical signals and send the electrical signals to the electronic die. The photonic die can also convert electrical signals received from the electronic die to optical signals and send the optical signals via a fiber array. The electronic die is connected with the photonic die.

[0024] Figure 1 includes a cross-section A-A' taken through the second photonic die 110-2, the first electronic die 114-1, the system die 108, the second electronic die 114-2, and the fourth photonic die 110-4 along the Y direction. Figure 2 A cross-sectional view along the cross-section A-A' is shown. Further, Figure 1 includes a cross-section B-B' taken through the first memory structure 112-1, the system die 108, and the third memory structure 112-3 along the X direction. Figure 3 A cross-sectional view along the cross-section B-B' is shown.

[0025] Referring to Figure 2 , the package substrate 102 includes package bumps 130 so that the package structure 100 can be subsequently mounted on and coupled to a larger substrate. The interposer 106 is bonded to the top surface of the package substrate 102 by controllable chip connection (C4) bumps 140. Each photonic die, such as the second photonic die 110-2 and the fourth photonic die 110-4 shown, is bonded to the top surface of the interposer 106 by micro bumps 150. The first electronic die 114-1 is bonded to the top surface of the first photonic die 110-1 and the second photonic die 110-2 by micro bumps 160. Similarly, the second electronic die 114-2 is bonded to the top surface of the third photonic die 110-3 and the fourth photonic die 110-4 by micro bumps 160. As Figure 2 shown, the system die 108 partially overlaps the photonic dies, such as the second photonic die 110-2 and the fourth photonic die 110-4. The overlap between the system die 108 and the photonic dies helps to minimize the electrical signal propagation distance and maximize the optical signal propagation distance. Because optical signals propagate faster and with minimal energy loss than electrical signals, Figure 2 Figure 1 Figure 2 and Figure 3 ​​The illustrated package structure 100 can have improved performance and energy efficiency. It should be noted that the system die 108 can be physically bonded to the top surface of a photonic die, such as the second photonic die 110-2 and the fourth photonic die 110-4, by micro bumps 161. In some implementations, the system die 108 does not directly communicate with the photonic die. In these implementations, the micro bumps 161 can be dummy micro bumps that do not provide electrical connections between the system die 108 and the photonic die, or can be bonded to a redistribution layer on the top of the photonic die to communicate with an electronic die, such as the first electronic die 114-1 and the second electronic die 114-2. In some further implementations, not explicitly shown in the figures, the functional integration of the electronic die into the photonic die such that the system die 108 can be directly connected to the photonic die. Typically, the C4 bumps (e.g., C4 bumps 140) and the micro bumps (e.g., micro bumps 150, 160, or 161) have a circular profile when viewed along the vertical direction (i.e., Z direction). The diameter of the C4 bumps is substantially larger than the size of the micro bumps. In some cases, the diameter of the micro bumps can be between about 3 pm and about 30 pm, and the diameter of the C4 bumps can be between about 50 pm and about 200 pm.

[0026] In Figure 2 In some embodiments, the system die 108 can also be directly bonded to the top surface of the interposer 106 by a plurality of high micro bumps 162. Because the bottom surface of the system die 108 is substantially flat, the height of each high micro bump 162 can be the sum of the height of the micro bump 150, the height of the micro bump 160, and the thickness of the second photonic die 110-2 or the fourth photonic die 110-4. The height of the high micro bump 162 can be between about 5 pm and about 20 pm, while the height of the micro bump 150 or the micro bump 160 can be between about 0.5 pm and about 15 pm. In some cases, the ratio of the height of the high micro bump to the height of the micro bump can be between about 4 and about 10. In Figure 2 In some cases, the second photonic die 110-2 and the fourth photonic die 110-4 are spaced apart along the Y direction. The first electronic die 114-1 and the second electronic die 114-2 are also spaced apart along the Y direction. The high micro bump 162 can be said to be disposed between the second photonic die 110-2 and the fourth photonic die 110-4 along the Y direction. The system die 108 can be said to be disposed between the first electronic die 114-1 and the second electronic die 114-2 along the Y direction. The vertical overlap between the system die 108 and the second photonic die 110-2 along the Y direction can be referred to as the Y-direction overlap (OY). In some cases, OY can be between about 500 pm and about 1000 pm. In Figure 2 In the illustrated embodiment, the system die 108 also vertically overlaps the fourth photonic die 110-4 by a Y-direction overlap (OY).

[0027] Still referencing Figure 2 The heat sink 104 may be in the form of a metal cap. The heat sink 104 is bonded to the top surface of the package structure 100, such as the top surface of the first die 114-1, the second die 114-2, and the system die 108, via a thermally conductive layer 109. In some embodiments, the thermally conductive layer 109 comprises a thermal interface material (TIM). The heat sink 104 may be attached to the top surface of the package substrate 102 by an adhesive. The TIM layer may comprise a gallium alloy, zinc oxide (ZnO), or aluminum nitride (AlN). The adhesive may comprise a die attachment film (DAF), silicone, polyimide (PI), or epoxy. The heat sink 104 may be formed of a metal or metal alloy, such as aluminum (Al), copper (Cu), iron (Fe), stainless steel, nickel (Ni), cobalt (Co), or alloys thereof. Example alloys may include aluminum-copper alloys, iron-nickel alloys, or iron-nickel-cobalt alloys. Figure 2 As shown, the photonic chip is coupled to an optical fiber array to receive or transmit optical signals. Figure 2 In some embodiments shown, the fiber array 120 is coupled to a coupler 124 on each photonic die via fiber connectors 122 extending through the sidewall of the heat sink 104. In some embodiments, the coupler 124 may be an edge coupler or a grating coupler. When the coupler 124 is an edge coupler, it is disposed along the sidewall of the photonic die (such as the second photonic die 110-2 or the fourth photonic die 110-4). When the coupler 124 is a grating coupler, it is disposed along the top surface of the photonic die (such as the second photonic die 110-2 or the fourth photonic die 110-4).

[0028] Now for reference Figure 3 In some embodiments, each of memory structures 112-1, 112-2, 112-3, and 112-4 may include a high-bandwidth memory (HBM) construction. HBM is a computer memory interface, typically used in conjunction with high-performance graphics accelerators, high-performance data centers, application-specific integrated circuits (ASICs) for AI applications, packaged caches in CPUs, or high-performance computing ICs. In the depicted embodiments, each memory structure may include a dynamic random access memory (DRAM) stack die (or memory stack die) and a controller die bonded to the DRAM stack die. In some cases, the DRAM stack die may include 2 to 10 DRAM dies stacked vertically. Vertical stacking allows for higher bandwidth, lower power consumption, and a smaller form factor. Figure 3In particular embodiments, the first memory structure 112-1 includes a first memory stack 112S-1 bonded to the first controller die 112C-1. The third memory structure 112-3 includes a third memory stack 112S-3 bonded to the third controller die 112C-3. Although not explicitly shown in the figures, it should be understood that the second memory structure 112-2 and the fourth memory structure 112-4 have similar structures. Each of the second memory structure 112-2 and the fourth memory structure 112-4 includes a memory stack die bonded to a controller die.

[0029] Still referring to Figure 3 The first controller die 112C-1 of the first memory structure 112-1 is bonded to the top surface of the interposer 106 by micro bumps 152. Similarly, the third controller die 112C-3 of the third memory structure 112-3 is bonded to the top surface of the interposer 106 by micro bumps 152. As shown in Figure 3 The first memory structure 112-1 and the third memory structure 112-3 are spaced apart from each other along the X direction. More specifically, along the X direction, the system die 108 is disposed between the first memory stack 112S-1 and the third memory stack 112S-3. To reduce electrical signal propagation distance, the system die 108 vertically overlaps the first controller die 112C-1 and the third controller die 112C-3. The vertical overlap between the system die 108 and the controller dies along the X direction can be referred to as X-directional overlap (OX). In some cases, the OX can be between about 500 pm and about 1000 pm. The system die 108 is directly bonded to the top surface of the interposer 106 by high micro bumps 162. Due to the X-directional overlap (OX), the system die 108 is also bonded to the top surface of the controller dies (such as the first controller die 112C-1 and the third controller die 112C-3) in Figure 3 by micro bumps 163. The micro bumps 163 can provide electrical connections between the system die 108 and the controller dies. As shown in Figure 3 The heat spreader 104 covers the first memory structure 112-1, the second memory structure 112-2, the third memory structure 112-3, and the fourth memory structure 112-4. The thermally conductive layer 109 is sandwiched between the bottom surface of the heat spreader 104 and the top surface of the memory structures to facilitate heat conduction.

[0030] To show the overlapping relationship in more detail, Figure 2 Region 10 in Figure 4 and Figure 5 is enlarged and shown in Figure 3 Region 20 in Figure 6 is enlarged and shown in. It should be noted that Figure 4 and Figure 5The structures in FIGS. 1A and IB represent two different configurations that produce the same benefits contemplated in this disclosure. Referring first to FIG. 1A, Figure 4 The portion of the system die 108 vertically overlaps the fourth photonic die 110-4 in a Y-direction overlap (OY). The system die 108 is bonded to the top surface of the fourth photonic die 110-4 by micro bumps 161. The second electronic die 114-2 is bonded to the top surface of the fourth photonic die 110-4 by micro bumps 160. The micro bumps 160 can include a pitch P and a width W along the Y-direction. In some cases, the pitch P can be between about 10 pm and about 30 pm, and the width W can be between about 5 pm and about 20 pm. Referring now to FIG. IB, Figure 5 , Figure 5 An alternative configuration is shown. Instead of having a photonic die next to the system die, the alternative configuration includes an engraved portion 1040 of the system die 1080, and the second electronic die 114-2 is disposed within the engraved portion 1040. The second electronic die 114-2 is bonded to the top surface of the engraved portion 1040 of the system die 1080 by micro bumps 1600. Figure 5 The portion of the system die 1080 in FIG. 1C vertically overlaps the fourth photonic die 110-4 in a Y-direction overlap (OY). In this case, the system die 1080 is bonded to the top surface of the fourth photonic die 110-4 by micro bumps 1602. Figure 5 In the embodiment shown in FIG. 1D, the second electronic die 114-2 vertically overlaps a portion of the system die 1080 and a portion of the fourth photonic die 110-4. The system die 1080 is bonded to the top surface of the fourth photonic die 110-4 by micro bumps 1602. The micro bumps 1602 can include a pitch P and a width W along the Y-direction. In some cases, the pitch P can be between about 10 pm and about 30 pm, and the width W can be between about 5 pm and about 20 pm.

[0031] Referring now to FIG. 1E, Figure 6 The third memory structure 112-3 includes a third memory stack 112S-3 bonded to a third controller die 112C-3. To reduce electrical signal propagation distances, the system die 108 vertically overlaps the third controller die 112C-3. The vertical overlap between the system die 108 and the third controller die 112C-3 along the X-direction defines an X-direction overlap (OX). As a result of the X-direction overlap (OX), the system die 108 is also bonded to the top surface of the third controller die 112C-3 by micro bumps 163. The third controller die 112C-3 of the third memory structure 112-3 is bonded to the top surface of the interposer 106 by micro bumps 152.

[0032] In this regard, Figure 7is a flowchart illustrating a method 200 of forming the package structure 100 described above. The method 200 is an example only and is not intended to limit the present disclosure to whatever is described in the method 200. Additional steps can be provided before, during, and after the method 200, and some steps described can be replaced by other steps, eliminated, or performed in a different order. For simplicity, not all steps are described in detail here. Some steps are described below in more detail in conjunction with the Figures 8 to 17 The method 200 is described below in conjunction with Figures 8 to 17 is a cross-sectional view or a top view of a precursor structure at different manufacturing stages according to various embodiments of the method 200. In the present disclosure, the same reference numbers represent the same components unless explicitly stated otherwise.

[0033] Referring to Figure 7 , Figure 8 and Figure 9 , the method 200 includes block 202, in which the photonic die is bonded to the interposer 106. According to the present disclosure, 2 to 4 photonic dies are bonded to the interposer 106. In Figure 8 and Figure 9 some embodiments, the interposer 106 is bonded to four photonic dies - the first photonic die 110-1, the second photonic die 110-2, the third photonic die 110-3, and the fourth photonic die 110-4. In some embodiments, micro-bonding components are formed on contact pads on the photonic dies. In some implementations, each micro-bonding component includes a metal pillar and a solder component located above the metal pillar. The metal pillar can include copper (Cu), nickel (Ni), or cobalt (Co), and the solder component includes tin (Sn), silver (Ag), or a combination thereof. At block 202, the photonic dies are placed on the top surface of the interposer 106. The micro-bonding components are aligned with the contact pads on the interposer 106. Then an annealing process or a bonding process is performed to bond the photonic dies to the interposer 106.

[0034] Referring to Figure 7 , Figure 10 and Figure 11 , the method 200 includes block 204, in which the memory structure is bonded to the interposer 106. According to the present disclosure, 2 to 4 memory structures are bonded to the interposer 106. In Figure 10 and Figure 11In some embodiments shown, four memory structures are bonded to the interposer 106. The four memory structures include a first memory structure 112-1, a second memory structure 112-2, a third memory structure 112-3, and a fourth memory structure 112-4. As described above, each of the four memory structures includes a memory stack die bonded to a controller die. In some embodiments, micro-bonding components are formed on contact pads on the controller die. In some implementations, each micro-bonding component includes a metal pillar and a solder component positioned above the metal pillar. The metal pillar can include copper (Cu), nickel (Ni), or cobalt (Co), and the solder component includes tin (Sn), silver (Ag), or a combination thereof. At block 204, the memory structures are placed on the top surface of the interposer 106. The micro-bonding components are aligned with contact pads on the interposer 106. An anneal process or a bonding process is then performed to bond the memory structures to the interposer 106.

[0035] Although the photonic die is depicted as being bonded to the interposer 106 first, the present disclosure fully contemplates embodiments in which the memory structures are bonded to the interposer 106 first. As will be further described below, the system die 108 will be bonded to the interposer 106. Referring to Figure 10 Because the system die 108 is intended to partially overlap the photonic die and the memory structures, the photonic die and the memory structures substantially define the outer periphery of a rectangular region. In the depicted embodiment, the photonic die is divided into two groups spaced apart along the Y direction, and the memory structures are divided into two groups spaced apart along the X direction.

[0036] Referring to Figure 7 , Figure 12 and Figure 13, the method 200 includes block 206, in which the system die 108 is bonded to the interposer 106 such that edges of the system die 108 overlap the photonic die and the memory structure. As described above, the system die 108 will be bonded to the interposer 106 through high micro bumps 162, to the photonic die through micro bumps 161, and to the controller die through micro bumps 163. In some embodiments, micro bonding features (for micro bumps 161 and 163) and high micro bonding features (for high micro bumps 162) are formed on contact pads on the system die 108. In some implementations, each micro bonding feature includes a metal pillar and a solder feature positioned above the metal pillar. Each high micro bonding feature includes a high metal pillar and a solder feature. The high metal pillar has a height that is greater than the height of the metal pillar. The metal pillar and the high metal pillar can include copper (Cu), nickel (Ni), or cobalt (Co), and the solder feature includes tin (Sn), silver (Ag), or a combination thereof. At block 206, the system die 108 is placed on the top surface of the interposer 106, on the portion of the photonic die, and on the portion of the memory structure. The micro bonding features are aligned with contact pads on the photonic die and the controller die. The high micro bonding features are aligned with contact pads on the interposer. An anneal process or a bonding process is then performed to bond the system die 108 to the photonic die, the memory structure, and the interposer 106.

[0037] Referring to Figure 7 and Figure 14 , the method 200 includes block 208, in which the electronic die is bonded to the photonic die. According to the present disclosure, one to two electronic dies can be bonded to a photonic die. In some embodiments, each electronic die is configured to be bonded to two photonic dies. For example, when the package structure includes four photonic dies, two electronic dies are bonded to them because each electronic die is bonded to two photonic dies. Another example, when the package structure includes two photonic dies, one electronic die is bonded to the pair of photonic dies. In some embodiments, the electronic die is bonded to the photonic die through micro bumps. In some embodiments, the electronic die is bonded to the photonic die through high micro bumps. In some embodiments, the electronic die is bonded to the photonic die through both micro bumps and high micro bumps. In some embodiments, the electronic die is bonded to the photonic die through a combination of micro bumps and high micro bumps. In some embodiments, the electronic die is bonded to the photonic die through a combination of micro bumps, high micro bumps, and solder. In some embodiments, the electronic die is bonded to the photonic die through a combination of micro bumps, high micro bumps, and solder. Figure 14In some embodiments shown, two electronic dies are bonded to four photonic dies. The two electronic dies include a first electronic die 114-1 and a second electronic die 114-2. Each electronic die is fabricated to have a configuration that bonds to photonic dies while still allowing the system die 108 to overlap the photonic dies. As described above, the electronic dies will be bonded to the photonic dies through micro-bumps 160. In some embodiments, the micro-bonding features are formed on contact pads on the electronic dies. In some implementations, each micro-bonding feature includes a metal pillar and a solder feature positioned above the metal pillar. The metal pillar can include copper (Cu), nickel (Ni), or cobalt (Co), and the solder feature can include tin (Sn), silver (Ag), or a combination thereof. At block 208, each electronic die is placed over the top surface of two photonic dies. In the depicted embodiment, the first electronic die 114-1 is placed over the first photonic die 110-1 and the second photonic die 110-2, and the second electronic die 114-2 is placed over the third photonic die 110-3 and the fourth photonic die 110-4. The micro-bonding features are aligned with the contact pads on the photonic dies. An annealing process or a bonding process is then performed to bond the electronic dies to the photonic dies.

[0038] It should be noted that the operations at block 208 can be performed before the operations at block 206. Because the bonding of the electronic dies and the bonding of the system die 108 do not interfere with each other, they can be bonded to the interposer 106 / photonic dies in any order. In some cases, the operations at block 206 can be performed before the operations at block 208. In some cases, the operations at block 208 can be performed before the operations at block 206. This is why the first photonic die 114-1 and the second photonic die 114-2 are shown in dashed lines in Figure 12 , and why the system die 108 is shown in dashed lines in Figure 14 . As Figure 15 shown, after the operations at blocks 206 and 208 are completed, the photonic dies, the memory structure, the system die 108, and the electronic dies are all bonded to the interposer 106.

[0039] Referring to Figure 7 and Figure 16At block 210, the method 200 includes bonding the interposer 106 to the package substrate 102. In some embodiments, controllable collapsed chip connection (C4) bumps 140 are formed on contact pads on the back surface of the interposer 106. The contact pads on the interposer can include under bump metal (UBM) bumps. The C4 bumps 140 are larger in size than the micro bumps described above. The C4 bumps 140 can include lead, tin, silver, or alloys thereof. After forming the C4 bumps 140, the interposer 106 is placed on the package substrate 102 such that the C4 bumps 40 are aligned with contact pads on the package substrate 102. An anneal process or a bonding process is then performed to bond the interposer 106 to the package substrate 102.

[0040] Referring to Figure 7 , Figure 17 and Figure 18 At block 212, the method 200 includes attaching the heat spreader 104 to the package substrate 102 to cover the photonic die, the memory structure, the system die, the electronic die, and the interposer. As described above, the heat spreader 104 is formed from a metal or a metal alloy, such as aluminum (Al), copper (Cu), iron (Fe), stainless steel, nickel (Ni), cobalt (Co), or alloys thereof. Example alloys can include aluminum copper alloys, iron nickel alloys, or iron nickel cobalt alloys. Because the heat spreader 104 includes a metal, it can also be referred to as a metal lid. At block 212, a thermally conductive layer 109 is formed over the top surfaces of the electronic die, the system die, and the controller die, and an adhesive is dispensed in the landing areas on the package substrate 102. The thermally conductive layer 109 can include a TIM material, which can include a gallium alloy, zinc oxide (ZnO), or aluminum nitride (AIN). When the TIM material is a liquid, they can be dispensed over the top surfaces of the dies to form the thermally conductive layer 109. The adhesive can include a die attach film (DAF), a silicone, a polyimide (PI), or an epoxy. The heat spreader 104 is then placed over the package substrate 102 such that the bottom surface of the heat spreader 104 is bonded to the thermally conductive layer 109 and the lower edges of the sidewalls of the heat spreader 104 are bonded to the adhesive. A curing process, such as an anneal process, is then performed to cure the thermally conductive layer 109 and the adhesive to bond the heat spreader 104 to the package substrate 102.

[0041] Referring to Figure 7 and Figure 17The method 200 includes block 214, in which a fiber connection to the photonic die is formed. In some embodiments, the fiber connection is formed prior to attaching the heat spreader 104, and the heat spreader 104 includes a slot or opening to accommodate such a fiber connection. In some embodiments, the fiber connection is formed after attaching the heat spreader 104 through a slot or opening on the heat spreader 104. Typically, the fiber connection includes three components - a fiber array 120, a fiber connector 122 that physically engages a sidewall of the heat spreader 104, and a coupler 124 configured to couple to the fiber array 120. The coupler 124 can include an edge coupler or a grating coupler. When the coupler 124 is an edge coupler, the coupler 124 is disposed along a sidewall of a photonic die, such as the second photonic die 110-2 or the fourth photonic die 110-4. When the coupler 124 is a grating coupler, the coupler 124 is disposed along a top surface of a photonic die, such as the second photonic die 110-2 or the fourth photonic die 110-4.

[0042] Figures 19 to 27 An optional embodiment is shown. Figure 19 And Figure 20 An optional embodiment is shown, in which the decoupling capacitor die 170 is disposed vertically between the system die 108 and the interposer 106. Figure 21 And Figure 22 An optional embodiment is shown, in which the input / output die 180 is disposed vertically between the system die 108 and the interposer 106. Figure 23 And Figure 24 An optional embodiment is shown, in which the photonic die and the controller die are bonded to a top surface of the system die 108. Figure 25 And Figure 26 An optional embodiment is shown, in which the photonic die and the electronic die are switched positions. Figure 27 An optional embodiment is shown, in which the package structure 100 includes two photonic dies. Figure 28 An optional embodiment is shown, in which the electronic die is integrated in the system die 108.

[0043] Figure 19 And Figure 20 A cross-sectional view of the package structure 1002 is shown. The package structure includes a decoupling capacitor die 170 that is bonded to the system die 108 and the interposer 106 through micro bumps 165 and micro bumps 167. The decoupling capacitor die 170 includes a decoupling capacitor designed to isolate the circuitry in the system die 108 from noise and anomalies from other devices or dies coupled to the same power supply. As shown in Figure 19 And Figure 20 The decoupling capacitor die 170 is disposed vertically between the system die 108 and the interposer 106, as shown in Figure 19As shown, along the Y direction, the decoupling capacitor die 170 is disposed between the second photon die 110-2 and the fourth photon die 110-4. As shown, Figure 20 As shown, along the X direction, the decoupling capacitor die 170 is disposed between the first controller die 112C-1 and the third controller die 112C-3.

[0044] Figure 21 and Figure 22 A cross-sectional view of a package structure 1004 is shown. The package structure 1004 includes an input / output (I / O) die 180 bonded to the system die 108 and the interposer 106 by micro bumps 168 and micro bumps 169. The I / O die 180 can act as an interface between the system die 108 and the peripheral dies. In some embodiments, the I / O die 180 can redistribute signals from the system die 108 to couple to the interposer 106. As shown, Figure 21 and Figure 22 As shown, the I / O die 180 is disposed vertically between the system die 108 and the interposer 106. As shown, Figure 21 As shown, along the Y direction, the I / O die 180 is disposed between the second photon die 110-2 and the fourth photon die 110-4. As shown, Figure 22 As shown, along the X direction, the I / O die 180 is disposed between the first controller die 112C-1 and the third controller die 112C-3.

[0045] Figure 23 and Figure 24 A cross-sectional view of a package structure 1006 is shown. In Figure 2 , Figure 3 , Figure 17 and Figure 18 In the representative embodiment shown in FIGS. 10A-10D, the photon dies and the controller dies are bonded to the interposer 106 and the system die 108 such that portions of the photon dies and the controller dies are disposed between the system die 108 and the interposer 106. In the package structure 1006, the photon dies and the controller dies are bonded to a top surface of the system die 108. The system die 108 is bonded to the interposer 106 by micro bumps 164. The photon dies, such as the second photon die 110-2 and the fourth photon die 110-4, are bonded to the top surface of the system die 108 by micro bumps 172 and overhang the interposer 106. A thermal spreading layer 190 is disposed directly on the system die 108. The thermal spreading layer 190 can include a thermal interface material (TIM), a metal, or a metal alloy. In some cases, the thermal spreading layer 190 includes a gallium alloy, zinc oxide (ZnO), aluminum nitride (AIN), aluminum (Al), copper (Cu), iron (Fe), stainless steel, nickel (Ni), cobalt (Co), an aluminum copper alloy, an iron nickel alloy, or an iron nickel cobalt alloy. As shown, Figure 23As shown, the heat diffusion layer 190 is disposed between the two sets of photonic dies along the Y-direction. Viewed from above the system die 108, each photonic die is perpendicularly overlapped with the system die 104 in the Y-direction (OY). In some cases, the Y-direction overlap (OY) is between approximately 500 μm and approximately 1000 μm. Figure 23 As shown, the fiber array 120 is coupled to a coupler 124 on each photonic chip via a fiber connector 122 extending through the sidewall of the heat sink 104. In some embodiments, the coupler 124 may be an edge coupler or a grating coupler. When the coupler 124 is an edge coupler, it is disposed along the sidewall of the photonic chip (such as the second photonic chip 110-2 or the fourth photonic chip 110-4). When the coupler 124 is a grating coupler, it is disposed along the top surface of the photonic chip (such as the second photonic chip 110-2 or the fourth photonic chip 110-4). Because the top surface of the photonic chip and the heat diffusion layer 190 is engaged with the bottom surface of the heat sink 104, the coupler 124 may be disposed closer to the lower edge of the photonic chip than the interposer layer 106. The bottom surface of the heat sink 104 is connected to the top surface of the controller die and the photon die through the thermal conductive layer 109.

[0046] like Figure 23 As shown by the dashed lines, electron dies (such as the first electron die 114-1 and the second electron die 114-2) can be directly bonded to photonic dies (such as the second photonic die 110-2 and the fourth photonic die 110-4) via microbumps. Alternatively, the functions of the first electron die 114-1 and the second electron die 114-2 can be performed through electron die regions allocated in the system die 108. As will be explained below... Figure 28 As further described in the text, this system die 108 can be referred to as an integrated system die.

[0047] refer to Figure 24 The memory structure is bonded to system die 108 and interposer 106. Controller dies (such as first controller die 112-1 and third controller die 112-3) are coupled to the top surface of system die 108 via microbumps 174. Memory stack dies (such as first memory stack 112S-1 and third memory stack 112S-3) are bonded to the top surface of interposer 106 via microbumps 176. A thermal diffusion layer 190 is disposed between first controller die 112C-1 and third controller die 112C-3 along the X direction. System die 108 is disposed between first memory stack 112S-1 and third memory stack 112S-3 along the X direction. Viewed from above system die 108, each controller die is perpendicularly overlapped with system die 106 in the X direction (OX). In some cases, the X-direction overlap (OX) is between approximately 500 μm and approximately 1000 μm.

[0048] Figure 25 and Figure 26 A cross-sectional view of a package structure 1008 is shown. As compared to the embodiment representatively shown in Figure 2 , Figure 3 , Figure 17 and Figure 18 , the photonic die and the electronic die are swapped in the package structure 1008. Referring to Figure 25 , the first electronic die 114-1 and the second electronic die 114-2 are directly bonded to the interposer 106 by micro bumps 151, and the photonic die is bonded to the top surface of the electronic die by micro bumps 179. The photonic die is now located next to the system die 108. Along the Y direction, the system die 108 is disposed between the second photonic die 110-2 and the fourth photonic die 110-4. The system die 108 is vertically overlapped with each electronic die Y-direction overlap (OY). In some cases, the Y-direction overlap (OY) is between about 500 pm and about 1000 pm. As shown in Figure 25 , the fiber array 120 is coupled to the coupler 124 on the lower edge of each photonic die via a fiber connection 122 that extends through the sidewall of the heat sink 104. In some embodiments, the coupler 124 can be an edge coupler or a grating coupler. When the coupler 124 is an edge coupler, the coupler 124 is disposed along the sidewall of the photonic die, such as the second photonic die 110-2 or the fourth photonic die 110-4. When the coupler 124 is a grating coupler, the coupler 124 is disposed along the top surface of the photonic die, such as the second photonic die 110-2 or the fourth photonic die 110-4.

[0049] In some embodiments, as shown in Figure 26 , the first electronic die 114-1 and the second electronic die 114-2 are directly bonded to the interposer 106 by micro bumps 151. The system die 1080 includes an engraved portion. The photonic die is disposed within the engraved portion and bonded to the system die 1080. The photonic die is disposed next to the system die 1080. Along the Y direction, the system die 1080 is disposed between the second photonic die 110-2 and the fourth photonic die 110-4. The system die 1080 is vertically overlapped with each electronic die Y-direction overlap (OY). In some cases, the Y-direction overlap (OY) is between about 500 pm and about 1000 pm. As shown in Figure 26As shown, the fiber array 120 is coupled to a coupler 124 on each photonic die via a fiber connection 122 that extends through a sidewall of the heat spreader 104. In some embodiments, the coupler 124 can be an edge coupler or a grating coupler. When the coupler 124 is an edge coupler, the coupler 124 is disposed along a sidewall of a photonic die, such as the second photonic die 110-2 or the fourth photonic die 110-4. When the coupler 124 is a grating coupler, the coupler 124 is disposed along a top surface of a photonic die, such as the second photonic die 110-2 or the fourth photonic die 110-4.

[0050] Figure 27 The package structure 1010 includes the package substrate 102. As shown, the package substrate 102 includes a first surface 102-1 and a second surface 102-2. The first surface 102-1 is opposite the second surface 102-2. The first surface 102-1 is disposed on the first side 100-1 of the package structure 1010. The second surface 102-2 is disposed on the second side 100-2 of the package structure 1010. Figure 2 、 Figure 3 、 Figure 17 and Figure 18 In contrast to the embodiments representative shown in Figure 27 As shown, the first electronic die 114-1 is disposed along an edge of the system die 108 and is bonded to a top surface of the first photonic die 110-1 and the second photonic die 110-2. In some embodiments, as shown in Figure 27 The package structure 1010 includes a first memory structure 112-1, a second memory structure 112-2, a third memory structure 112-3, and a fourth memory structure 112-4. As with the embodiments representative shown in Figure 2 、 Figure 3 、 Figure 17 and Figure 18 The system die 108 vertically overlaps the first photonic die 110-1 and the second photonic die 110-2 in a Y-direction overlap (OY). The system die 108 vertically overlaps the controller dies of the first memory structure 112-1, the second memory structure 112-2, the third memory structure 112-3, and the fourth memory structure 112-4 in an X-direction overlap (OX). As shown, Figure 27 The interposer 106, the first memory structure 112-1, the second memory structure 112-2, the third memory structure 112-3, the fourth memory structure 112-4, the first photonic die 110-1, the second photonic die 110-2, and the system die 108 are covered by the heat spreader 104 that is attached to the package substrate 102.

[0051] Figure 28 The integrated system die 1082 includes blocks that perform electronic die functions. In Figure 28 In some embodiments, as shown, the integrated system die 1082 includes a first block 1200 and a second block 1202 of integrated circuitry to perform electronic die functions. The integrated system die 1082 can performFigures 1 to 3 、 Figures 17 to 18 、 Figures 19 to 20 and Figures 21 to 22 the functions of the system die 108, the first electronic die 114-1, and the second electronic die 114-2 shown in Figures 1 to 3 、 Figures 17 to 18 、 Figures 19 to 20 and Figures 21 to 22 for avoidance of doubt, the integrated system die 1082 in Figure 28 is a single die. In some cases, each of the first block 1200 and the second block 1202 can be obtained by reusing two serializer / deserializer regions in the integrated system die 1082.

[0052] The present disclosure provides many embodiments. In one aspect, the present disclosure provides a package structure. The package structure includes a package substrate, a interposer disposed above the package substrate, a photonic die disposed above the interposer, a memory structure disposed above the interposer and including a controller die, a system die disposed above the interposer and partially overlapping the photonic die and the controller die, and a cap covering the system die, the memory structure, and the photonic die. The system die includes micro-bumps extending from a bottom surface of the system die to a top surface of the controller die.

[0053] In some embodiments, the package structure further includes an electronic die disposed on the photonic die and extending along an edge of the system die. In some embodiments, the system die further includes high micro-bumps extending from a bottom surface of the system die to a top surface of the interposer. In some implementations, the package structure further includes a decoupling capacitor disposed between the interposer and the system die. In some embodiments, the package structure further includes an input / output die disposed between the interposer and the system die. In some embodiments, the photonic die includes an edge coupler, and the edge coupler is coupled to a fiber array. In some cases, a portion of the system die extends between a bottom surface of the electronic die and a top surface of the photonic die. In some embodiments, the partial overlap between the photonic die and the controller die defines an overlap width between about 500 pm and about 1000 pm.

[0054] In another aspect, the disclosure provides a package structure. The package structure includes: a package substrate; a interposer disposed above the package substrate; first and second photonic dies disposed above the interposer and spaced apart from each other along a first direction; first and second memory structures disposed above the interposer and spaced apart from each other along a second direction perpendicular to the first direction, the first memory structure including a first controller die, and the second memory structure including a second controller die; a system die disposed above the interposer and partially overlapping the first controller die, the second controller die, the first photonic die, and the second photonic die; and a cap covering the system die, the first memory structure, the second memory structure, the first photonic die, and the second photonic die. The system die includes micro-bumps extending from a bottom surface of the system die to top surfaces of the first and second controller dies.

[0055] In some embodiments, the first photonic die includes a first edge coupler, and the second photonic die includes a second edge coupler. In some embodiments, the package structure further includes high micro-bumps extending from a bottom surface of the system die to a top surface of the interposer. In some embodiments, the package structure further includes a die disposed vertically between the interposer and the system die and disposed along the first direction between the first and second photonic dies. In some embodiments, the die includes a decoupling capacitor die or an input / output die. In some embodiments, the system die is coupled to the die by first micro-bumps, and the die is coupled to the interposer by second micro-bumps. In some embodiments, the package structure further includes a first electronic die disposed above the first photonic die and a second electronic die disposed above the second photonic die. The system die is disposed between the first and second electronic dies along the first direction.

[0056] In yet another aspect, the disclosure provides a package structure. The package structure includes: a package substrate; an interposer disposed above the package substrate; a system die disposed above the interposer; first and second photonic dies disposed above the system die and overhanging the system die; first and second memory structures disposed above the interposer, the first memory structure including a first controller die and a first memory stack bonded to the first controller die, and the second memory structure including a second controller die and a second memory stack bonded to the second controller die; and a cap covering the system die, the first memory structure, the second memory structure, the first photonic die, and the second photonic die. Portions of the first controller die and portions of the second controller die span top surfaces of the system die.

[0057] In some embodiments, the first photonic die and the second photonic die are spaced apart from each other along a first direction. The first memory structure and the second memory structure are spaced apart from each other along a second direction that is perpendicular to the first direction. In some embodiments, the package structure further includes a thermal spreading layer disposed between the top surface of the system die and the bottom surface of the cap. In some embodiments, the thermal spreading layer is disposed between the first controller die and the second controller die along the second direction. In some implementations, the system die is disposed between the first memory stack and the second memory stack along the second direction.

[0058] The features outlined above for several embodiments make it possible for those skilled in the art to better understand the aspects of the present disclosure. It should be understood that they can easily use the present disclosure as a basis for the design or modification of other processes and structures for implementing the same objectives and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A packaging structure, comprising: Packaging substrate; An intermediate layer is disposed above the encapsulation substrate; The photonic chip is disposed above the interlayer; A memory structure is disposed above the intermediary layer and includes a controller die; The system die is disposed above the interposer layer and partially overlaps with the photonic die and the controller die; as well as The cover covers the system die, the memory structure, and the photonic die. The system die includes microbumps extending from the bottom surface of the system die to the top surface of the controller die.

2. The packaging structure according to claim 1 further includes: An electron die is disposed on the photonic die and extends along the edge of the system die.

3. The packaging structure according to claim 1, wherein, The system die also includes high micro-bumps extending from the bottom surface of the system die to the top surface of the interposer layer.

4. The packaging structure according to claim 1 further includes: A decoupling capacitor is disposed between the interlayer and the system die.

5. The packaging structure according to claim 1, further comprising: The input / output die is disposed between the interposer layer and the system die.

6. The packaging structure according to claim 1, in, The photonic die includes an edge coupler, and The edge coupler is coupled to the fiber array.

7. The packaging structure according to claim 2, in, A portion of the system die extends between the bottom surface of the electronic die and the top surface of the photonic die.

8. The packaging structure according to claim 1, wherein, The partial overlap between the photonic die and the controller die defines an overlap width between approximately 500 μm and approximately 1000 μm.

9. A packaging structure, comprising: Packaging substrate; An intermediate layer is disposed above the encapsulation substrate; The first photonic chip and the second photonic chip are disposed above the interposer and spaced apart from each other along the first direction; A first memory structure and a second memory structure are disposed above the interposer and spaced apart from each other along a second direction perpendicular to the first direction. The first memory structure includes a first controller die, and the second memory structure includes a second controller die. The system die is disposed above the interposer layer and partially overlaps with the first controller die, the second controller die, the first photonic die, and the second photonic die; as well as The cover covers the system die, the first memory structure, the second memory structure, the first photonic die, and the second photonic die. The system die includes microbumps extending from the bottom surface of the system die to the top surfaces of the first controller die and the second controller die.

10. A packaging structure, comprising: Packaging substrate; An intermediate layer is disposed above the encapsulation substrate; The system die is disposed above the interposer layer; The first photonic chip and the second photonic chip are disposed above the system chip and suspended on the system chip; A first memory structure and a second memory structure are disposed above the interposer layer. The first memory structure includes a first controller die and a first memory stack attached to the first controller die, and the second memory structure includes a second controller die and a second memory stack attached to the second controller die. as well as The cover covers the system die, the first memory structure, the second memory structure, the first photonic die, and the second photonic die. The first controller die portion and the second controller die portion extend across the top surface of the system die.

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