Monolithic integrated device of full GaN Cascode structure based on NiO bonding and preparation method thereof

Abstract

The invention relates to a monolithic integrated device of a full GaN Cascode structure based on NiO bonding and a preparation method of the monolithic integrated device. The monolithic integrated device comprises a substrate, a buffer layer and an AlGaN / GaN heterojunction from bottom to top, a NiO grid electrode is grown in the D-mode GaN device region of the AlGaN / GaN heterojunction, and grid electrode metal is grown in the E-mode GaN device region of the AlGaN / GaN heterojunction and above the NiO grid electrode. According to the invention, monolithic integration of an enhanced device and a depletion device can be realized, and the device has the advantages that the chip area is reduced, the packaging is simplified, the packaging volume is reduced, and the low-voltage tube is a control tube, so that threshold voltage drift can be reduced, dynamic on-resistance degradation can be reduced, and superior high-frequency performance and lower switching loss caused by reduction of parasitic parameters can be reduced.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power semiconductor devices, and particularly relates to a monolithic integrated device based on a full GaNCascode structure of NiO bonding and a preparation method thereof. BACKGROUND

[0002] With the development of power semiconductor devices, power devices made of wide-bandgap semiconductor materials such as gallium nitride (GaN) and silicon carbide (SiC) are being used more and more widely. GaN-based power devices, especially heterojunctions (such as AlGaN / GaN) with high-mobility two-dimensional electron gas (2DEG) channels, have become the candidate materials for a new generation of power conversion systems with high conversion efficiency and high power density due to their excellent material properties such as wide bandgap, large critical breakdown field strength, and high operating temperature.

[0003] In semiconductor technology, full GaN monolithic integration technology has gradually become one of the key technologies for improving the performance of integrated circuits due to its small system size, low assembly cost, simple and excellent manufacturing process, low parasitic inductance caused by small device interconnection distance, and fast switching speed caused by small GaN device parasitic parameters and near-zero reverse recovery time. Traditional circuits usually use MOSFETs as switching devices. However, with the increase of power density and operating frequency, traditional MOSFET devices face many challenges such as large switching loss, high leakage current, and switching speed limitation caused by capacitance effect. SUMMARY

[0004] The application provides a monolithic integrated device based on a full GaNCascode structure of NiO bonding and a preparation method thereof, which solves the problems of increasing defect density of an epitaxial wafer and reducing free electron gas concentration caused by P-GaN technology.

[0005] The application provides a monolithic integrated device based on a full GaNCascode structure of NiO bonding, which comprises, from bottom to top, a substrate, a buffer layer, and an AlGaN / GaN heterojunction; a NiO gate is grown in a D-mode GaN device region of the AlGaN / GaN heterojunction, and a gate metal is grown above the E-mode GaN device region and the NiO gate of the AlGaN / GaN heterojunction; source metal and drain metal are provided on both sides of the D-mode GaN device region and the E-mode GaN device region of the AlGaN / GaN heterojunction, a first deep trench is etched below the drain metal, and a second deep trench is etched between the D-mode GaN device region and the E-mode GaN device region of the AlGaN / GaN heterojunction.

[0006] Preferably, the substrate comprises one or several of polycrystalline AlN ceramic, SiN ceramic, silicon on insulator.

[0007] Preferably, the buffer layer comprises one or several of SiO2, Al2O3, HfO2, La2O3, ZrO2, Si3N4.

[0008] Preferably, the gate metal comprises one or several of W, TiN, Al, Ni, Ti, Au, Mo, Pt.

[0009] Preferably, the source metal and drain metal comprise one or several of W, TiN, Al, Ni, Ti, Au, Mo, Pt.

[0010] Preferably, the monolithic integrated device is filled with a dielectric layer to isolate the high-voltage tube from the low-voltage tube.

[0011] Preferably, the dielectric layer comprises one or several of SiO2, Al2O3, HfO2, La2O3, ZrO2, Si3N4.

[0012] The application also provides a preparation method of a monolithic integrated device based on a full GaN Cascode structure of NiO bonding, comprising the following steps:

[0013] (1) providing a GaN HEMT device comprising a substrate, a buffer layer and an AlGaN / GaN heterojunction;

[0014] (2) growing a NiO gate on the D-mode GaN device region of the AlGaN / GaN heterojunction;

[0015] (3) growing a gate metal on the E-mode GaN device region of the AlGaN / GaN heterojunction and the NiO gate;

[0016] (4) providing a source metal and a drain metal on both sides of the D-mode GaN device region and the E-mode GaN device region of the AlGaN / GaN heterojunction, and etching a first deep groove under the drain metal;

[0017] (5) etching a second deep groove between the D-mode GaN device region and the E-mode GaN device region of the AlGaN / GaN heterojunction;

[0018] (6) connecting the source of the high-voltage tube to the drain of the low-voltage tube and connecting the gate of the high-voltage tube to the source of the low-voltage tube through a top via and an interconnection process;

[0019] (7) filling with dielectric layer to realize isolation between high-voltage tube and low-voltage tube, and obtain a monolithic integrated device based on the full GaN Cascode structure of NiO bonding.

[0020] Preferably, the etching method in steps (4) and (5) comprises ICP or RIE; the etching atmosphere is one or more of SF6, CHF3, BCl3, CF4, C4F8, Cl2 and He.

[0021] Preferably, the filling method of the dielectric layer in step (7) comprises one or more of chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, thermal or electron beam evaporation, and sputtering.

[0022] The monolithic integration technology based on the full GaN Cascode structure of NiO bonding can realize monolithic integration of enhancement-mode devices and depletion-mode devices, and has the advantages of reduced chip area, simplified packaging, smaller packaging volume, reduced threshold voltage drift and reduced dynamic on-resistance degradation of low-voltage tubes as control tubes, superior high-frequency performance and lower switching loss due to reduced parasitic parameters, and significant advantages in the field of power electronics, especially in suppressing crosstalk and substrate bias effect. NiO bonding is used to form enhancement-mode GaN devices, so that depletion-mode GaN devices can be manufactured using standard silicon process lines, fully utilizing the advantages of low defect density, high 2DEG mobility and high charge density of GaN epitaxial wafers.

[0023] The theory of the present application is based on the following formula:

[0024]

[0025] The literature reported values are brought into the formula and calculated

[0026]

[0027] Therefore, the full GaN Cascode structure based on NiO bonding has a stable threshold voltage. Among them, V T is the threshold voltage of the device, E gp is the band gap of the gate material ΔE C2 is the conduction band offset of the barrier and u-GaN (unintentionally doped GaN), ΔE C1 is the conduction band offset between NiO and the barrier, ΔV b is the built-in potential difference, and q is the charge quantity.

[0028] The energy band structure of the present application is shown in Figure 2 . Among them, V gs is the gate-source voltage of the device, E Fmis the metal Fermi level, m is the metal, qψs1 is the surface potential at NiO / u-GaN, qψ bi is the total built-in potential, qV R is the energy of the reverse bias voltage, E Fn is the Fermi level of the n-type region, E Fp is the Fermi level of the p-type region, qφ Bn is the Schottky barrier height of the metal conduction band, qφ Bp is the Schottky barrier height of NiO, E a1 is the activation energy of Mg, b is the barrier, CB is the conduction band, VB is the valence band, ΔV ch is the energy drop in the conduction band in the channel, i.e., the potential difference E Fbb is the Fermi level of the bottom n-type GaN:C region, E a1 is the activation level of the compensating impurities in GaN:C.

[0029] Advantages

[0030] Compared with the prior art, the present application has the following advantages:

[0031] (1) High-quality wafer: Eliminate the adverse effects of traditional P-GaN process on the quality of epitaxial wafer, use NiO to control threshold voltage, improve device performance consistency and process compatibility.

[0032] (2) High efficiency and low power consumption: The full GaN cascode structure based on NiO bonding realizes the enhancement mode by growing a NiO layer on the AlGaN / GaN heterojunction. This structure avoids the always-on mode in traditional GaN HEMT, reduces the static power consumption during power conversion, and improves the overall efficiency of the system.

[0033] (3) Good electrical isolation: The high-voltage tube and the low-voltage tube are isolated by deep trench etching technology, which effectively reduces the mutual interference between devices (such as parasitic capacitance and parasitic diode effect) and the source and substrate are at the same potential, which can avoid substrate crosstalk.

[0034] (4) Reduce leakage current and switching loss: The insulating layer in the substrate can reduce the substrate leakage current and the parasitic effect caused by the substrate, and the dielectric above NiO makes the gate leakage of the device smaller, which together improves the electrical performance of the system and reduces power loss.

[0035] (6) Low parasitic effect: Avoid the parasitic effect caused by Si-based drive circuit and Si-based low-voltage device through wire bonding, heterogeneous packaging and other ways, and improve the switching performance.

[0036] (7) Fast switching speed: The common-source common-gate technology reduces the Miller capacitance of the full GaN device, and greatly reduces the turn-off loss and switching time by using the characteristics of extremely low reverse recovery effect of the GaN device. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 Figure 1 is a structural schematic diagram of a monolithic integrated device of the present application.

[0038] Figure 2 Figure 2 is a band structure of a monolithic integrated device of the present application.

[0039] Figures 3-7 Figure 3 is a preparation flow chart of a monolithic integrated device of the present application. DETAILED DESCRIPTION

[0040] The present application will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present application and not to limit the scope of the present application. In addition, it should be understood that those skilled in the art can make various modifications or changes to the present application after reading the content taught by the present application, and these equivalent forms also fall within the scope of the appended claims of the present application.

[0041] Example 1

[0042] As shown in Figure 1 , the present embodiment provides a monolithic integrated device based on NiO bonding full GaN Cascode structure, which comprises, from bottom to top, a substrate, a buffer layer and an AlGaN / GaN heterojunction; a NiO gate is grown in the D-mode GaN device region of the AlGaN / GaN heterojunction, and a gate metal is grown above the E-mode GaN device region of the AlGaN / GaN heterojunction and the NiO gate; a source metal and a drain metal are provided on both sides of the D-mode GaN device region and the E-mode GaN device region of the AlGaN / GaN heterojunction, a first deep trench is etched below the drain metal, and a second deep trench is etched between the D-mode GaN device region and the E-mode GaN device region of the AlGaN / GaN heterojunction.

[0043] Preferably, the substrate comprises one or more of polycrystalline AlN ceramic, SiN ceramic and silicon-on-insulator. In the present embodiment, silicon-on-insulator (SOI) can be selected.

[0044] Preferably, the buffer layer comprises one or more of SiO2, Al2O3, HfO2, La2O3, ZrO2, Si3N4. In the present embodiment, SiO2may be selected.

[0045] Preferably, the gate metal comprises one or more of W, TiN, Al, Ni, Ti, Au, Mo, Pt. In the present embodiment, TiNmay be selected.

[0046] Preferably, the source metal and drain metal comprise one or more of W, TiN, Al, Ni, Ti, Au, Mo, Pt. In the present embodiment, TiNmay be selected.

[0047] Preferably, the monolithic integrated device is filled with a dielectric layer to achieve isolation of high-voltage tubes and low-voltage tubes.

[0048] Preferably, the dielectric layer comprises one or more of SiO2, Al2O3, HfO2, La2O3, ZrO2, Si3N4. In the present embodiment, SiO2may be selected.

[0049] The present embodiment also provides a preparation method of a monolithic integrated device based on a full GaN Cascode structure of NiO bonding, comprising the following steps:

[0050] (1) as shown in Figure 3 , a GaN HEMT device comprising a substrate, a buffer layer and an AlGaN / GaN heterojunction is provided;

[0051] (2) as shown in Figure 4 , a NiO gate is grown in the D-mode GaN device region of the AlGaN / GaN heterojunction;

[0052] (3) as shown in Figure 5 , a gate metal is grown above the E-mode GaN device region of the AlGaN / GaN heterojunction and the NiO gate;

[0053] (4) a source metal and a drain metal are provided on both sides of the D-mode GaN device region and the E-mode GaN device region of the AlGaN / GaN heterojunction, and a first deep groove is etched below the drain metal;

[0054] (5) as shown in Figure 6 , a second deep groove is etched between the D-mode GaN device region and the E-mode GaN device region of the AlGaN / GaN heterojunction;

[0055] (6) The source of the high-voltage tube is connected with the drain of the low-voltage tube, and the gate of the high-voltage tube is connected with the source of the low-voltage tube through a top via and an interconnection process;

[0056] (7) As shown in FIG. 7, the medium layer is filled to realize the isolation of the high-voltage tube and the low-voltage tube, and a monolithic integrated device based on the NiO bonding full-GaN Cascode structure is obtained. Figure 7

[0057] Optionally, the growth and etching of the NiO can be selected after the second deep trench etching and filling.

[0058] Preferably, the etching method in the steps (4) and (5) includes ICP or RIE, and the etching atmosphere is one or more of SF6, CHF3, BCl3, CF4, C4F8, Cl2 and He. In the embodiment, the etching method can be selected as ICP, and the etching atmosphere is SF6.

[0059] Preferably, the filling method of the medium layer in the step (7) includes one or more of chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, thermal or electron beam evaporation and sputtering. In the embodiment, the filling method can be selected as chemical vapor deposition.​

Claims

1. A monolithically integrated device based on NiO bonded all-GaN cascode structure, characterized by: The substrate includes one or more of polycrystalline AlN ceramic, SiN ceramic, silicon-on-insulator.

2. The monolithic integrated device of claim 1, wherein: The buffer layer includes one or more of SiO2, Al2O3, HfO2, La2O3, ZrO2, Si3N4.

3. The monolithic integrated device of claim 1, wherein: The gate metal includes one or more of W, TiN, Al, Ni, Ti, Au, Mo, Pt.

4. The monolithic integrated device of claim 1, wherein: The source metal and drain metal include one or more of W, TiN, Al, Ni, Ti, Au, Mo, Pt.

5. The monolithic integrated device of claim 1, wherein: The monolithic integrated device is filled with a dielectric layer to isolate the high-voltage tube from the low-voltage tube.

6. The monolithic integrated device of claim 1, wherein: The dielectric layer includes one or more of SiO2, Al2O3, HfO2, La2O3, ZrO2, Si3N4.

7. The monolithic integrated device of claim 6, wherein:

8. A method for preparing a monolithic integrated device based on a full GaN Cascode structure of NiO bonding according to any one of claims 1-7, comprising the following steps: (1) providing a GaN HEMT device including a substrate, a buffer layer, and an AlGaN / GaN heterojunction; (2) growing a NiO gate on a D-mode GaN device region of the AlGaN / GaN heterojunction; (3) growing a gate metal on an E-mode GaN device region of the AlGaN / GaN heterojunction and above the NiO gate; (4) providing a source metal and a drain metal on both sides of the D-mode GaN device region and the E-mode GaN device region of the AlGaN / GaN heterojunction, and etching a first deep trench below the drain metal; (5) etching a second deep trench between the D-mode GaN device region and the E-mode GaN device region of the AlGaN / GaN heterojunction; (6) connecting the source of the high-voltage tube to the drain of the low-voltage tube and connecting the gate of the high-voltage tube to the source of the low-voltage tube through a top via and an interconnection process; (7) filling the dielectric layer to isolate the high-voltage tube from the low-voltage tube, thereby obtaining a monolithic integrated device based on a full GaN Cascode structure of NiO bonding. The etching method in steps (4) and (5) includes ICP or RIE, and the etching atmosphere includes one or more of SF6, CHF3, BCl3, CF4, C4F8, Cl2, and He.

9. The method of claim 8, wherein: ​ 10. The method of claim 8, wherein: The filling method of the medium layer in the step (7) includes one or several of chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, thermal or electron beam evaporation, sputtering.

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